Patents Issued in August 24, 2017
  • Publication number: 20170243705
    Abstract: Disclosed are various embodiments relating to an electronic device that includes a key An electronic device may include a housing having a through-hole formed therein. A key may be exposed through the through-hole and configured to be pressed. A key switch may be located on a rear surface of the key, wherein the key structure may be configured to enable the key to be pressed and to detect the press of the key. Moreover, a structure provided on a lower portion of the housing may be able to bear a pressure exerted by a user when pressing the key in a direction opposite the housing. Further, a dummy detachably provided between the housing and the structure, wherein the dummy, when being attached, may support the key and the key switch such that both are capable of being pressed in the through-hole toward the direction of the structure.
    Type: Application
    Filed: February 17, 2017
    Publication date: August 24, 2017
    Inventors: Myung-Hyo Bae, Young-Tae Kim, Sang-Hun Park, Jin-Wan An
  • Publication number: 20170243706
    Abstract: A push switch includes: a hollow housing having an inner circumferential surface formed with a guide part; an operation button formed with a first ratchet tooth; a cam follower including a cam part, and a second ratchet tooth, and being movable up and down in an axial direction and rotatable in a circumferential direction; a first spring; an engagement piece engaged with the cam follower; a movable contact; a metallic contact member rotatable integrally with the cam follower; a fixed terminal including contacts to be switched by rotating the contact member; and a base on which the fixed terminal is fixed. The contact member defines a through hole at a rotation center of the contact member. The base includes a rotation axis part inserted in the through hole and serving as the rotation center of the contact member.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 24, 2017
    Inventors: Fumio Yoshida, Hirotaka Oohori, Kotaro Endo, Akishige Kasegawa
  • Publication number: 20170243707
    Abstract: A keyswitch includes a board, a cap, and a support device. The board has first and second bending members and a main body extending along X and Y axes perpendicular to each other. An included angle between a first abutting surface of the first bending member and the X-axis and an included angle between a second abutting surface of the second bending member and the X-axis are greater than 0°. The support device includes first and second support members having first and second hook structures respectively. When the cap is pressed, the first and second hook structures slide on the first and second abutting surfaces respectively to deform the first and second hook structures. When the cap is released, the deformed first and second hook structures drive the first and second support members to slide relatively for making the cap return to a non-pressed position.
    Type: Application
    Filed: December 27, 2016
    Publication date: August 24, 2017
    Inventor: Ling-Hsi Chao
  • Publication number: 20170243708
    Abstract: A keyboard device includes plural keycaps and a membrane switch circuit member. The membrane switch circuit member is disposed under the plural keycaps. The membrane switch circuit member includes a wiring board and plural separate covering pads. The wiring board includes plural first trace patterns and plural second trace patterns corresponding to the plural keycaps. The plural second trace patterns are disposed on the wiring board and separated from the plural first trace patterns. There is a gap between each first trace pattern and the adjacent second trace pattern. The covering pads are disposed over the wiring board. The plural covering pads are aligned with the corresponding keycaps and cover the corresponding gaps. The covering pad has a triggering trace pattern over the corresponding gap.
    Type: Application
    Filed: March 22, 2016
    Publication date: August 24, 2017
    Inventors: LEI-LUNG TSAI, YI-CHEN WANG
  • Publication number: 20170243709
    Abstract: An apparatus for controlling the electrical connection of an electrical load (2), which is arranged at a distance from the apparatus, to a control voltage source (4) which is associated with said electrical load, wherein control is performed by means of two control lines (6, 8) which bridge the physical distance between the apparatus and the load plus the control voltage source and which are connected to a control output (10, 12) of the apparatus, wherein the apparatus has a transducer (14) which detects the value of a state variable (16) of a fluid, and wherein control of the connection is performed depending on the respectively detected value of the state variable (16) exceeding and/or falling below a selectable threshold value, is characterized in that the transducer is formed by a measurement transducer (14) which converts the value of the respectively detected state variable (16) into an electrical signal (18), in that the apparatus has an electronics device (20) for evaluating said electrical signal (18
    Type: Application
    Filed: August 12, 2015
    Publication date: August 24, 2017
    Inventor: Joachim MORSCH
  • Publication number: 20170243710
    Abstract: Disclosed embodiments include an instant trip mechanism for a molded case circuit breaker. In some embodiments, the mechanism includes an adjustment dial to set a current for an instant trip operation; an instant bar provided with an upper portion contactable with the adjustment dial, a shaft portion serving as a rotation shaft, and a lower extending portion downwardly extending from the shaft portion; an electromagnet unit to generate a magnetic attraction force that is proportional to an amount of current flowing on the circuit; an armature rotatable with a lower end portion supported by a shaft, and attracted toward the electromagnet unit by the magnetic attraction force; and a spring for applying to the armature a load varying in a direction of the armature getting away from the electromagnet unit.
    Type: Application
    Filed: December 14, 2016
    Publication date: August 24, 2017
    Inventor: Kihwan OH
  • Publication number: 20170243711
    Abstract: A magnetron cooling fin has a flat plate shape in which one or a plurality of corrugated regions are formed in a body of the magnetron cooling fin to improve cooling efficiency thereof. A magnetron cooling fin in which a corrugated region processed to increase a contact area in contact with air is formed around a through-hole through which an anode unit of a magnetron passes, thereby improving cooling efficiency thereof.
    Type: Application
    Filed: February 23, 2017
    Publication date: August 24, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong Ho PARK, Hak-Jae KIM, Myoung Keun KWON, Eung Ryeol SEO, Seung Chul YANG
  • Publication number: 20170243712
    Abstract: An electron emission device includes a substrate and an electron emission layer. The electron emission layer is provided above the substrate, and is provided with an opening. The electron emission layer has an edge defining the opening and is configured to emit electrons from the edge when the edge is irradiated with light.
    Type: Application
    Filed: October 2, 2015
    Publication date: August 24, 2017
    Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Tsuyoshi ISHIKAWA, Takashi KATSUNO, Narumasa SOEJIMA
  • Publication number: 20170243713
    Abstract: A method of using a Charged Particle Microscope, comprising: A specimen holder, for holding a specimen; A source, for producing an irradiating beam of charged particles; An illuminator, for directing said beam so as to irradiate the specimen; A detector, for detecting a flux of emergent radiation emanating from the specimen in response to said irradiation, additionally comprising the following steps: In said illuminator, providing an aperture plate comprising an array of apertures; Using a deflecting device to scan said beam across said array, thereby alternatingly interrupting and transmitting the beam so as to produce a train of beam pulses; Irradiating said specimen with said train of pulses, and using said detector to perform positionally resolved (temporally discriminated) detection of the attendant emergent radiation.
    Type: Application
    Filed: December 22, 2016
    Publication date: August 24, 2017
    Applicant: FEI Company
    Inventors: Erik René Kieft, Walter van Dijk
  • Publication number: 20170243714
    Abstract: Disclosed is a method of diagnosing a conversion process for converting a format of image data including unit data corresponding to charged particle beams into a format suitable for an aperture array, the aperture array having a plurality of controllers provided to match a plurality of the charged particle beams to control the charged particle beams, and a driver configured to drive the controllers. The method includes: extracting the unit data having an identical first rank based on an arrangement of the unit data in the image data from the unit data of each block including a predetermined number of the unit data and calculating a first checksum of each of the first rank; extracting the unit data having an identical second rank after the conversion process from the unit data of each block and calculating a second checksum of each of the second rank; and comparing the first and second checksums.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 24, 2017
    Applicant: NuFlare Technology, Inc.
    Inventors: Kei HASEGAWA, Hayato KIMURA
  • Publication number: 20170243715
    Abstract: According to one embodiment, an inspection apparatus includes an irradiation device irradiating an inspection target substrate with multiple beams, a detector detecting each of a plurality of charged particle beams formed by charged particles emitted from the inspection target substrate as an electrical signal, and a comparison processing circuitry performing pattern inspection by comparing image data of a pattern formed on the inspection target substrate, the pattern being reconstructed in accordance with the detected electrical signals, and reference image data. The detector includes a plurality of detection elements that accumulate charges, and a detection circuit that reads out the accumulated charges. The plurality of detection elements are grouped into a plurality of groups.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 24, 2017
    Applicant: NuFlare Technology, Inc.
    Inventor: Munehiro OGASAWARA
  • Publication number: 20170243716
    Abstract: An inspection apparatus according to an embodiment includes an irradiation part configured to irradiate an inspection target substrate with multiple beams including energy beams, a detector, on which a plurality of charged particle beams of charged particles released from the inspection target substrate are imaged, configured to detect each of the charged particle beams as an electrical signal, and a comparing unit configured to compare reference image data and image data that is reproduced based on the detected electrical signals and that represents patterns formed on the inspection target substrate to inspect the patterns. The detector includes a plurality of detecting elements corresponding one-to-one to the charged particle beams. The detecting elements each have a size greater than a size that covers a beam blur of each charged particle beam imaged on the detector.
    Type: Application
    Filed: November 22, 2016
    Publication date: August 24, 2017
    Applicant: NuFlare Technology, Inc.
    Inventor: Munehiro OGASAWARA
  • Publication number: 20170243717
    Abstract: Provided is an assembly for inspecting the surface of a sample. The assembly includes two or more multi-beam electron column units. Each unit has: a single thermal field emitter for emitting a diverging electron beam towards a beam splitter; wherein the beam splitter includes a first multi-aperture plate having multiple apertures for creating multiple primary electron beams; a collimator lens for collimating the diverging electron beam from the emitter; an objective lens unit for focusing said multiple primary electron beams on said sample; and a multi-sensor detector system for separately detecting the intensity of secondary electron beams created by each one of said focused primary electron beams on said sample. The two or more multi-beam electron column units are arranged adjacent to each other for inspecting different parts of the surface of the sample at the same time.
    Type: Application
    Filed: September 3, 2015
    Publication date: August 24, 2017
    Inventor: Pieter KRUIT
  • Publication number: 20170243718
    Abstract: In one embodiment, A charged particle beam drawing apparatus includes an irradiation amount resetting processing circuitry changing the irradiation amount in the shot data to the irradiation amount lower limit value when the irradiation amount defined in the shot data is less than the irradiation amount lower limit value, a shot size adjustment processing circuitry changing the shot size defined in the shot data, based on an amount of the change in the irradiation amount, a shot position adjustment processing circuitry changing the shot position defined in the shot data, based on an amount of the change in the shot size, and a drawing device drawing a pattern by irradiating the substrate with the charged particle beam, using the shot data in which the irradiation amount, the shot size, and the shot position have been changed.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 24, 2017
    Applicant: NuFlare Technology, Inc.
    Inventor: Tomoo MOTOSUGI
  • Publication number: 20170243719
    Abstract: A method for generating an ion beam in an ion implantation process is provided. The method includes supplying a working gas into a first portion of an arc chamber which is separated from a second portion of the arc chamber by an intermediate plate. The method further includes guiding the working gas into the second portion of the arc chamber via a plurality of gas outlets formed at two opposite edges of the intermediate plate. The method also includes generating an ion beam from the working gas in the second portion of the arc chamber.
    Type: Application
    Filed: November 3, 2016
    Publication date: August 24, 2017
    Inventors: Tai-Kun KAO, Tsung-Min LIN, Jen-Chung CHIU
  • Publication number: 20170243720
    Abstract: Embodiments of systems and methods for a poly-phased inductively coupled plasma source are described. In an embodiment, a system may include a metal source configured to supply a metal for ionized physical vapor deposition on a substrate in a process chamber. The system may also include a high-density plasma source configured to generate a dense plasma, the high-density plasma source comprising a plurality of inductively coupled antennas. Additionally, the system may include a substrate bias source configured to provide a potential necessary to thermalize and ionize the plasma. In such embodiments, each antenna is configured to receive power at a phase orientation determined according to a phase arrangement.
    Type: Application
    Filed: March 29, 2016
    Publication date: August 24, 2017
    Inventor: Jozef Brcka
  • Publication number: 20170243721
    Abstract: Plasma processing apparatus and methods are disclosed. Embodiments of the present disclosure include a processing chamber having an interior space operable to receive a process gas, a substrate holder in the interior of the processing chamber operable to hold a substrate, and at least one dielectric window. A metal shield is disposed adjacent the dielectric window. The metal shield can have a peripheral portion and a central portion. The processing apparatus includes a primary inductive element disposed external to the processing chamber adjacent the peripheral portion of the metal shield. The processing apparatus can further include a secondary inductive element disposed between the central portion of the metal shield and the dielectric window. The primary and secondary inductive elements can perform different functions, can have different structural configurations, and can be operated at different frequencies.
    Type: Application
    Filed: May 8, 2017
    Publication date: August 24, 2017
    Inventors: Vladimir Nagorny, Dongsoo Lee, Andreas Kadavanich
  • Publication number: 20170243722
    Abstract: A charge volume configuration for use in delivery of gas to a reactor for processing semiconductor wafers is provided. A charge volume includes a chamber that extends between a proximal end and a distal end. A base connected to the proximal end of the chamber, and the base includes an inlet port and an outlet port. A tube is disposed within the chamber. The tube has a tube diameter that is less than a chamber diameter. The tube has a connection end coupled to the inlet port at the proximal end of the chamber and an output end disposed at the distal end of the chamber.
    Type: Application
    Filed: February 23, 2016
    Publication date: August 24, 2017
    Inventor: Karl Leeser
  • Publication number: 20170243723
    Abstract: A radio-frequency (RF) generator is provided that produces a controlled overshoot. One embodiment includes a RF power amplifier and a direct-current (DC) power supply that includes a primary DC power supply, an auxiliary DC power supply, a half-bridge circuit, and a control circuit. The half-bridge circuit, in a first switching state, electrically connects, in series, the auxiliary DC power supply with the primary DC power supply and, in a second switching state, electrically disconnects the auxiliary DC power supply from the primary DC power supply. The control circuit places the half-bridge circuit in the first switching state for a first period of time and places the half-bridge circuit in the second switching state for a second period of time to produce a controlled overshoot in the power produced by the RF generator throughout the first period of time.
    Type: Application
    Filed: January 25, 2017
    Publication date: August 24, 2017
    Inventor: Gideon Van Zyl
  • Publication number: 20170243724
    Abstract: Embodiments of showerheads having a detachable gas distribution plate are provided herein. In some embodiments, a showerhead for use in a semiconductor processing chamber may include a body having a first side and a second side; a gas distribution plate disposed proximate the second side of the body and having an annular channel formed in a side surface; and a clamp disposed about a peripheral edge of the gas distribution plate to removably couple the gas distribution plate to the body, wherein the clamp includes a body and a protrusion extending radially inward into the annular groove, and wherein a portion of the gas distribution plate extends over a bottom surface of the clamp.
    Type: Application
    Filed: January 26, 2017
    Publication date: August 24, 2017
    Inventors: Hamid Noorbakhsh, Xiaoping Zhou
  • Publication number: 20170243725
    Abstract: In a plasma processing apparatus, insulating members are horizontally and separately arranged above a mounting unit in a processing chamber. Each insulating member serves as a partition between a vacuum atmosphere in the processing chamber and an external atmosphere of the processing chamber. Antennas are provided on the respective insulating members to generate an inductively coupled plasma. A first processing gas is supplied into the processing chamber and adsorbed onto a substrate on the mounting unit. A second processing gas is turned into a plasma by power supplied from the antennas and is supplied to activate the first processing gas adsorbed onto the substrate or react with the first processing gas adsorbed onto the substrate. The supply of the first processing gas and the supply of the second processing gas are alternately repeated multiple times with a process of evacuating an inside of the processing chamber interposed therebetween.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 24, 2017
    Inventors: Ryoji YAMAZAKI, Susumu SAITO, Koichi NAGAKURA, Akitaka SHIMIZU, Hidetoshi KINOSHITA
  • Publication number: 20170243726
    Abstract: A method for manufacturing an arrestor for an electrostatic chuck includes printing first layers of an arrestor for an electrostatic chuck using a 3-D printer and an electrically non-conductive material. The first layers of the arrestor at least partially define a first opening to a gas flow channel. The method includes printing intermediate layers of the arrestor using the 3-D printer and the electrically non-conductive material. The intermediate layers of the arrestor at least partially define the gas flow channel. The method includes printing second layers of the arrestor using the 3-D printer and the electrically non-conductive material. The second layers of the arrestor at least partially define a second opening of the gas flow channel. At least one of the first opening, the second opening and/or the gas flow channel of the arrestor is arranged to prevent a direct line of sight between the first opening and the second opening of the arrestor.
    Type: Application
    Filed: February 18, 2016
    Publication date: August 24, 2017
    Inventor: Michael Kellogg
  • Publication number: 20170243727
    Abstract: An atmospheric pressure pulsed arc plasma source and method of using including a housing having a housing opening therein; an insulator tube having an insulator tube opening therein, retained within the housing opening; and a conductive tube, retained within the insulator tube opening. A nozzle is retained by the housing. A feed path is defined in the conductive tube and the nozzle and a gas feed port is operatively coupled to the feed path. Feedstock is provided in the feed path and electrically coupled to the conductive tube. A pulsed DC power source provides a pulsed voltage to the conductive tube. The plasma source emits a discharge stream having a temperature that is less than 50° C. from the nozzle and a coating is formed on a substrate.
    Type: Application
    Filed: February 18, 2016
    Publication date: August 24, 2017
    Inventors: Vasiliki Zorbas POENITZSCH, Ronghua WEI, Edward LANGA, Kent E. COULTER
  • Publication number: 20170243728
    Abstract: A method of analyzing molecules, comprising: generating ions from a sample of molecules; cooling the generated ions below ambient temperature; fragmenting at least some of the cooled ions by irradiating the ions with light at a plurality of different wavelengths (?) within one or more predetermined spectral intervals; recording a fragment mass spectrum of the fragmented ions comprising a detected signal (I) versus m/z over a predetermined range of m/z values for each of the plurality of different wavelengths (?), thereby recording a two dimensional dependency of the detected signal (I) on m/z and irradiation wavelength (?); and determining from the recorded two dimensional dependency an identity of at least one of the generated ions and/or relative abundances of different generated ions and thereby determining an identity of at least of one of the molecules and/or relative abundances of different molecules in the sample.
    Type: Application
    Filed: October 13, 2015
    Publication date: August 24, 2017
    Inventors: Alexander MAKAROV, Oleg BOYARKINE, Vladimir KOPYSOV
  • Publication number: 20170243729
    Abstract: A method of ionising a sample is provided, comprising providing a fluid sample, wherein the fluid sample contains an analyte, applying one or more pulses of acoustic energy to the fluid sample to cause a spray of the fluid sample to eject from the surface of the fluid sample, and applying an AC, RF or alternating voltage to the fluid sample using an electrode.
    Type: Application
    Filed: October 16, 2015
    Publication date: August 24, 2017
    Inventors: Michael Raymond MORRIS, Steven Derek PRINGLE, Richard ELLSON, Richard STEARNS, Lars MAJLOF, Ian SINCLAIR
  • Publication number: 20170243730
    Abstract: An ion beam irradiation apparatus is provided. The apparatus includes an ion source, a mass separator, and an energy filter. The mass separator sorts dopant ions having a specific mass number and valence from an ion beam extracted from the ion source, and outputs the dopant ions. The energy filter is formed to define a beam passing region for allowing the ion beam to pass therethrough, and configured to have a given filter potential in response to application of a voltage thereto to separate passable ions capable of passing through the beam passing region and non-passable ions incapable of passing through the beam passing region, from each other by a difference in ion energy. The given filter potential is set such that the dopant ions are included in the passable ions, and a portion of unwanted ions which cannot be separated from the dopant ions by the mass separator are included in the non-passable ions.
    Type: Application
    Filed: October 28, 2016
    Publication date: August 24, 2017
    Applicant: NISSIN ION EQUIPMENT CO., LTD.
    Inventors: Naoya TAKAHASHI, Hideki FUJITA, Yosuke YOSHIMURA, Shigeki SAKAI
  • Publication number: 20170243731
    Abstract: Systems and methods are discussed to create radiation from one or more compact toroids. Compact toroids can be created from plasma of gases within a confinement chamber using a plurality of coils of various densities of windings. High current pulses can be generated within the coil and switched at high frequencies to repeatedly generate compact toroids within the plasma. The plasma can produce radiation at various wavelengths that is focused toward a target or an intermediate focus.
    Type: Application
    Filed: May 8, 2017
    Publication date: August 24, 2017
    Inventors: Timothy Ziemba, Kenneth E. Miller, John G. Carscadden, James Prager, Angus Macnab
  • Publication number: 20170243732
    Abstract: Providing a manufacture method of a gate insulating film formed on an SiC substrate having thereon an SiON film, achieving both of the maintenance of an SiON film structure and the formation of a high-quality insulating film. A manufacture method of a gate insulating film for an SiC semiconductor device comprises preparing a transfer plate comprising a transfer substrate and an insulating film formed thereon; preparing a surface-processed substrate comprising an SiC substrate and an epitaxial silicon acid nitride film as an atomic monolayer formed thereon; and transferring the insulating film from the transfer plate onto the silicon acid nitride film of the surface-processed substrate to produce the surface-processed substrate having a transferred insulating film.
    Type: Application
    Filed: January 4, 2017
    Publication date: August 24, 2017
    Inventors: Takuro Inamoto, Takeshi Fujii, Mariko Sato
  • Publication number: 20170243733
    Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a wafer stage that is operable to secure and rotate a wafer; a polish head configured to polish a backside surface of the wafer; an air bearing module configured to apply an air pressure to a front surface of the wafer; and an edge sealing unit configured to seal edges of the wafer.
    Type: Application
    Filed: February 24, 2016
    Publication date: August 24, 2017
    Inventors: Chih-Hung Chen, Chia-Jung Hsu, Yi-An Lin
  • Publication number: 20170243734
    Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventors: Dai Ishikawa, Atsuki Fukazawa
  • Publication number: 20170243735
    Abstract: A substrate processing apparatus includes a driving magnet that is disposed correspondingly to a movable pin and that has a predetermined polar direction with respect to a radial direction of a rotary table, a pressing magnet that has a magnetic pole that gives an attractive magnetic force or a repulsive magnetic force between the driving magnet and the pressing magnet and that presses a support portion against a peripheral edge of a substrate by urging the support portion toward a contact position by means of the attractive magnetic force or the repulsive magnetic force, and a pressing-force changing unit that changes a magnitude of a pressing force against the peripheral edge of the substrate pressed by the support portion while keeping the magnitude higher than zero in response to rotation of the rotary table.
    Type: Application
    Filed: February 2, 2017
    Publication date: August 24, 2017
    Inventors: Hiromichi KABA, Akihiko TAKI, Tomomi IWATA, Toru EDO, Kunio YAMADA
  • Publication number: 20170243736
    Abstract: A substrate treatment method is provided, which includes: an organic solvent replacing step of supplying an organic solvent, whereby a liquid film of the organic solvent is formed on the substrate as covering the upper surface of the substrate to replace a rinse liquid with the organic solvent; a substrate temperature increasing step of allowing the temperature of the upper surface of the substrate to reach a first temperature level higher than the boiling point of the organic solvent after the formation of the organic solvent liquid film, whereby a vapor film of the organic solvent is formed below the entire organic solvent liquid film between the organic solvent liquid film and the substrate to levitate the organic solvent liquid film above the organic solvent vapor film; and an organic solvent removing step of removing the levitated organic solvent liquid film from above the upper surface of the substrate.
    Type: Application
    Filed: May 5, 2017
    Publication date: August 24, 2017
    Inventors: Kenji KOBAYASHI, Manabu OKUTANI
  • Publication number: 20170243737
    Abstract: Disclosed is a method for manufacturing a semiconductor device, including a step of yielding a pattern 2a of a polysiloxane-containing composition over a substrate 1, and a step of forming an ion impurity region 6 in the substrate, wherein, after the step of forming an ion impurity region, the method further includes a step of firing the pattern at a temperature of 300 to 1,500° C. This method makes it possible that after the formation of the ion impurity region in the semiconductor substrate, the pattern 2a of the polysiloxane-containing composition is easily removed without leaving any residual. Thus, the yield in the production of a semiconductor device can be improved and the tact time can be shortened.
    Type: Application
    Filed: March 18, 2015
    Publication date: August 24, 2017
    Applicant: Toray Industries, Inc.
    Inventors: Yugo Tanigaki, Takenori Fujiwara
  • Publication number: 20170243738
    Abstract: A processing method in one embodiment includes: a step that takes an image of the end face of a reference substrate, whose warp amount is known, over the whole periphery thereof using a camera to obtain shape data of the end face of the reference substrate over the whole periphery of the reference substrate; a step that takes an image of the end face of a substrate over the whole periphery thereof using a camera to obtain shape data of the end face of the substrate over the whole periphery of the substrate; a step that calculates warp amount of the substrate based on the obtained shape data; a step that forms a resist film on a surface of the substrate; a step that determines the supply position from which an organic solvent is to be supplied to a peripheral portion of the resist film and dissolves the peripheral portion by the solvent supplied from the supply position to remove the same from the substrate.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 24, 2017
    Applicant: Tokyo Electron Limited
    Inventors: Yasuaki NODA, Tadashi NISHIYAMA
  • Publication number: 20170243739
    Abstract: According to various aspects and embodiments, a system and method for forming a packaged electronic device is disclosed. One example of the method comprises treating a surface of a first substrate to create a first surface having a low bond strength, at least a portion of the first surface defined by at least one three-dimensional structure and a layer of optical masking material, depositing a layer of structure material onto at least a portion of the first surface, bonding a second substrate to at least a portion of the layer of structure material, and separating the first substrate from the second substrate along the first surface.
    Type: Application
    Filed: February 23, 2017
    Publication date: August 24, 2017
    Inventors: Bradley Paul Barber, Kezia Cheng
  • Publication number: 20170243740
    Abstract: The invention provides the use of at least one binary group 15 element compound of the general formula R1R2E-E?R3R4 (I) or R5E(E?R6R7)2 (II) as the educt in a vapor deposition process. In this case, R1, R2, R3 and R4 are independently selected from the group consisting of H, an alkyl radical (C1-C10) and an aryl group, and E and E? are independently selected from the group consisting of N, P, As, Sb and Bi. This use excludes hydrazine and its derivatives. The binary group 15 element compounds according to the invention allow the realization of a reproducible production and/or deposition of multinary, homogeneous and ultrapure 13/15 semiconductors of a defined combination at relatively low process temperatures. This makes it possible to completely waive the use of an organically substituted nitrogen compound such as 1.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 24, 2017
    Applicant: Philipps-Universität Marburg
    Inventors: Carsten VON HAENISCH, Kerstin VOLZ, Wolfgang STOLZ, Eduard STERZER, Andreas BEYER, Dominik KEIPER, Benjamin RINGLER
  • Publication number: 20170243741
    Abstract: A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.
    Type: Application
    Filed: May 9, 2017
    Publication date: August 24, 2017
    Inventors: Jae-Duk LEE, Young-Woo PARK
  • Publication number: 20170243742
    Abstract: A method of forming a silicon film, a germanium film or a silicon germanium film on a target substrate having a fine recess formed on a surface of the target substrate by a chemical vapor deposition method includes placing the target substrate having the fine recess in a processing container, and supplying a film forming gas containing an element constituting a film to be formed and a chlorine-containing compound gas into the processing container. Adsorption of the film forming gas at an upper portion of the fine recess is selectively inhibited by the chlorine-containing compound gas.
    Type: Application
    Filed: February 20, 2017
    Publication date: August 24, 2017
    Inventors: Kazuya TAKAHASHI, Mitsuhiro OKADA, Katsuhiko KOMORI
  • Publication number: 20170243743
    Abstract: Lift-off methods for fabricating metal line patterns on a substrate are provided. For example, a method to fabricate a device includes forming a sacrificial layer on a substrate and forming a photoresist mask over the sacrificial layer, isotropically etching a portion of the sacrificial layer exposed through an opening of the photoresist mask to form an undercut region in the sacrificial layer below the photoresist mask, wherein the undercut region defines an overhang structure, and anisotropically etching a portion of the sacrificial layer exposed through the opening of the photoresist mask to form an opening through the sacrificial layer down to the substrate. Metallic material is deposited to cover the photoresist mask and to at least partially fill the opening formed in the sacrificial layer without coating the overhang structure with metallic material. The sacrificial layer is dissolved to lift-off the metallic material covering the photoresist mask.
    Type: Application
    Filed: May 10, 2017
    Publication date: August 24, 2017
    Inventors: Guy M. Cohen, Sebastian U. Engelmann, Steve Holmes, Jyotica V. Patel
  • Publication number: 20170243744
    Abstract: Provided is a method of trimming an inorganic resist in an integration scheme, the method comprising: disposing a substrate in a process chamber, the substrate having an inorganic resist layer and an underlying layer comprising an oxide layer, a silicon nitride layer, and a base layer, the inorganic resist layer having an inorganic structure pattern; performing an inorganic resist trimming process to selectively remove a portion of the inorganic resist structure pattern on the substrate, the trimming process using a first etchant gas mixture and generating a first pattern; controlling selected two or more operating variables of the integration scheme in order to achieve target integration objectives; wherein the first etchant gas mixture comprises a fluorine-containing gas and a diluent gas; and wherein the target integration objectives include a target critical dimension (CD), a target line edge roughness (LER), a target line width roughness (LWR) and a target substrate throughput.
    Type: Application
    Filed: August 9, 2016
    Publication date: August 24, 2017
    Inventors: Vinh Luong, Akiteru Ko
  • Publication number: 20170243745
    Abstract: Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
    Type: Application
    Filed: May 9, 2017
    Publication date: August 24, 2017
    Inventor: Hamza Yilmaz
  • Publication number: 20170243746
    Abstract: Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
    Type: Application
    Filed: May 9, 2017
    Publication date: August 24, 2017
    Inventor: Hamza Yilmaz
  • Publication number: 20170243747
    Abstract: A method for implanting ions into a semiconductor substrate includes performing a test implantation of ions into a semiconductor substrate. The ions of the test implantation are implanted with a first implantation angle range over the semiconductor substrate. Further, the method includes determining an implantation angle offset based on the semiconductor substrate after the test implantation and adjusting a tilt angle of the semiconductor substrate with respect to an implantation direction based on the determined implantation angle offset. Additionally, the method includes performing at least one target implantation of ions into the semiconductor substrate after the adjustment of the tilt angle. The ions of the at least one target implantation are implanted with a second implantation angle range over the semiconductor substrate. Further, the first implantation angle range is larger than the second implantation angle range.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 24, 2017
    Inventors: Michael Brugger, Moriz Jelinek, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder
  • Publication number: 20170243748
    Abstract: Methods for forming a gate structure of a circuit structure are provide. The methods for forming the gate structure may include: forming a first gate pattern in a gate mask layer, the forming including a first etching of rounded corner portions of the first gate pattern; forming a second gate pattern in the gate mask layer, the second gate pattern at least partially overlapping the first gate pattern, the forming including a second etching of rounded corner portions of the second gate pattern; and, etching the gate mask layer using the first gate pattern and second gate pattern to form the gate structure.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 24, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xintuo DAI, Jiong LI
  • Publication number: 20170243749
    Abstract: A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H2O2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.
    Type: Application
    Filed: February 22, 2016
    Publication date: August 24, 2017
    Inventors: Chueh-Yang Liu, Chun-Wei Yu, Yu-Ying Lin, Yu-Ren Wang
  • Publication number: 20170243750
    Abstract: Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a MISFET is formed. At this time, over the semiconductor substrate located in the memory cell region, a control gate electrode and a memory gate electrode each for the memory cell are formed first. Then, an insulating film is formed so as to cover the control gate electrode and the memory gate electrode. Subsequently, the upper surface of the insulating film is polished to be planarized. Thereafter, a conductive film for the gate electrode of the MISFET is formed and then patterned to form a gate electrode or a dummy gate electrode for the MISFET in the peripheral circuit region.
    Type: Application
    Filed: May 11, 2017
    Publication date: August 24, 2017
    Inventor: Masaaki SHINOHARA
  • Publication number: 20170243751
    Abstract: A method of metal-assisted chemical etching comprises forming an array of discrete metal features on a surface of a semiconductor structure, where each discrete metal feature comprises a porous metal body with a plurality of pores extending therethrough and terminating at the surface of the semiconductor structure. The semiconductor structure is exposed to an etchant, and the discrete metal features sink into the semiconductor structure as metal-covered surface regions are etched. Simultaneously, uncovered surface regions are extruded through the pores to form anchoring structures for the discrete metal features. The anchoring structures inhibit detouring or delamination of the discrete metal features during etching. During continued exposure to the etchant, the anchoring structures are gradually removed, leaving an array of holes in the semiconductor structure.
    Type: Application
    Filed: February 24, 2017
    Publication date: August 24, 2017
    Inventors: Xiuling Li, Jeong Dong Kim, Munho Kim, Lingyu Kong
  • Publication number: 20170243752
    Abstract: Provided is a polishing composition which is capable of sufficiently suppressing a polishing speed for a low relative permittivity material. Disclosed is a polishing composition to be used for polishing a material having a relative permittivity of 4 or less, the polishing composition including abrasive grains and an organic compound, the organic compound having a polyoxyalkylene group and an aliphatic hydrocarbon group containing three or more carbon atoms.
    Type: Application
    Filed: July 30, 2015
    Publication date: August 24, 2017
    Applicant: FUJIMI INCORPORATED
    Inventor: Akihito YASUI
  • Publication number: 20170243753
    Abstract: There is disclosed a substrate processing method for etching a substrate on which a first and a second silicon oxide layer having different film qualities are formed side by side. The substrate processing method includes: a first etching step of supplying a halogen-containing gas that is not activated to the substrate and sublimating reaction by-products generated by reaction between the halogen-containing gas and the first and the second silicon oxide layer; and a second etching step of etching the substrate by radicals generated by activating the halogen-containing gas.
    Type: Application
    Filed: February 23, 2017
    Publication date: August 24, 2017
    Inventors: Muneyuki IMAI, Satoshi TODA
  • Publication number: 20170243754
    Abstract: Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.
    Type: Application
    Filed: January 4, 2017
    Publication date: August 24, 2017
    Inventors: Aurelien TAVERNIER, Qingjun ZHOU, Tom CHOI, Yungchen LIN, Ying ZHANG, Olivier JOUBERT