Abstract: Embodiments of the invention provide a method for atomic layer etching (ALE) of a substrate. According to one embodiment, the method includes providing a substrate, and alternatingly exposing the substrate to a fluorine-containing gas and an aluminum-containing gas to etch the substrate. According to one embodiment, the method includes providing a substrate containing a metal oxide film, exposing the substrate to a fluorine-containing gas to form a fluorinated layer on the metal oxide film, and thereafter, exposing the substrate to an aluminum-containing gas to remove the fluorinated layer from the metal oxide film. The exposing steps may be alternatingly repeated at least once to further etch the metal oxide film.

Abstract: The present invention is a plasma etching method that is implemented under plasma conditions using a process gas, wherein at least one gas selected from a hydrofluoroether represented by a formula (I) is used as the process gas, wherein R represents a hydrogen atom or a fluoroalkyl group represented by CnF2n+1, and m and n represent integers that satisfy 1?m?3 and 3?(m+n)?4. This plasma etching method can implement high etching selectivity with respect to silicon nitride, silicon, and an organic material while achieving a sufficiently high etching rate without using oxygen and hydrogen when etching silicon oxide.

Abstract: Methods and systems for cyclic etching of a patterned layer are described. In an embodiment, a method includes receiving a substrate comprising an underlying layer, a mask layer that exposes portions of an intermediate layer that is disposed between the underlying layer and the mask layer. An embodiment may also include forming a first layer on the mask layer and a second layer on the exposed portions of the intermediate layer, the first layer and the second layer being concurrently formed. Additionally, the method may include removing, concurrently, the first layer and the second layer from the substrate. In such embodiments, the method may include alternating between the forming and the removing until portions of the underlying layer are exposed.

Abstract: Methods include exposing polysilicon to an aqueous composition comprising nitric acid, poly-carboxylic acid and ammonium fluoride, and removing a portion of the polysilicon selective to an oxide using the aqueous composition.

Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.

Abstract: In a method of manufacturing a semiconductor device, a first layer containing a Si1-xGex layer doped with phosphorous is formed over an n-type semiconductor layer, a metal layer containing a metal material is formed over the first layer, and a thermal process is performed to form an alloy layer including Si, Ge and the metal material.

Abstract: A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.

Abstract: Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.

Abstract: A support substrate, a method of manufacturing a semiconductor package, and a semiconductor package, the support substrate including a first plate; a second plate on the first plate; and an adhesive layer between the first plate and the second plate, wherein a coefficient of thermal expansion (CTE) of the adhesive layer is higher than a CTE of the first plate and higher than a CTE of the second plate.

Abstract: A substrate processing apparatus, including: a process chamber configured to process substrates; a substrate mounting stand installed in the process chamber and configured to support the substrates along a circumferential direction; a rotating unit configured to rotate the substrate mounting stand; a first gas supply unit configured to supply a first gas from above the substrate mounting stand; a second gas supply unit configured to supply a second gas from above the substrate mounting stand; a third gas supply unit configured to supply a cleaning gas from above the substrate mounting stand; and an elevating unit configured to maintain the substrate mounting stand at a substrate processing position while supplying the first gas and the second gas and also configured to maintain the substrate mounting stand at a cleaning position while supplying the cleaning gas.

Abstract: A plasma processing method which performs plasma processing on a sample by a plurality of steps includes a first step of stopping supply of gas of one step while supplying an inert gas and a second step stopping the supply of the inert gas of the first step while as supplying a gas of the other step after the first step. An amount of the gas of the one step remaining inside a process chamber in which the sample is plasma-processed is detected in the first step. An amount of the gas of the other step reached inside the process chamber is detected in the second step. The one step is switched to the other step based on the amount of the gas of the one step detected in the first step and the amount of the gas of the other step detected in the second step.

Abstract: A miniature wafer processing apparatus includes a first half portion, a second half portion, a gas supply unit, a liquid supply unit, a ring sealing member disposed at peripheries of the first half portion and the second half portion, and a liquid recycling member. The first half portion includes a first hole disposed at a work platform. The second half portion includes an upper cover correspondingly covering the work platform to form a processing chamber, and a second hole disposed at the upper cover. The gas supply unit and the liquid supply unit are in communication with the first hole and the second hole. The liquid recycling member includes a recycling tube, a discharging tube and a filtering portion. With the first half portion and the second half portion, the processing chamber and the overall volume can be reduced.

Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

Abstract: A wet etching apparatus includes a wet bench; a tank, which is set in the wet bench and is movable in the wet bench in an upper position and a lower position; a conveyor, which includes a plurality of rollers arranged in the wet bench in such a way that the tank surrounds the plurality of rollers; and a supply line, which supplies an etchant into the tank located in the lower position. The tank is movable by cylinders arranged at two ends of a bottom of the tank to selectively move the tank between a lower position and an upper position. The rollers of the conveyor convey a substrate into the tank such that when the tank is moved to the upper position, the etchant supplied into to tank is raised to completely cover the substrate so as to have the substrate completely immersed in the etchant.

Abstract: A semiconductor structure bonding apparatus is disclosed. The apparatus may include a leveling adjustment system configured to provide leveling adjustment of upper and lower block assemblies of the apparatus. In some cases, the leveling adjustment system may include a plurality of threaded posts, differentially threaded adjustment collars, and leveling sleeves. In some instances, the leveling adjustment system further may include a plurality of preload springs configured to provide a given preload capacity and range of adjustment. In some instances, the leveling adjustment system further may include a load cell through which one of the threaded posts may be inserted. In some embodiments, the upper block assembly further may include a reaction plate configured to reduce deformation of the upper block assembly. In some embodiments, the upper block assembly further may include a thermal isolation plate configured to provide compliance deflection and being of monolithic or polylithic construction, as desired.

Abstract: A semiconductor wafer held by a holder within a chamber is irradiated and heated with halogen light emitted from multiple halogen lamps. Cylindrical outer and inner louvers made of opaque quartz are provided between the halogen lamps and the semiconductor wafer. A reflector is provided in an area of tube walls of the halogen lamps that faces the spacing between the inner wall surface of the outer louver and the outer wall surface of the inner louver. The spacing between the two louvers is located immediately below and faces the peripheral portion of the semiconductor wafer. Thus, the illuminance of light that reaches the peripheral portion of the semiconductor wafer where a temperature drop is likely to occur will be higher than the illuminance of light that travels toward the central portion from the halogen lamps. This configuration will help make uniform the in-plane temperature distribution of the semiconductor wafer.

Abstract: A semiconductor wafer held by a holder within a chamber is irradiated and heated with halogen light emitted from multiple halogen lamps. A cylindrical louver made of opaque quartz and a light-shielding member of a ring shape having a cut-out portion are provided between the halogen lamps and the semiconductor wafer. When the semiconductor wafer is heated with the light emitted from the halogen lamps, a shadow region will appear in the semiconductor wafer as a result of the louver blocking off the emitted light. However, in the presence of the cut-out portion of the light-shielding member, the light emitted from the halogen lamps will reach the shadow region through the cut-out portion. This configuration allows the shadow region to be heated in the same manner as the other regions, and accordingly will help make uniform the in-plane temperature distribution of the semiconductor wafer during light irradiation heating.

Abstract: A transfer apparatus includes: a body portion; and an adhesive portion connected to the body portion, with which a point light source of a display apparatus is attachable to and detachable from the transfer apparatus by contact therewith. The adhesive portion is defined by a plurality of surfaces in different planes from each other.

Abstract: A method of transferring light-emitting diodes including picking up the light-emitting diodes from a base substrate by using a first stamper; rotating the light-emitting diodes by about 90 degrees and arranging the light-emitting diodes over the first stamper or a sacrificial substrate; picking up the rotated light-emitting diodes arranged over the first stamper or the sacrificial substrate by using a second stamper; and releasing the light-emitting diodes from the second stamper towards a display substrate.

Abstract: Methods and apparatus for forming porous silicon layers are provided. In some embodiments, an anodizing bath includes: a housing having a first volume to hold a chemical solution; a cathode disposed within the first volume at a first side of the housing; an anode disposed within the first volume at a second side of the housing, opposite the first side, wherein a face of each of the cathode and the anode have a given surface area; a substrate holder configured to retain a plurality of substrates along a perimeter thereof within the first volume in a plurality of substrate holding positions, a plurality of vent openings fluidly coupled to the first volume to release process gases, wherein a top of each of the plurality of vent openings are disposed above a chemical solution fill level in the first volume.

Abstract: An overhead transport vehicle includes a vibration-proof portion disposed between a belt and a lift device. The vibration-proof portion includes a first connection mechanism disposed on a side where a first load acts in a width direction perpendicular or substantially perpendicular to both a travelling direction and a lifting direction of the lift device, and a second connection mechanism disposed on a side where a second load larger than the first load acts in the width direction, and which has a larger repulsive force than that of the first connection mechanism.

Abstract: A container is placed at a predetermined position on a purge device to prevent the container from getting caught on a nozzle. When the container is lowered and placed on the purge device, the two facing sides of the front end of the container's bottom surface and the front end of a recessed part, and the two facing sides of both left and right side ends of the container's bottom surface are guided by a front guide, side guides and a center guide. Following that, the nozzle is brought into contact with the bottom surface of the container.

Abstract: In one embodiment, a plasma processing apparatus includes an electrostatic chuck configured to hold a substrate. The apparatus further includes a surrounding member holder configured to hold a surrounding member that surrounds an edge portion of the substrate. The apparatus further includes a plasma feeder configured to feed plasma for processing the substrate to a side of a first face of the substrate. The apparatus further includes a gas feeder configured to feed a gas to a space between the edge portion of the substrate and the surrounding member by discharging the gas to a side of a second face of the substrate from a gas hole provided on a side face of the electrostatic chuck or a gas hole provided in the surrounding member.

Abstract: An electrostatic chuck device that adsorbs a plate-like specimen with an electrostatic adsorption electrode and cools the plate-like specimen, including an electrostatic chuck portion, a forming material of which is a ceramic sintered body, and that has one main surface that is a placement surface on which the plate-like specimen is placed, in which a plurality of protrusions supporting the plate-like specimen are provided on the placement surface, the protrusion has a top surface that is in contact with the plate-like specimen and supports the plate-like specimen, and has a cross-sectional area that gradually increases vertically downward from a height position of the top surface, and a cross-sectional area at a distance 0.6 ?m vertically downward from a lower end of the top surface of the protrusion is 110% or less of a cross-sectional area of a lower end of the top surface.

Abstract: A method and apparatus for planarizing a substrate are provided. A substrate carrier head with an improved cover for holding the substrate securely is provided. The cover may have a bead that is larger than the recess into which it fits, such that the compression forms a conformal seal inside the recess. The bead may also be left uncoated to enhance adhesion of the bead to the surface of the groove. The surface of the cover may be roughened to reduce adhesion of the substrate to the cover without using a non-stick coating.

Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.

Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

Abstract: One illustrative method disclosed includes forming an isolation structure so as to define first and second active regions on the SOI substrate, forming a field effect transistor above the first active region and forming an opening in the second active region that exposes an upper surface of the bulk semiconductor layer in the second active region. In this example, the method further includes performing a common epitaxial growth process so as to form an epi semiconductor material region above each of the source/drain regions of the transistor and to form a unitary epi semiconductor structure above the second active region, wherein the unitary epi semiconductor structure is formed on and in contact with the exposed upper surface of the bulk semiconductor layer within the opening and on and in contact with an upper surface of the active layer in the second active region.

Abstract: Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.

Abstract: Techniques relate to forming an integrated circuit. Trench contacts are formed on top of at least one source and drain of an intermediate structure. An interlayer dielectric is formed on top of the intermediate structure. A trench is cut through the interlayer dielectric, through at least one of the trench contacts, down to a shallow trench isolation area. The trench is filled with a filling material. Upper contacts are formed on top of the trench contacts in the interlayer dielectric. A first metal layer pattern is patterned such that a separation is formed by a filling material width of the filling material. First metal layers are formed according to the first metal layer pattern, where tips of the first metal layers are aligned to the filling material that fills the trench, such that the tips of the first metal layers are separated by the filling material width.

Abstract: A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a liquid is provided on a selected portion of the wafer to selectively alter at least one circuit element within the at least one of the plurality of semiconductor device structures.

Abstract: Disclosed herein is a wafer processing method for dividing a wafer into individual device chips along division lines. The wafer processing method includes a frame supporting step of attaching the wafer to an adhesive tape fixed at its peripheral portion to an annular frame, thereby supporting the wafer through the adhesive tape to the annular frame, a laser processing step of applying a laser beam to each division line to thereby form a strength reduced portion along each division line, and a dividing step of applying a radial tension to the adhesive tape and next applying an external force to the wafer in the condition where the radial tension is kept acting on the adhesive tape, thereby dividing the wafer into the individual device chips along the division lines.

Abstract: A processing method of processing a workpiece on which a plurality of intersecting planned dividing lines are set is provided. The processing method includes a holding step of holding the workpiece by a holding table, a dividing step of forming a plurality of chips by dividing the workpiece held by the holding table along the planned dividing lines, and a carrying-out step of, after the dividing step is performed, sucking the plurality of chips on the holding table by a suction unit including a suction head sucking the plurality of chips and a suction passage connected to the suction head, and carrying out the plurality of chips from the holding table via the suction passage.

Abstract: Disclosed herein is a technique for providing a layout structure for a semiconductor integrated circuit with SOI transistors with an antenna error that could occur in a buried insulator under a source or drain taken into account.

Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

Abstract: A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is formed above the plurality of fins and the plurality of gate structures. The first mask layer has at least one fin cut opening and at least one gate cut opening defined therein. A first portion of a first fin of the plurality of fins disposed below the fin cut opening is removed to define a fin cut cavity. A second portion of a first gate structure of the plurality of gate structures disposed below the gate cut opening is removed to define a gate cut cavity. An insulating material layer is concurrently formed in at least a portion of the fin cut cavity and the gate cut cavity.

Abstract: One illustrative method disclosed herein includes forming a gate structure above a portion of a fin and performing a first epitaxial growth process to form a silicon-carbide (SiC) semiconductor material above the fin in the source and drain regions of a FinFET device. In this example, the method also includes performing a heating process so as to form a source/drain graphene contact from the silicon-carbide (SiC) semiconductor material in both the source and drain regions of the FinFET device and forming first and second source/drain contact structures that are conductively coupled to the source/drain graphene contact in the source region and the drain region, respectively, of the FinFET device.

Abstract: A semiconductor device includes a substrate structure, multiple fins protruding from the substrate structure, each of the fins having a first portion, a second portion on opposite sides of the first portion, and a third portion at an outer side of the first portion and adjacent to the second portion, a gate structure on the upper surface of the first portion, sidewall spacers on opposite sides of the gate structure and covering the upper surface of the second portion, and source and drain regions outside of the sidewall spacers. The source and drain regions each have an upper surface higher than the second portion upper surface. The first portion protrudes from the second portion. The upper surface of the second portion is lower than the first portion upper surface. The upper surface of the third portion is lower than the second portion upper surface.

Abstract: According to an embodiment, a micro-fabricated test structure includes a structure mechanically coupled between two rigid anchors and disposed above a substrate. The structure is released from the substrate and includes a test layer mechanically coupled between the two rigid anchors. The test layer includes a first region having a first cross-sectional area and a constricted region having a second cross-sectional area smaller than the first cross-sectional area. The structure also includes a first tensile stressed layer disposed on a surface of the test layer adjacent the first region.

Abstract: A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a substance is provided on a selected portion of the wafer to selectively configure a circuit element within the at least one of the plurality of semiconductor device structures.

Abstract: A method of manufacturing a wafer. The method includes providing a wafer and testing the wafer. Based on a test result, a substance is selectively provided on the wafer to obtain an altered wafer that has at least one selected portion altered. The method includes forming a structural layer over the altered wafer.

Abstract: A wafer cutting apparatus comprises a wafer positioning device for holding a wafer that is substantially covered with an opaque material such as molding compound and that has an exposed peripheral area, and for displacing the wafer relative to a wafer inspection system comprising a camera having a field of view. To perform visual data acquisition of said dicing street portions, the wafer is displaced such that a centre of the camera's field of view follows a path along the exposed peripheral area of the wafer. A processing unit analyses the visual data acquired for detecting or calculating locations and directions of the dicing streets. A wafer cutting tool cuts the wafer along straight lines between the dicing street portions which have been detected or calculated by the processing unit.

Abstract: Disclosed is a display driving device including a bonding resistance measurement circuit. The display driving device may include: first and second pads bonded to a pad of a display panel through a wire and configured to provide bonding resistance; and a bonding resistance measurement circuit configured to measure the bonding resistance by comparing an input voltage applied to the bonding resistance through the first pad to one or more preset reference voltages.

Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.

Abstract: The present invention relates to a substrate for an integrated circuit package and, more specifically, to a substrate for an integrated circuit package, which reduces mismatch of coefficients of thermal expansion with a semiconductor chip, thereby preventing or minimizing warpage during a reflow process.

Abstract: A device package is provided. The device package includes a first die and a second die. A top surface of the first die is offset from a top surface of the second die in a direction that is parallel to a sidewall of the first die. A molding compound extends along sidewalls of the first die and the second die, where at least a portion of a top surface of the molding compound includes an inclined surface. A polymer layer contacts the top surface of the molding compound, the top surface of the first die, and the top surface of the second die. A top surface of the polymer layer is substantially level. A first conductive feature is in the polymer layer, where the first conductive feature is electrically connected to the first die.

Abstract: An electronic component mounting structure includes a terminal of an electronic component package and a chip heat radiating member. The terminal is soldered on a land of an electronic substrate and the chip heat radiating member is soldered on a back surface of the package. The chip heat radiating member is covered by a packaging resin. The metallic heat radiating pattern integrally includes a pattern extension part that is protruded from the package, such that at least a part of the metallic heat radiating pattern in formed to be larger than the package. The pattern extension part guides excessive solder to outside of the package.

Abstract: An electrical circuit device includes a circuit board including a cavity extending from a top surface of the circuit board to an embedded conductor, an integrated circuit chip in the cavity, an electrical connection between the integrated circuit chip and the embedded conductor, a thermal slug disposed over a top surface of the integrated circuit chip, and a heat sink mounted to an outer surface of the thermal slug for transferring a thermal energy away from the circuit board, the heat sink extending above a top surface of the circuit board.

Abstract: A thermally enhanced semiconductor assembly with three dimensional integration includes a semiconductor chip electrically coupled to a wiring board by bonding wires. A heat spreader that provides an enhanced thermal characteristic for the semiconductor chip is disposed in a through opening of a wiring structure. Another wiring structure disposed on the heat spreader not only provides mechanical support, but also allows heat spreading and electrical grounding for the heat spreader by metallized vias. The bonding wires provide electrical connections between the semiconductor chip and the wiring board for interconnecting the semiconductor chip to terminal pads provided in the wiring board.

Abstract: Provided herein is a resin structure having high heat dissipation, and desirable adhesion at the interface with a heat generating device. The resin structure is provided on a substrate to dissipates heat of the substrate to outside, and includes: a water-based coating material layer provided on the substrate and including a water-based coating material, and fillers having an average particle size of 30 ?m to 150 ?m; and a resin layer provided on the water-based coating material layer and containing a thermosetting resin. The fillers have a far-infrared emissivity of 0.8 or more, and an average aspect ratio of 1 to 12 as measured as a ratio of lengths along the long axis and the short axis through the center of gravity of the fillers. At least 80% of the total number of fillers has a length that is at least 1.