Abstract: Provided herein is an apparatus including a top continuous layer and a bottom continuous layer under the top continuous layer. The top continuous layer and the bottom continuous layer are antiferromagnetically coupled. A number of granular columns are under the bottom continuous layer. The number of granular columns include at least a first granular layer under the bottom continuous layer and a second granular layer also under the first granular layer. The first granular layer and the second granular layer are separated by a non-magnetic spacer. The first granular layer and the second granular layer are ferromagnetically coupled. The first granular layer is antiferromagnetically coupled to the bottom continuous layer.

Abstract: A sequential storage media system may include a head for reading or writing data to sequential storage media and a controller communicatively coupled to the head. The controller may be configured to control winding of a tape comprising sequential storage media and cleaning media between reels of a cartridge comprising the tape in order to clean a head of a sequential storage media system by passing the cleaning media over the head, after cleaning the head of the sequential storage media system, monitor a bit error rate of input/output communication between the head and the sequential storage media, and repeat the cleaning and the monitoring steps responsive to the bit error rate exceeding a threshold. A sequential storage media system may include a head for reading or writing data to sequential storage media and a controller communicatively coupled to the head.

Abstract: A thermally-assisted magnetic recording head includes a main pole and a plasmon generator. The plasmon generator includes a first material portion and a second material portion formed of different materials. The first material portion is located away from the medium facing surface. The second material portion includes a near-field light generating surface. The main pole has a front end face including a first end face portion and a second end face portion. The near-field light generating surface, the first end face portion and the second end face portion are arranged in this order along the direction of travel of a recording medium.

Abstract: A heat assisted magnetic recording (HAMR) writer is described. The HAMR writer is coupled with a laser that provides energy having a first polarization state. The HAMR writer has an air-bearing surface (ABS) configured to reside in proximity to a media during use, a plurality of waveguides, a main pole and at least one coil. The main pole writes to the media and is energized by the coil(s). The waveguides receive the energy from the laser and direct the energy toward the ABS. The waveguides include an input waveguide and an output waveguide. The input waveguide is configured to carry light having the first polarization state. The output waveguide is configured to carry light having a second polarization state different from the first polarization state. The waveguides are optically coupled and configured to transfer the energy from the first polarization state to the second polarization state.

Abstract: Systems and methods for determining a relationship between write fault threshold and temperature are described. The systems and methods include measuring an operating temperature of the storage device, determining a current operating temperature of the storage device, determining whether the current operating temperature of the storage device satisfies a temperature threshold, and upon determining the current operating temperature of the storage device satisfies the temperature threshold, modifying a write fault threshold associated with a data track of the storage device.

Abstract: A magnetic media disk is fabricated by depositing magnetic layers over the disk, then depositing protective later over the magnetic layer, and then performing ion implant process to implant ions into the protective coating. A system for performing the ion implant of the magnetic media disk includes two ion implant chambers. During operation one chamber performs ion implant and one chamber performs chamber cleaning by maintaining inside a plasma of cleaning gas without a disk present inside the chamber.

Abstract: Disclosed is a method for video editing. The method comprises selecting at least one video, using a user interface, displaying one of the selected at least one video, on a video preview area on the user interface, providing at least one effect button on the user interface, to be activated by applying a pointing device at the at least one effect button, wherein each of the at least one effect button is associated with one video editing effect, selecting a time point in a timeline of the displayed one video, activating an effect button selected from the at least one effect button provided, and applying a video editing effect corresponding to the activated effect button from the selected time point forward until detecting de-activation of the activated effect button.

Abstract: A playlist file for controlling playback of a VOB stream file is recorded in a recording medium. A CombiExt_for_Cell( ) and Combi( ) indicating combinations of elementary streams that each can be played at the same time in the same Cell are described in the playlist file. Elementary streams that can be played at the same time as SDR video are listed in the CombiExt_for_Cell( ), and elementary streams that can be played at the same time as HDR video are listed in Combi( ). The number of elementary streams of a predetermined type listed in CombiExt_for_Cell( ) and the number of elementary streams of the predetermined type listed in Combi( ) are each equal in the same Cell.

Abstract: An image processing apparatus includes a display and a CPU that is configured to: select, as a group, a plurality of moving images as a group of target moving images to be played back simultaneously or in sequence; specify a plurality of spatial or temporal playback relationships for playing back the group of target moving images simultaneously or in sequence; generate a plurality of groups of thumbnails representing the plurality of specified spatial or temporal playback relationships, such that each group of thumbnails includes one thumbnail corresponding to each of the target moving images to be played back, and such that each group of thumbnails visually represents a respective one of the specified the spatial or temporal playback relationships; and display the plurality of groups of thumbnails representing the plurality of specified spatial or temporal playback relationships.

Abstract: A computing device for processing a video file. The video file comprises an audio track and contains at least one event comprising a scene of interest. One or more audio criteria that characterize the event are used to detect events using the audio track and an offset timestamp is recorded for each detected event. A set of offset timestamps may be produced for a set of detected events of the video file. The set of offset timestamps for the set of detected events may be used to time align and time adjust a set of real timestamps for a set of established events for the same video file. A user interface (UI) is provided that allows quick and easy search and playback of events of interest across multiple video files.

Abstract: This disclosure relates to systems and methods to synchronize recordings between content recording devices. A method may include establishing a synchronized recording relationship with a second content recording device. The method may further include capturing a first recording and periodically inserting a first set of markers in the first recording at a first set of points of time. A second recording may be captured by the second content recording device and a second set of markers are inserted in the second recording at a second set of points of time. The first recording and the second recording may be temporally aligned based on a first marker of the first set of markers and a second marker of the second set of markers. The first marker and the second marker have a matching type and corresponding to a common point in time in the first recording and the second recording.

Abstract: A display control device includes an assigning unit and a display control unit. The assigning unit assigns, with respect to S number of units of display (where S is an integer equal to or greater than two) included in a display area in which units of display having the width equal to L number of pixels (where L is an integer equal to or greater than one) are placed in the width direction, M number of sets of data (where M is an integer greater than S) in a divided manner. The display control unit controls display of the units of display in different display formats according to the number of sets of data of a particular type included in the assigned data.

Abstract: A method of providing an image by an electronic device may include: acquiring first and second images and sound data; generating event information through analysis of at least one of the first and second images and the sound data; and generating a multitrack file including the first and second images, the sound data, and the event information.

Abstract: A method controls display of one or more visually perceptible tags in association with a video. The method receives a first signal from a user input control device while the video is being presented via a display device without any visually perceptible tags. The first signal is generated by the user input control device in response to activation of a control associated with a function of causing the display device to present the video with the at least one visually perceptible tag. In response to receiving the first signal, the method causes the display device to present the video with at least one visually perceptible tag. After causing the display device to present the video with the at least one visually perceptible tag, the method changes the function associated with the control to thereafter cause the display device to present the video without any visually perceptible tags.

Abstract: A system for dual mode operation having power saving and active modes in a stacked circuit topology having logic preservation is provided. The system includes a pre-charge circuit and a sleep mode control circuit for providing a signal to disable a plurality of circuit elements and switching a mode of the system, the sleep mode control circuit being coupled to the pre-charge circuit and further being coupled to a logic function circuit, wherein the plurality of circuit elements comprise logic gates and transistor devices. The system also includes a keeper circuit coupled to the global bitline, and the logic function circuit coupled to a solar bitline, wherein the logic function circuit preserves a state of the solar bitline, the state of the global bitline determines the state of the solar bitline. The system includes an effective pull-up transistor coupled to the sleep mode control circuit and the logic function circuit.

Abstract: A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

Abstract: Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.

Abstract: According to embodiments of the present invention, a flip-flop circuit is provided. The flip-flop circuit includes a first stage circuit and a second stage circuit, wherein each of the first stage circuit and the second stage circuit is operable in two modes of operation, and a driver arrangement, wherein the first stage circuit includes a first transistor and a first non-volatile memory cell connected to each other, wherein the second stage circuit includes a second transistor and a second non-volatile memory cell connected to each other, and wherein the driver arrangement is configured, at a clock level, to drive the first stage circuit in one of the two modes of operation to access the first non-volatile memory cell and, at the clock level, to drive the second stage circuit in the other of the two modes of operation to access the second non-volatile memory cell.

Abstract: A self-referenced MRAM cell including a reference layer having a fixed reference magnetization, a sense layer having a free sense magnetization, a tunnel barrier, a biasing layer having bias magnetization and a biasing antiferromagnetic layer pinning the bias magnetization in a bias direction when MRAM cell is at temperature equal or below a bias threshold temperature. The bias magnetization is arranged for inducing a bias field adapted for biasing the sense magnetization in a direction opposed to the bias direction, such that the biased sense magnetization varies linearly in the presence of the external magnetic field, when the external magnetic field is oriented in a direction substantially perpendicular to the one of the reference magnetization. The present disclosure further concerns a magnetic field sensor including a plurality of the self-referenced MRAM cell and a method for programming the magnetic field sensor.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.

Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

Abstract: A memory system includes a memory controller and a memory module, where the memory controller is arranged for generating at least a first clock signal and an inverted first clock signal, and the memory module is arranged to receive at least the first clock signal and the inverted first clock signal from the memory controller. In addition, the memory module includes a termination module, and the first clock signal is coupled to the inverted first clock signal through the termination module.

Abstract: A memory system includes a memory controller and a memory module. The memory controller is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module includes a first termination resistor, a second termination resistor and a switch module, where a first node of the first termination resistor is to receive the clock signal, a second termination resistor, wherein a first node of the second termination resistor is to receive the inverted clock signal, and the switch module is arranged for selectively connecting or disconnecting a second node of the second termination resistor to a second node of the first termination resistor.

Abstract: An electronic device includes a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a command/address output pad formed in the control device mounting area, a clock signal main wiring connected to the clock output pad, a command/address signal main wiring connected to the command/address output pad, a first clock signal branch wiring branched from the clock signal main wiring at a first branch point of the clock signal main wiring, and a second clock signal branch wiring branched from the clock signal main wiring at a second branch point of the clock signal main wiring, which is located at a downstream side of the clock signal main wiring than the first branch point of the clock signal main wiring.

Abstract: Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices.

Abstract: A refresh control device may include a plurality of latch circuits configured to receive an active signal, a refresh signal, an active control signal, and a refresh control signal, and output a word line enable signal for controlling a refresh operation to banks. The refresh control device may include a command decoder configured to decode a row address in correspondence to an external command signal and generate the active signal and the refresh signal. The refresh control device may include an address buffer configured to buffer an active address and generate the active control signal. The refresh control device may include an address control circuit configured to generate the refresh control signal in correspondence to a refresh command signal.

Abstract: A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is connected to a pre-charge circuit, and the pre-charge circuit is adapted for pre-charging the global bit-line with a programmable pre-charge voltage before reading data. The pre-charge circuit comprises a limiter circuit which comprises a pre-charge regulator circuit connected to the global bit-line to pre-charge the global bit-line with the programmable pre-charge voltage, and an evaluation and translation circuit connected to the pre-charge regulator circuit and the global bit-line to compensate leakage current of the global bit-line without changing its voltage level.

Abstract: A semiconductor memory device includes a plurality of static random access memory (SRAM) cells connected to a bit line pair comprising a first bit line and a second bit line. An equalizer circuit controls a connection between the first bit line and the second bit line. A timing control circuit controls the equalizer circuit such that the equalizer circuit disconnects the first bit line from the second bit line during a first mode and connects the first bit line to the second bit line during a second mode. The first mode permits data to be read from or written to the SRAM cells, and the second mode is a retention mode during which data is not read from or written to SRAM cells.

Abstract: A voltage supply circuit for a memory cell including a first circuit coupled between a first voltage supply and a first voltage supply terminal of the memory cell, and a second circuit coupled between the first voltage supply and a second voltage supply terminal of the memory cell. The first circuit is controlled by a first bit line of the memory cell, and the second circuit is controlled by a second bit line of the memory cell. The first and second circuits provide the first supply voltage to the first and second voltage supply terminals of the memory cell, respectively, during a pre-charge phase. During a write operation, only one of the first circuit and the second circuit provides the first supply voltage to the memory cell, and the other one of the first circuit and the second circuit provides an adjusted voltage (e.g., a collapsed voltage) to the memory cell.

Abstract: The present invention discloses a static RAM for defensive differential power consumption analysis, comprising a replica bit-line circuit, a decoder, an address latch circuit, a clock circuit, n-bit memory arrays, n-bit data selectors, n-bit input circuit and n-bit output circuits; the output circuits comprises a sensitivity amplifier and a data latch circuit; the 1st PMOS tube, the 2nd PMOS tube, the 3rd PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 1st NMOS tube, the 2nd NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube constitute the sensitivity amplifier; two NOR gates, the 8th PMOS tube, the 9th PMOS tube, the 10th PMOS tube, the 11th PMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube and the 10th NMOS tube constitute the data latch circuit; the present invention is characterized in that energy consumption in each working cycle is basically identical, which is provided with higher capability in defense of

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Abstract: A resistive memory device and a method may be provided. The resistive memory device may include a reset voltage-detecting circuit, a set voltage-detecting circuit, a control circuit and a read voltage-generating circuit. The reset voltage-detecting circuit may receive a variable preliminary reset current to detect reference reset voltage information. The set voltage-detecting circuit may receive a variable preliminary set current to detect reference set voltage information. The control circuit may receive the reference reset voltage information and the reference set voltage information to determine middle voltage information of the reference reset voltage information and the reference set voltage information. The read voltage-generating circuit may receive the middle voltage information to generate a read voltage.

Abstract: A nonvolatile memory device includes a nonvolatile memory cell and a variable resistive load portion. The variable resistive load portion is coupled between a bit line of the nonvolatile memory cell and a supply voltage line. The variable resistive load portion is suitable for changing a resistance value between the bit line and the supply voltage line according to a level of a supply voltage applied to the supply voltage line.

Abstract: A resistive memory apparatus may include a memory region including a plurality of resistive memory cells arranged in a plurality of memory cell pairs. The resistive memory apparatus may include a voltage generating circuit configured to generate a read voltage code based on a switching state of at least one memory cell pair. The resistive memory apparatus may include a voltage providing unit configured to generate a read voltage corresponding to the read voltage code.

Abstract: A method to access two memory cells include determining a first cell current flowing through a first memory cell by subtracting a sneak current associated with the first memory cell from a first access current of the first bitline and determining a second cell current flowing through a second memory cell in the first bitline or a second bitline by subtracting the sneak current associated with the first memory cell from a second access current of the first bitline or the second bitline.

Abstract: Phase change memory devices, systems, and associated methods are provided and described. Such devices, systems, and methods manage and reduce voltage threshold drift to increase read accuracy of phase change memory.

Abstract: Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.

Abstract: A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of the first transistor is connected to a line to instruct setting of the bi-polar memristor, and the second switch is a second transistor and a gate of the second transistor is connected to a line to instruct re-setting of the bi-polar memristor.

Abstract: According to an embodiment of the present disclosure, a device and a method are provided. The device includes one or more resistive random access memory (ReRAM) elements. The device further includes a random number generator configured to generate a random number in dependence on impedance values of the one or more ReRAM elements.

Abstract: A state-changeable device includes a first and a second particle arranged in proximity to each other; and a coupling material between the first and the second particle; wherein the first and the second particle are adapted to provide a charge carrier distribution such that surface plasmon polaritons (SPP) occur; and the coupling material is adapted to exhibit a variable conductivity in response to a trigger signal thereby changing an electro-optical coupling between the first and the second particle.

Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

Abstract: A nonvolatile memory cell includes a first-conductivity-type silicon substrate, a metal layer formed in a surface of the first-conductivity-type silicon substrate, a second-conductivity-type diffusion layer formed in the surface of the first-conductivity-type silicon substrate and spaced apart from the metal layer, an insulating film disposed on the surface of the first-conductivity-type silicon substrate between the metal layer and the second-conductivity-type diffusion layer, a gate electrode disposed on the insulating film between the metal layer and the second-conductivity-type diffusion layer, and a sidewall disposed at a same side of the gate electrode as the metal layer and situated between the gate electrode and the metal layer, the sidewall being made of insulating material.

Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

Abstract: A semiconductor device includes sub-block stack structures respectively including source layers, where the sub-block stack structures are disposed to be spaced apart from each other along a first direction, a memory block stack structure including word lines stacked over the sub-block stack structures, the word lines being coupled to memory cells, the memory block stack structure extending along the first direction to overlap the sub-block stack structures, and channel layers respectively coupled to the source layers by penetrating the memory block stack structure.

Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.

Abstract: Disclosed herein is a NAND flash memory comprising a bit-line and a page buffer, the page buffer comprising: a first switching circuit arranged between a first node and the bit-line; a third switching circuit arranged between the first node and a sensing node and configured to discharge the sensing node during an evaluation period, a pre-charging period preceding the evaluation period; and a fourth switching circuit configured to provide a first pre-charging path to the bit-line through the first node and the first switching circuit from a first voltage source during the pre-charging period, wherein the sensing node is configured to be charged through a second pre-charging path during the pre-charging period, and the second pre-charging path is separated from the first pre-charging path by the third switching circuit during the pre-charging period.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, and first and second bit lines. The first and second bit lines are electrically connected to one ends of the first and second memory cells, respectively.