Abstract: Provided is a stable manufacturing method for a semiconductor device. In the manufacturing method for a semiconductor device, first, fins with an equal width are formed in each of a memory cell portion and a logic portion of a semiconductor substrate. Then, the fins in the logic portion are etched with the fins in the memory cell covered with a mask film, thereby fabricating fins in the logic portion, each of which is narrower than the fin formed in the memory cell portion.

Abstract: A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etch to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first and second fin end and the second cut fin having a first and second fin ends; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etch to remove a portion of the second cut fin.

Abstract: A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate structure, multiple fins having a germanium layer, a dummy gate structure including sequentially a hardmask, a dummy gate, a dummy gate insulating material on the germanium layer, and spacers on opposite sides of the dummy gate structure and on a portion of the germanium layer. The method also includes forming an interlayer dielectric layer on the substrate structure covering the dummy gate structure, planarizing the interlayer dielectric layer to expose a surface of the dummy gate, removing the dummy gate and the dummy gate insulating material to expose a surface of the germanium layer, performing a silane impregnation process on the exposed surface of the germanium layer to introduce silicon to the germanium layer, and performing an oxidation process on the germanium layer to form an oxide layer comprising silicon and germanium.

Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

Abstract: A complementary tunneling field effect transistor and a manufacturing method are disclosed, which includes: a first drain region and a first source region that are disposed on a substrate, where they include a first dopant; a first channel that is disposed on the first drain region and a second channel that is disposed on the first source region; a second source region that is disposed on the first channel and a second drain region that is disposed on the second channel, where they include a second dopant; a first epitaxial layer that is disposed on the first drain region and the second source region, and a second epitaxial layer that is disposed on the second drain region and the first source region; and a first gate stack layer that is disposed on the first epitaxial layer, and a second gate stack layer that is disposed on the second epitaxial layer.

Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.

Abstract: An RB-IGBT is provided that has a new emitter trench structure with improved breakdown voltage achieved by improving the electrical field distribution of the drift region. The RB-IGBT includes an isolation region having a first conductivity type on a side surface of a semiconductor substrate. The semiconductor substrate includes a drift region having a second conductivity type; a collector region having the first conductivity type and provided farther downward than the drift region; and an emitter trench portion provided extending to the drift region in a thickness direction from a front surface to a back surface of the semiconductor substrate. The emitter trench portion includes a trench electrode electrically connected to an emitter electrode provided above the semiconductor substrate; an upper trench insulating film directly contacting a bottom portion and side portions of the trench electrode; and a lower trench insulating film provided below the upper trench insulating film.

Abstract: A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn).

Abstract: A semiconductor device includes: a semiconductor substrate; a main electrode; a peripheral electrode; an insulating protective film; a surface metallic layer; and a solder layer, wherein the semiconductor substrate includes: a first region of a first conductive-type in contact with the main electrode on a main contact surface; a second region of a first conductive-type in contact with the peripheral electrode on a peripheral contact surface; and a third region of a second conductive-type provided under the first region, under the second region, and circumferentially outward of the second region, and a circumferentially-outward end of the metallic layer and a circumferentially-outward end of the solder layer are located more circumferentially inward than the circumferentially-outward end of the peripheral electrode.

Abstract: In one embodiment, a bi-directional punch-through semiconductor device can include: a first transistor in a first region of a semiconductor substrate of a first conductivity type, where the first transistor includes a semiconductor buried layer of a second conductivity type in the semiconductor substrate, and a first epitaxy region of an epitaxy semiconductor layer above the semiconductor buried layer, the semiconductor buried layer being configured as a base of the first transistor; and a second transistor coupled in parallel with the first transistor, where the second transistor is in a second region of the semiconductor substrate of the first conductivity type, where the second transistor comprises a second epitaxy region of the epitaxy semiconductor layer above the semiconductor substrate, and a first doped region of the second conductivity type in the second epitaxy region, the first doped region being configured as a base of the second transistor.

Abstract: A thyristor, in particular a phase control thyristor, is disclosed with comprises: a) a semiconductor slab, in particular a semiconductor wave or die, in which a thyristor structure is formed, b) a cathode metallization formed on a cathode region on a cathode side surface of the semiconductor slab, c) a gate metallization formed on a gate region on the cathode side surface of the semiconductor slab, d) a plurality of N discrete emitter shorts, arranged at points Pi in the cathode region, said points having point locations xi, with i?{1; . . . ; N}, e) the points Pl defining a Delaunay triangulation comprising a plurality of triangles Tj with j?{1; . . . ; M), wherein f) for a first subset of triangles Tl with l?S1?{1; . . . ; M), g) with each triangle Tl being characterized by a geometric quantity having values qT,l with l?S1?{1; . . . ; M), said geometric quantity having a mean value ?, and i) a coefficient of variation of the values qT,l with l?S1 is smaller than 0.1, preferably smaller than 0.

Abstract: An electronic device including a two-dimensional electron gas is provided. The electronic device includes a substrate, a first material layer disposed on the substrate and formed of a binary oxide, a second material layer disposed on the first material layer and formed of a binary oxide, and a two-dimensional electron gas generated between the first material layer and the second material layer.

Abstract: Semiconductor devices with airgap spacers and methods of forming the same include forming a lower spacer that defines a gate region. A sacrificial upper spacer is formed directly above the lower spacer. A gate stack is formed in the gate region. The sacrificial upper spacer is etched away to form an upper spacer opening. An airgap spacer is formed in the upper spacer opening. The airgap spacer includes a dielectric material that encapsulates an internal void.

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Abstract: Embodiments of a silicon carbide (SiC) device are provided herein. In some embodiments, a silicon carbide (SiC) device may include a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises: a drift region having a first conductivity type; a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×1014 cm?2, and wherein the pinch region is configured to deplete at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region.

Abstract: According to one embodiment, the gate insulating film is provided on a semiconductor region including the body region and the drift region between the source region and the drain region. The gate insulating film includes a first part and a second part. The first part is provided on the source region side. The second part is provided on the drain region side and thicker than the first part. The insulating portion is provided in the semiconductor region under a boundary between the first part and the second part of the gate insulating film.

Abstract: Disclosed is a semiconductor device, including: a first pipe gate; a second pipe gate on the first pipe gate; a stacked structure on the second pipe gate; a first channel layer including a first pipe channel layer positioned within the first pipe gate and first cell channel layers connected to the first pipe channel layer; a second channel layer including a second pipe channel layer positioned within the second pipe gate, and second cell channel layers connected to the second pipe channel layer; and a slit insulating layer passing through the stacked structure and positioned between the adjacent second cell channel layers, wherein the second pipe channel layer has a body portion and a protrusion portion extending below the body portion at a position below the slit insulating layer.

Abstract: A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.

Abstract: A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.

Abstract: The present disclosure relates to a transistor device having a strained source/drain region. In some embodiments, the transistor device has a gate structure arranged over a semiconductor substrate. The transistor device also has a strained source/drain region arranged within the semiconductor substrate along a side of the gate structure. The strained source/drain region includes a first layer and a second layer over the first layer. The first layer has a strain inducing component with a first concentration profile that decreases as a distance from the second layer decreases, and the second layer has the strain inducing component with a second non-zero concentration profile that is discontinuous with the first concentration profile.

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. A topmost location of the epitaxy structure has an n-type impurity concentration lower than an n-type impurity concentration of a location of the epitaxy structure below the topmost location.

Abstract: The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.

Abstract: An oxide semiconductor transistor according to an exemplary embodiment of the present invention includes: a substrate; a first gate electrode disposed on the substrate; a gate insulating layer disposed on the substrate and the first gate electrode; an oxide semiconductor layer disposed on the gate insulating layer; an etch stopper layer disposed on the oxide semiconductor layer; and a source electrode and a drain electrode disposed on the oxide semiconductor layer and the etch stopper layer and spaced apart from each other.

Abstract: An array substrate and a display device are provided. A gate insulating layer and a gate electrode are formed on a semiconductor layer in sequence, the gate insulating layer and the gate electrode are located in a middle position of the semiconductor layer and have a uniform shape and size. In a region on the semiconductor layer that is not covered by the gate insulating layer, there is further provided a metal diffusion layer. A barrier layer includes a portion covering the gate insulating layer and the gate electrode and a portion located around the semiconductor layer. A passivation layer covers the semiconductor layer, the gate insulating layer, the gate electrode and the barrier layer. Source and drain electrodes are connected to the metal diffusion layer respectively, and a pixel electrode contacts with the drain electrode.

Abstract: The thin film transistor includes a first insulating layer provided on a substrate; a source electrode and a drain electrode that are provided on the first insulating layer; a semiconductor layer provided so as to cover the first insulating layer, the source electrode, and the drain electrode; a second insulating layer provided on the semiconductor layer; and a gate electrode provided on the second insulating layer, in which the first insulating layer is formed of a hydrophilic/hydrophobic material and has a recess portion, and the source electrode and the drain electrode are provided so as to fill the recess portion of the first insulating layer.

Abstract: Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films. In addition, the first and second gate electrodes surround the oxide semiconductor film in a cross-section in the channel width direction, with the first gate insulating film provided between the first gate electrode and the oxide semiconductor film and the second gate insulating film provided between the second gate electrode and the oxide semiconductor film. Furthermore, the channel length of the transistor is 0.5 ?m or longer and 6.5 ?m or shorter.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface, an element separation film formed over the main surface, and a fin protruding from the element separation film and extending in the first direction in plan view. The semiconductor device further includes a control gate electrode extending in the second direction that is orthogonal to the first direction along the surface of the fin through a gate insulating film and overlaps with a first main surface of the element separation film, and a memory gate electrode extending in the second direction along the surface of the fin through an insulating film and overlaps with a second main surface of the element separation film, in which the second main surface is lower than the first main surface relative to the main surface.

Abstract: A transistor (100), including a planar semiconducting substrate (36), a source (42) formed on the substrate, a first drain (102) formed on the substrate, and a second drain (104) formed on the substrate in a location physically separated from the first drain. At least one gate (38, 40) is formed on the substrate and is configured to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path (62) to be established within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established within the substrate from the source to the second drain.

Abstract: A semiconductor device comprising at least two holes (18, 20) realised in a substrate (6), having each a width and a depth, and forming a diode (4), wherein the substrate (6) has a determined type of doping, wherein the inner wall of each hole (18, 20) is doped so that its doping is of the other type than the doping of the substrate (6), and wherein the width and/or the depth of a hole (18, 20) is different from the width and/or the depth of a neighboring hole.

Abstract: A vertical positive-intrinsic-negative (pin) diode includes a semiconductor substrate in which a P-type region, an intrinsic region, and an N-type region are sequentially disposed in a vertical direction to be formed therein, a first electrode formed on one surface of the semiconductor substrate to be in electrical contact with the P-type region, and a second electrode formed on the other surface of the semiconductor substrate to be in electrical contact with the N-type region, wherein the P-type region and the N-type region are respectively disposed in an upper portion and a lower portion of the semiconductor substrate to be opposite to each other.

Abstract: A high efficiency configuration for a solar cell module comprises solar cells arranged in an overlapping shingled manner and conductively bonded to each other in their overlapping regions to form super cells, which may be arranged to efficiently use the area of the solar module.

Abstract: A method for use in forming a photovoltaic device includes forming a doped semiconductor layer on a surface of a semiconductor substrate and forming a metal film on the doped semiconductor layer. A patterned etched resist is formed on the metal film and a dielectric layer is formed on the doped semiconductor layer and the etched resist. A laser having a wavelength absorbable by the patterned etch resist is applied through the dielectric layer to the patterned etch resist to remove the patterned etch resist.

Abstract: Embodiments of the present invention provide a compound optical filter device comprising a semiconductor substrate having an optical transducer formed on the semiconductor substrate, the optical transducer responsive to light to produce a signal or responsive to a signal to emit light. An optical filter comprises a filter substrate separate and independent from the semiconductor substrate and one or more optical filter layers disposed on the filter substrate. The filter substrate is micro-transfer printed on or over the semiconductor substrate or on layers formed over the semiconductor substrate and over the optical transducer to optically filter the light to which the optical transducer is responsive or to optically filter the light emitted by the optical transducer. In further embodiments, the optical filter is an interference filter and the semiconductor substrate includes active components that can control or operate the optical transducer.

Abstract: The low-reflection coating of the present invention is adapted to be provided on at least one principal surface of a substrate. The low-reflection coating is a porous film having a thickness of 80 to 800 nm, the porous film including: fine silica particles being solid and spherical and having an average particle diameter of 80 to 600 nm; and a binder containing silica as a main component and containing a hydrophobic group, the fine silica particles being bound by the binder. The low-reflection coating contains 35 to 70 mass % of the fine silica particles, 25 to 64 mass % of the silica of the binder, and 0.2 to 10 mass % of the hydrophobic group of the binder. The low-reflection coating produces a transmittance gain of 1.5% or more when provided on the substrate.

Abstract: A solar panel using a light guiding component for receiving external light includes at least one solar cell, a transparent back plate, a transparent cover plate, a light guiding component and a packaging material. The transparent back plate is located on a first side of the solar cell. The transparent cover plate is located on a second side of the solar cell for passing and projecting the light to the solar cell and the transparent back plate. The light guiding component is located on the first side of the solar cell. The packaging material is disposed between the transparent cover plate and the transparent back plate for packaging the solar cell. The solar cell is packaged between the transparent back plate and the transparent cover plate, such that after the light projects to the light guiding component, the light guiding component scatters the light.

Abstract: The present disclosure provides a method of patterning a polymeric layer based on the chemical reaction of two chemical compounds. One chemical compound is provided in the polymeric layer and another chemical compound is deposited on the polymeric layer by, for example, ink-jet printing. The method allows for fabrication of, for example, metallisation patterns for solar cells electronic components, integrated devices and formation of selective doped areas in solar cells amongst others.

Abstract: A solar cell (104) is disclosed. The solar cell includes a substrate (151) including a front surface (156) and front surface electrodes (153) extending along the front surface (156). Therein, the front surface electrodes comprise a plurality of bus bar electrodes (152) coupled to a plurality of first finger electrodes (1531) arranged in a parallel finger region (105) and second finger electrodes (1532) arranged in a palm finger region (106).The first finger electrodes (1531) are substantially parallel to each other and perpendicular to the bus bar electrodes (152). The second finger electrodes (1532) originate from end regions of the bus bar electrodes (152) and radially extend at least in portions thereof in directions non-perpendicular to the bus bar electrodes (152).

Abstract: A method (200) for fabricating patterns on the surface of a layer of a device (100), the method comprising: providing at least one layer (130, 230); adding at least one alkali metal (235); controlling the temperature (2300) of the at least one layer, thereby forming a plurality of self-assembled, regularly spaced, parallel lines of alkali compound embossings (1300, 1305) at the surface of the layer. The method further comprises forming cavities (236, 1300) by dissolving the alkali compound embossings. The method (200) is advantageous for nanopatterning of devices (100) without using templates and for the production of high efficiency optoelectronic thin-film devices (100).

Abstract: A quantum cascade detector includes a semiconductor substrate; an active layer having a cascade structure; a lower cladding layer provided between the active layer and the substrate and having a lower refractive index than the active layer; a lower metal layer provided between the lower cladding layer and the substrate; an upper cladding layer provided on an opposite side to the substrate with respect to the active layer and having a lower refractive index than the active layer; and an upper metal layer provided on an opposite side to the active layer with respect to the upper cladding layer. A first end face being in a waveguide direction in a waveguide structure with the active layer, lower cladding layer, and upper cladding layer is an entrance surface for light to be detected.

Abstract: The present invention relates to a glass, in particular a glass for the joining of glass panes for the production of vacuum insulating glasses at processing temperatures ?420° C., to the corresponding composite glass, and to the corresponding glass paste. Moreover, the present invention relates to a vacuum insulating glass produced using the glass paste according to the invention, to the production process thereof, and to the use of the inventive glass and/or composite glass, and glass paste. The glass according to the invention is characterized in that it comprises the following components, in units of mol-%: V2O5 5-58 mol-%,Te02 40-90 mol-%, and at least one oxide selected from ZnO 38-52 mol-%, or Al2O3 1-25 mol %, or MoO3 1-10 mol-%, or WO3 1-10 mol-%, or a combination thereof.

Abstract: The present invention relates to a polymer composition, to a layer element, preferably to at least one layer element of a photovoltaic module, comprising the polymer composition and to an article which is preferably said at least one layer of a layer element, preferably of a layer element of a photovoltaic module.

Abstract: A multijunction solar cell including an upper first solar subcell having a first band gap; a second solar subcell adjacent to the first solar subcell and having a second band gap smaller than the first band gap; a first graded interlayer adjacent to the second solar subcell; the first graded interlayer having a third band gap greater than the second band gap; and a third solar subcell adjacent to the first graded interlayer, the third subcell having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell. A second graded interlayer is provided adjacent to the third solar subcell; the second graded interlayer having a fifth band gap greater than the fourth band gap; and a lower fourth solar subcell is provided adjacent to the second graded interlayer, the lower fourth subcell having a sixth band gap smaller than the fourth band gap such that the fourth subcell is lattice mismatched with respect to the third subcell.

Abstract: In case of forming electrodes for electronic device using a two-dimensional semiconductor, a two-dimensional semiconductor layer doped into n-type or p-type is formed on a substrate, a first area and a second area of the doped two-dimensional semiconductor layer is patterned into a predetermined pattern shape, and a first electrode and a second electrode are formed on the patterned first and second areas, respectively.

Abstract: A solar cell according to embodiments of the inventive concept includes a back electrode on a substrate, a first light absorbing layer including gallium (Ga) and indium (In) on the back electrode, a first buffer layer on the first light absorbing layer, a first window layer on the first buffer layer, a second light absorbing layer including Ga on the first window layer, a second buffer layer on the second light absorbing layer, and a second window layer on the second buffer layer, wherein a composition ratio of (Ga)/(Ga+In) of the first light absorbing layer is lower than that of the second light absorbing layer.

Abstract: A light detection device includes a substrate, a buffer layer disposed on the substrate, a first band gap change layer disposed on a portion of the buffer layer, a light absorption layer disposed on the first band gap change layer, a Schottky layer disposed on a portion of the light absorption layer, and a first electrode layer disposed on a portion of the Schottky layer.

Abstract: The invention relates to a photo bode type structure (comprising: a support (100) including at least one semiconductor layer, the semiconductor layer (120) including of a first semiconductor zone (10) of a first type of conductivity and a mesa (130) in contact with the semiconductor layer (120). The mesa (130) includes of a second semiconductor zone (20), known as absorption zone, said second semiconductor zone (20) being of a second type of conductivity. The second semiconductor zone has a concentration of majority carriers such that the second semiconductor zone (30) is depleted in the absence of polarization of the structure (1). The structure (1) further comprises a third semiconductor zone (30) of the second type of conductivity made of a third material transparent in the absorbed wavelength range. The third semiconductor zone (30) is interposed between the first and the second semiconductor zones (10, 20) while being at least partially arranged in the semiconductor layer (120).

Abstract: An avalanche photodiode, and related method of manufacture and method of use thereof, that includes a first contact layer; a multiplication layer, wherein the multiplication layer includes AlInAsSb; a charge, wherein the charge layer includes AlInAsSb; an absorption, wherein the absorption layer includes AlInAsSb; a blocking layer; and a second contact layer.

Abstract: A semiconductor module includes a light emitting element, a semiconductor element including a light receptor circuit disposed to receive light from the light emitting element, a light-transmissive insulating body disposed between the light emitting element and the semiconductor element, at least one of a first surface thereof facing the semiconductor element and a second surface thereof facing the light emitting element including a ragged region, a first light-transmissive bonding resin formed between the light emitting element and the light-transmissive insulating body, and a second light-transmissive bonding resin formed between the semiconductor element and the light-transmissive insulating body.

Abstract: A light receiving and emitting element module includes a substrate; a light emitting element and a light receiving element on an upper surface of the substrate; a frame-shaped outer wall that on the upper surface of the substrate; and a light shielding wall that is positioned inside the outer wall and partitions an internal space of the outer wall into spaces respectively corresponding to the light emitting element and the light receiving element. The light shielding wall includes a light emitting element-side shading surface on the light emitting element side, a light receiving element-side shading surface on the light receiving element side, and a lower surface that is connected to each of the light emitting element-side shading surface and the light receiving element-side shading surface, and that faces the substrate. The lower surface has an inclined surface inclined with respect to the upper surface of the substrate.