Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for associating one or more of a plurality of metadata collections with one or more respective identifiers, wherein each metadata collection includes one or more pairings of metadata attributes with metadata values, and wherein each identifier is one of a project identifier, a tag identifier or an instance identifier; identifying, based on identifier information associated with a virtual machine instance, one or more metadata values to be provided to the virtual machine instance, wherein the identifier information specifies one or more of a project identifier, a tag identifier and an instance identifier, and wherein each identified metadata value belongs to a metadata collection associated with an identifier that is specified in the identifier information; and providing, to the virtual machine instance, the identified one or more metadata values.

Abstract: Standard nested virtualization allows a hypervisor to run other hypervisors as guests, i.e. a level-0 (L0) hypervisor can run multiple level-1 (L1) hypervisors, each of which can run multiple level-2 (L2) virtual machines (VMs), with each L2 VM is restricted to run on only one L1 hypervisor. Span provides a Multi-hypervisor VM in which a single VM can simultaneously run on multiple hypervisors, which permits a VM to benefit from different services provided by multiple hypervisors that co-exist on a single physical machine. Span allows (a) the memory footprint of the VM to be shared across two hypervisors, and (b) the responsibility for CPU and I/O scheduling to be distributed among the two hypervisors. Span VMs can achieve performance comparable to traditional (single-hypervisor) nested VMs for common benchmarks.

Abstract: A method of sharing a resource using a virtual device driver and an electronic device thereof are provided. The method includes generating a virtual device driver, which corresponds to a real device driver of a host electronic device, in the client electronic device, receiving a resource from the host electronic device by using the virtual device driver through a first communication mechanism designated in the host electronic device, and after the first communication mechanism is changed to a second communication mechanism designated in the host electronic device, receiving the resource from the host electronic device by using the virtual device driver.

Abstract: A system for and method of retrieving values of captured local variables for a lambda function in Java. In one embodiment, the system includes: (1) a Java virtual machine and (2) a captured variable retriever that interacts with the Java virtual machine and configured to retrieve a signature of the lambda function from a classfile of a Java class containing the lambda function, compare the signature with a declaration of the lambda function to identify arguments corresponding to the captured local variables, modify the lambda function and cause the Java virtual machine to execute the modified lambda function.

Abstract: Provided is a system and method for a multi-tenant datacenter with nested hypervisors. This is provided by at least two physical computing systems each having at least one processor and memory store adapted to provide a first level Hypervisors, each providing a First Virtual Computing Environment with a plurality of inactive Virtual Hypervisors nested therein. The multi tenant data center is structured and arranged to activate a Virtual Hypervisor on one of the at least two Hypervisors and automatically migrate the at least one Customer VM from a Customer Hypervisor to the Active Virtual Hypervisor; and evacuate the remaining inactive Virtual Hypervisors from the Hypervisor supporting the Active Hypervisor to another of the at least two Hypervisors supporting inactive Virtual Hypervisors.

Abstract: Technology for generating, building, maintaining and sharing a pool of virtual environments. The virtual environments (for example, virtual machines) are instantiated and active prior to a request from a user to use a virtual environments. Delta maps are used to help match the request to the best-suited active virtual environment. The delta map is a data set that indicates differences between specification values of a given active virtual environment and specification values needed to reliably fulfill the user's request.

Abstract: The present invention provides a virtual machine migration method, a switch, a virtual machine system. A switch receives a message sent by a server, where the message is used to enable the switch to discover a connected virtual machine interface; obtains, from the message, an identifier for indicating whether a virtual machine is migrating; and determines whether the virtual machine is a virtual machine migrated to the server according to the identifier indicating whether the virtual machine is migrated. According to the embodiments of the present invention, it may be determined whether an added virtual machine on a server is a newly created one or a migrated one.

Abstract: Large-scale data migration processes are managed using a schedule optimizer implemented in software. The schedule optimizer assigns an available data migration window to each server in an inventory of servers based on a scheduling priority determined for that server. For example, servers that have manually scheduled conversion dates are assigned the highest scheduling priority, and servers that have a migration deadline are assigned the next highest scheduling priority. In addition, servers may grouped and data migration may be scheduled for server groups instead of individual servers.

Abstract: Examples are disclosed for composing memory resources across devices. In some examples, memory resources associated with executing one or more applications by circuitry at two separate devices may be composed across the two devices. The circuitry may be capable of executing the one or more applications using a two-level memory (2LM) architecture including a near memory and a far memory. In some examples, the near memory may include near memories separately located at the two devices and a far memory located at one of the two devices. The far memory may be used to migrate one or more copies of memory content between the separately located near memories in a manner transparent to an operating system for the first device or the second device. Other examples are described and claimed.

Abstract: Techniques to manage virtual classes for statistical tests are described. An apparatus may comprise a simulated data component to generate simulated data for a statistical test, statistics of the statistical test based on parameter vectors to follow a probability distribution, a statistic simulator component to simulate statistics for the parameter vectors from the simulated data with a distributed computing system comprising multiple nodes each having one or more processors capable of executing multiple threads, the simulation to occur by distribution of portions of the simulated data across the multiple nodes of the distributed computing system, and a distributed control engine to control task execution on the distributed portions of the simulated data on each node of the distributed computing system with a virtual software class arranged to coordinate task and sub-task operations across the nodes of the distributed computing system. Other embodiments are described and claimed.

Abstract: A centralized controller may include at least one processor, a memory and a communication interface. The centralized controller may configure a computing system in a single deployment of an executable process. The executable process may include multiple executable instances associated with one of multiple different templates for the executable process. Each template may include multiple user-configurable parameters. A user may request a template associated with a first executable instance and update the template using the user-configurable parameters. The centralized controller may generate a second executable instance of the executable process and a second template associated with the second executable instance based on the updated template. The centralized controller may reconfigure the computing system based on the second executable instance of the executable process while maintaining the configuration of the computing system based on the first executable instance.

Abstract: In at least some embodiments, a cache memory of a data processing system receives a transactional memory access request including a target address and a priority of the requesting memory transaction. In response, transactional memory logic detects a conflict for the target address with a transaction footprint of an existing memory transaction and accesses a priority of the existing memory transaction. In response to detecting the conflict, the transactional memory logic resolves the conflict by causing the cache memory to fail the requesting or existing memory transaction based at least in part on their relative priorities. Resolving the conflict includes at least causing the cache memory to fail the existing memory transaction when the requesting memory transaction has a higher priority than the existing memory transaction, the transactional memory access request is a transactional load request, and the target address is within a store footprint of the existing memory transaction.

Abstract: Example implementations relate to enabling native application capabilities. Some implementations may determine a set of object capabilities related to a source object stored in a remote third party repository. In some examples, the set of object capabilities represent at least one capability associated with the source object available to a third party application handling the source object. Some implementations may also determine a native application capability associated with the source object based on the determined set of object capabilities. Some implementations may also enable, in a native application, the native application capability for the source object.

Abstract: A multitasking method and apparatus of a user device are provided in which an interaction requesting task-switching is received in a state where an execution screen of a certain application is displayed. A stack of tasks that are currently running are displayed. A task selected from the stack is switched to a foreground task. An execution window of the foreground task is presented.

Abstract: A method for managing a background application is provided. The method includes determining whether an operating feature of the background application satisfies a preset condition, and when it is determined that the operating feature of the background application satisfies the preset condition, displaying an operating interface in a foreground interface of a mobile device for a user to close the background application.

Abstract: A method performed at an electronic device with a display includes: processing tasks in an application program; at least partially processing a plurality of layout objects in the application program; in accordance with a determination that one or more predefined control criteria are satisfied, pausing the processing of the plurality of layout objects in the application program; while the processing of the plurality of layout objects in the application program is paused, processing system tasks; and, after processing the system tasks while the processing of the plurality of layout objects in the application program is paused, resuming the processing of the plurality of layout objects.

Abstract: A computer program product is provided for prioritized hardware thread scheduling. The computer program product includes a non-transitory computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a computer to cause the computer to perform a method. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.

Abstract: Described herein are techniques and systems for onboarding a service from client-managed computing infrastructure to network computing infrastructure. As part of the onboarding, a database that stores onboarding information is accessed and a set of tasks is identified. A state diagram is generated based on the onboarding information. The techniques and systems are configured to calculate, within the state diagram, a task execution path that is associated with a highest probability of success for moving the client organization from a current environment associated with the client-managed computing infrastructure to a target environment associated with the network computing infrastructure. The task execution path can be used to identify and provide subsets of tasks as part of an autonomously guided onboarding process. The task execution path can be re-calculated based on a determination that an individual task has not been completed within an expected amount of time to complete the individual task.

Abstract: Methods and apparatuses select service tasks according to allocations of an available usage rate of a common processing resource are described. An ordering relationship is updated among the service tasks. E service task can have a rate of usage of the common processing resource. Each service may be associated with one of multiple task types. An allocation of the available rate of usage may be determined among the task types. The allocation can indicate a portion of the available rate of usage for each task type. The service tasks may be selected according to the allocation and the ordering relationship. At least one of the selected service tasks is associated with each task type associated with the service tasks.

Abstract: A method for scheduling threads for a software application. The method may include obtaining a thread from a thread queue. The thread may be a program segment of a software process. The method may include determining that the thread is for reading data from a program resource. The method may include, in response to determining that the thread is for reading the program resource, designating an exclusion lock on the program resource to various reader threads. The reader threads may include the thread from the thread queue. The method may include retrieving, by the reader threads, data from the program resource.

Abstract: An approach for providing mashup service of component services is described. A mashup service platform determines one or more component services available to at least one device. The mashup service platform also determines at least one mashup service based, at least in part, on a combination of the one or more component services. The mashup service platform further cause, at least in part, a generation of at least one mashup agent for interfacing with the at least one mashup service, the one or more component services, or a combination thereof.

Abstract: An embodiment of the invention includes applying a first partition to a plurality of LPs, wherein a particular LP is assigned to a first set of LPs. A second partition is applied to the LPs, wherein the particular LP is assigned to an LP set different from the first set. For both the first and second partitions, lookahead values and transit times are determined for each of the LPs and related links. For the first partition, a first system progression rate is computed using a specified function with the lookahead values and transit times determined for the first partition. For the second partition, a second system progression rate is computed using the specified function with the lookahead values and transit times determined for the second partition. The first and second system progression rates are compared to determine which is the lowest.

Abstract: For balancing load, a forwarder can selectively direct data from the forwarder to a processor according to a loading parameter. The selective direction includes forwarding the data to the processor for processing, transforming and/or forwarding the data to another node, and dropping the data. The forwarder can also adjust the loading parameter based on, at least in part, feedback received from the processor. One or more processing elements can store values associated with one or more flows into a structure without locking the structure. The stored values can be used to determine how to direct the flows, e.g., whether to process a flow or to drop it. The structure can be used within an information channel providing feedback to a processor.

Abstract: A system, and computer program product for large-scale data transformations. Embodiments include a smoothing engine within an R environment to configure at least one master task and at least two worker tasks. A chunk calculator receives a series of data values and divides the series of data values into portions of data values which are in turn assigned as workloads to at least two worker tasks. The worker tasks serve to calculate a first state value of a first one of the portions of data values, and calculate a second state value of a second one of the portions of data values. The workloads are selected such that calculating a second state value does not depend on the first state value. The results of the workload calculations are used to calculate a smoothing factor used to predict a trend.

Abstract: A method and apparatus for post-retire transaction access tracking is herein described. Load and store buffers are capable of storing senior entries. In the load buffer a first access is scheduled based on a load buffer entry. Tracking information associated with the load is stored in a filter field in the load buffer entry. Upon retirement, the load buffer entry is marked as a senior load entry. A scheduler schedules a post-retire access to update transaction tracking information, if the filter field does not represent that the tracking information has already been updated during a pendency of the transaction. Before evicting a line in a cache, the load buffer is snooped to ensure no load accessed the line to be evicted.

Abstract: Multiple lock assemblies are distributed on a chip, each lock assembly manage a lock application message for applying for a lock and a lock release message for releasing a lock that are sent by one small core. Specifically, embodiments include receiving a lock message sent by a small core, where the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; calculating, using the memory address of the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message.

Abstract: A system for determining a toggle value includes an input interface and a processor. The input interface is to receive a request for the toggle value associated with a toggle. The processor is to determine an indicated toggle value associated with the toggle; determine the toggle value associated with the toggle based at least in part on the indicated toggle value and a set of dependencies; and provide the toggle value associated with the toggle.

Abstract: Disclosed herein is a shared memory systems that use a combination of SBR and MRRR techniques to calculate eigenpairs for dense matrices having very large numbers of rows and columns. The disclosed system allows for the use of a highly scalable tridiagonal eigensolver. The disclosed system likewise allows for allocating a different number of threads to each of the different computational stages of the eigensolver.

Abstract: Embodiments for performing cooperative user mode scheduling between user mode schedulable (UMS) threads and primary threads are disclosed. In accordance with one embodiment, privileged hardware states are transferred from a kernel portion of a UMS thread to a kernel portion of a primary thread.

Abstract: Disclosed herein are systems and methods for managing information management operations. The system may be configured to employ a work flow queue to reduce network traffic and manage server processing resources. The system may also be configured to forecast or estimate information management operations based on estimations of throughput between computing devices scheduled to execute one or more jobs. The system may also be configured to escalate or automatically reassign notification of system alerts based on the availability of system alert recipients. Various other embodiments are also disclosed herein.

Abstract: An aspect includes include selective purging of entries from translation look-aside buffers (TLBs). A method includes building multiple logical systems in a computing environment, the multiple logical systems including at least two level-two guests. TLB entries are created in a TLB for the level-two guests by executing fetch and store instructions. A subset of the TLB entries is purged in response to a selective TLB purge instruction, the subset including TLB entries created for a first one of the level-two guests. Subsequent to the purging, verifying that the subset of the TLB entries were purged from the TLB, and determining whether a second one of the level-two guests is operational, the determining including executing at least one instruction that accesses a TLB entry of the second one of the level-two guests. Test results are generated based on the verifying and the determining. The test results are output.

Abstract: An approach is provided for managing a failure of a critical high availability (HA) component in a HA system. Critical HA components are identified. Categories are assigned to the identified components and weights are assigned to the categories. A current value indicating a performance of a component included in the identified components is obtained by periodically monitoring the components. A reference value for the performance of the component is received. A deviation between the current value and the reference value is determined. Based on the deviation, the component is determined to have failed. Based in part on the failed component, the categories, and the weights, a health index is determined in real-time. The health index indicates in part how much the component having failed affects a measure of health of the HA system.

Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.

Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

Abstract: A failure of communication between a first device and a second device is managed. A failure of communication between the first device and the second device is detected at a third device intermediate. The first data is transmitted from the third device to the first device. The first data indicates that the second device is unusable by the first device.

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract: A communication device includes: a receiving terminal; a storage device which stores a rule in which a condition regarding a bus system operation environment and an error tolerance scheme are associated with each other, and information regarding a path length; an error processor which determines the error tolerance scheme by utilizing the condition regarding the bus system operation environment and the rule so as to generate error tolerance information corresponding to the received data according to the determined error tolerance scheme; and a sending terminal for sending at least one packet including the error tolerance information and the data to the bus. The operation environment-related condition is a condition for granting an error tolerance for a transmission path of which a bus path length to another communication device, which is a destination of the data, is greater than a predetermined value.

Abstract: A method of firmware dump collection from a primary dump adapter is provided. The method includes identifying a primary system dump device and a secondary system dump device. An operating system (OS) dump coordinator writes non-disruptive state data to the primary system dump device, and writes disruptive state data to the secondary system dump device. Non-disruptive state data is requested from a hardware device adapter that is connected to the non-primary system dump device. Disruptive state data is requested from the hardware device adapter that is connected to the primary system dump device. The non-disruptive state data is written to the primary system dump device. Disruptive state data is written to the secondary system dump device.

Abstract: The embodiments relate to methods and systems for supporting a global effect analysis of a technical system. The embodiments include providing a meta-model stored in a computer readable storage medium, where the meta-model comprises at least one assembly of the technical system comprising parts having an associated set of failure mode elements, and where each failure mode element has an associated local effect element. The embodiments also include clustering local effect elements within global effect elements to generate a global effect tree stored within the meta-model.

Abstract: Systems and methods smart diagnosis using hosted resources with intelligent altering of boot order. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution by the processor, cause the IHS to: execute a first diagnostic module; identify a software or hardware malfunction as a result of the execution of the first diagnostic module; communicate the malfunction to a backend server; receive, from the backend server, an indication of a second diagnostic module to be subsequently executed by the IHS; and execute the second diagnostic module.

Abstract: An error guide including a set of error resolutions is stored. A set of log files is received which includes log entries generated by a set of processes associated with an application program. Each log entry includes a set of attributes including a first attribute specifying a message, a second attribute specifying a message identifier, a third attribute specifying process, and a fourth attribute specifying a message type. The log files are parsed based on the third and fourth attributes to identify a log entry associated with a particular process and message type. A message identifier of the log entry is compared with the error message guide to identify an error resolution that corresponds to a message of the log entry. The identified error resolution is displayed on an electronic screen.

Abstract: Techniques for recovering an enclosure are provided. A recovery program is retrieved from a recovery program repository. Results from a plurality of diagnostic tests are retrieved. The diagnostic test results are analyzed with the recovery program. The recovery program determines an enclosure recovery action. The enclosure is recovered using the determined recovery action.

Abstract: Disclosed is a battery management unit. The battery management unit according to the present disclosure can prevent performance of an erroneous control algorithm by executing an infinite loop when an error occurs on a communication line.

Abstract: A programmable logic controller includes an error detection unit, a data memory storing error occurrence information indicating, for each error kind, whether the error detection unit has detected an error, an error automatic cancellation processing unit determining whether an error factor of each error has been eliminated and, when the error factor has been eliminated, performing an error cancellation process including a process to change the error occurrence information to error non-occurrence, and an error-automatic-cancellation-permission determination unit referring to an error automatic cancellation permission setting and determining, when the error detection unit detects an error, whether the error is canceled by the error automatic cancellation processing unit on the basis of the error automatic cancellation permission setting, wherein the error automatic cancellation processing unit performs the error cancellation process on the error that the error-automatic-cancellation-permission determination unit

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for correcting a corrupted data sample using a trained deep neural network, the method including obtaining a feature representation of a corrupted data sample; and modifying the feature representation of the corrupted data sample to generate a feature representation of a corrected data sample by iteratively processing a current version of the feature representation of the corrupted data sample using the trained deep neural network to generate a current corruption score for the current version of the feature representation of the corrupted data sample and generating a less-corrupted version of the feature representation by performing an iteration of gradient descent against the current version of the feature representation of the corrupted data sample to reduce the current corruption score.

Abstract: According to one embodiment, a controller includes a decoder, calculation section, table creation, and control section. The decoder converts ECC frames into likelihood information based on a set table, generates decoded ECC frames by decoding using the likelihood information and switches the set table when there is an ECC frame in which the decoding is unsuccessful. The calculation section generates calculation data based on an ECC frame of calculation target among the decoded ECC frames and its ECC frame before decoded. The table creation section sets the new table to the decoder based on the calculation data. The control section controls the calculation target so that a calculation in the calculation section is not repeated for an ECC frame in which the decoding is successful.

Abstract: An operating method of a controller includes generating error reliability of data based on reliability information of one or more error-corrected bits of the data, wherein the data is read out from a semiconductor memory device and a hard decision ECC decoding to the data through a BCH code is determined as successful; and determining miscorrection of the data based on the error reliability.

Abstract: A storage system includes a storage server adapted to receive data, determine parity data based upon the data, and store the data and the parity data in a storage array associated with the storage server. The data and the parity data may be sent to a second storage server.

Abstract: A method begins by a dispersed storage (DS) processing module selecting a subset of a set of encoded data slices, wherein the subset of encoded data slices includes less than a decode threshold number of encoded data slices. When a receiving entity is affiliated with a first wireless communication resource, the method continues with the DS processing module outputting the subset of encoded data slices via the first wireless communication resource to the receiving entity, wherein the first wireless communication resource has a first wireless geographic coverage area. When the receiving entity is affiliated with a second wireless communication resource and is located outside of the first wireless geographic coverage area, the method continues with the DS processing module outputting one or more encoded data slices of the set of encoded data slices via the second wireless communication resource to the receiving entity.

Abstract: Example apparatus and methods produce a set of rateless erasure codes (e.g., fountain codes) for a file stored in a primary data store (e.g., hard drive) or in an archive system. The archive system may store the file in a redundant array of independent disks (RAID). A first subset of the rateless erasure codes are stored in an object storage using a synchronous protocol. A second subset of rateless erasure codes are stored in the object storage using an asynchronous protocol. The object storage system may inform the archive system when desired redundancy has been achieved or when desired redundancy has been lost. The archive system may buffer rateless erasure codes before providing the codes to the object storage to improve performance. A failure in the archive system or object storage system may be mitigated by retaining the file in the primary data store until the desired redundancy is achieved.