Patents Issued in October 24, 2017
  • Patent number: 9798618
    Abstract: Data placement for loss protection in a storage system includes constructing multiple logical compartments. Each logical compartment includes a placement policy including a set of storage placement rules for determining permitted placement of storage symbols, and a balancing policy for balancing placement of the storage symbols for each volume among physical storage containers. A first logical compartment of the multiple logical compartments is data loss independent with respect to a second logical compartment.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventor: David D. Chambliss
  • Patent number: 9798619
    Abstract: A method includes identifying an independent data object of a plurality of independent data objects for retrieval from dispersed storage network (DSN) memory. The method further includes determining a mapping of the plurality of independent data objects into a data matrix, wherein the mapping is in accordance with the dispersed storage error encoding function. The method further includes identifying, based on the mapping, an encoded data slice of the set of encoded data slices corresponding to the independent data object. The method further includes sending a retrieval request to a storage unit of the DSN memory regarding the encoded data slice. When the encoded data slice is received, the method further includes decoding the encoding data slice in accordance with the dispersed storage error encoding function and the mapping to reproduce the independent data object.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason K. Resch, Greg Dhuse, Andrew Baptist
  • Patent number: 9798620
    Abstract: Techniques are disclosed relating to writing data across multiple storage blocks in a storage device. In one embodiment, physical erase blocks in a bank of a storage device are erasable. Ones of the physical erase blocks may be associated with different respective communication channels. In such an embodiment, a data stripe may be written across a set of physical erase blocks such that the set of physical erase blocks includes physical erase blocks of different banks and includes physical erase blocks associated with different communication channels. In some embodiments, a request to read a portion of the data stripe may be received. In response to the request, a determination may be made that one of the set of physical erase blocks is unavailable to service the request. The request may then be serviced by reassembling data of the unavailable physical erase block.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: October 24, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Robert Wood, Jeremy Fillingim, Pankaj Mehra
  • Patent number: 9798621
    Abstract: In a dispersed storage network where slices of secure user data are stored on geographically separated storage units (44), a managing unit (18) connected to the network (20) may seek to broadcast and update secure access control list information across the network (20). Upon a target device (e.g., devices 12, 14, 16, 18, or 44) receiving the broadcast the target device creates and sends an access control list change notification message to all other system devices that should have received the same broadcast if the broadcast is a valid request to update access control list information. The target device waits for responses from the other system devices to validate that the broadcast has been properly sent to a threshold number of other system devices before taking action to operationally change local data in accordance with the broadcast.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason K. Resch, Andrew Baptist
  • Patent number: 9798622
    Abstract: Described is an apparatus which comprises: a first encoder to encode data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion, and each codeword of the set to be stored in a separate memory bank of a memory block; and a second encoder to encode the data portions of each codeword of the set with a second error correction scheme, the second encoder to generate a combined codeword having a data portion and a corresponding parity portion, wherein the corresponding parity portion of the combined codeword is to be stored in an additional memory bank of the memory block.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: October 24, 2017
    Assignee: Intel Corporation
    Inventor: Ravi H. Motwani
  • Patent number: 9798623
    Abstract: An occurrence of at least one storage error is determined in an addressable portion of a primary storage storing a block of data. In response to determining the occurrence of the at least one storage error, it is determined whether the block of data is available in cache storage. In response to determining the block of data is cached, the cached block of data is used rather than the block of data from the addressable portion of the primary storage.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: October 24, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Yunaldi Yulizar, Luke W. Friendshuh
  • Patent number: 9798624
    Abstract: Systems and methods for automated fault recovery. In some embodiments, an Information Handling System (IHS) includes a processor and a Basic I/O System (BIOS) coupled to the processor, the BIOS having program instructions that, upon execution, cause the IHS to: identify a failure during execution of an Operating System; select, by the BIOS, a given one of a plurality of recovery tools previously registered with the BIOS; and launch the given recovery tool by the BIOS.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: October 24, 2017
    Assignee: Dell Products, L.P.
    Inventors: Dirie N. Herzi, Abeye Teshome
  • Patent number: 9798625
    Abstract: Systems and methods for providing agentless and/or pre-boot technical support, and Field Replaceable Unit (FRU) isolation. In some embodiments, an Information Handling System (IHS) includes an embedded controller (EC) distinct from any processor or Basic I/O System (BIOS), the EC having program instructions stored thereon that, upon execution, cause the IHS to: implement a network stack independently of an operational status of the processor or BIOS, perform one or more diagnostic operations upon the IHS, and communicate a result of the one or more diagnostic operations to a remote server using the network stack.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: October 24, 2017
    Assignee: Dell Products, L.P.
    Inventors: Abeye Teshome, Dirie N. Herzi
  • Patent number: 9798626
    Abstract: A method for implementing a change capture system using an event publishing system as a database recovery log is provided. The method may include determining a set of data based on a description of events for which change capture is possible. The method may also include selecting at least one item of data from within the determined set of data, wherein the at least one item of data requires change capture to be performed. Additionally, the method may include identifying at least one published event, wherein the at least one published event is produced by the event publishing system. The method may include instructing the event publishing system to deliver the at least one identified published event to the change capture system. Furthermore, the method may include receiving the at least one identified published event. The method may also include processing the at least one published event.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Cadarette, James D. Spyker
  • Patent number: 9798627
    Abstract: Various systems and methods to display information regarding duplication operations and to configure duplication operations. For example, information regarding policies that can be included in a duplication operation is presented via a display. The display receives selection of one or more of the policies. In response to the selection, the display updates to reflect how much of a bucket has been allocated and how much is available, where the bucket specifies an amount of time and is calculated as a function of a duplication window duration.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: October 24, 2017
    Assignee: Veritas Technologies LLC
    Inventor: Thomas G. Clifford
  • Patent number: 9798628
    Abstract: Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: October 24, 2017
    Assignee: Rambus Inc.
    Inventors: Steven Woo, David Secker, Ravindranath Kollipara
  • Patent number: 9798629
    Abstract: Exemplary methods for predicting backup and restore failure include analyzing, at a management server, resource utilization statistics periodically collected during backup of data from a source storage system to a target storage system. In one embodiment, the methods include creating a predictive model based on the analysis of the collected resource utilization statistics. In one embodiment, the method includes predicting, using the predictive model, whether a backup time or a restore time of future backup will exceed a backup time threshold or restore time threshold, respectively.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: October 24, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Philip Shilane, Grant Wallace
  • Patent number: 9798630
    Abstract: Providing a snapshot of a physical memory region as of a specified time includes: sending, from a first processor to a second processor, a request to generate a snapshot of the physical memory region as of the specified time; and generating, using the second processor, the snapshot of the physical memory region based at least in part on a known state of the physical memory region and log information about update activity of the physical memory region.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: October 24, 2017
    Assignee: Intel Corporation
    Inventor: David R. Cheriton
  • Patent number: 9798631
    Abstract: This document relates to data storage techniques. One example can buffer write commands and cause the write commands to be committed to storage in flush epoch order. Another example can maintain a persistent log of write commands that are arranged in the persistent log in flush epoch order. Both examples may provide a prefix consistent state in the event of a crash.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: October 24, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: James W. Mickens, Amar Phanishayee, Vijaychidambaram Velayudhan Pillai
  • Patent number: 9798632
    Abstract: A computer cluster includes a group of connected computers that work together essentially as a single system. Each computer in the cluster is called a node. Each node has a boot device configured to load an image of an operating system into the node's main memory. Sometimes the boot device of a first node experiences a problem that prevents the operating system from loading. This can affect the entire cluster. Some aspects of the disclosure, however, are directed to operations that determine the problem with the first node's boot device based on a communication sent via a first communications network. Further, the operations can communicate to the first node a copy of boot data from a second node's boot device. The copy of the boot data is sent via a second communications network different from the first communications network. The copy of the boot data can solve the first boot device's problem.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: October 24, 2017
    Assignee: NetApp, Inc.
    Inventors: NandaKumar Ravindranath Allu, Prateek Bhatnagar, Venkata Ramprasad Darisa
  • Patent number: 9798633
    Abstract: An access point IHS group controller failover system includes a first access point IHS group controller that controls a first access point IHS group that includes plurality of access point IHSs. Following a failure of the first access point IHS group controller, the first access point IHS broadcasts a first access point IHS identifier to a first subset of the plurality of access point IHSs. The first access point IHS then registers the first subset of the plurality of access point IHSs as members of a second access point IHS group, and controls at least some functions of the second access point IHS group. When the first access point IHS detects activity from the first access point IHS group controller, it instructs the first subset of the plurality of access point IHSs in the second access point IHS group to reconnect to the first access point IHS group controller.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: October 24, 2017
    Assignee: Dell Products L.P.
    Inventors: Rabah S. Hamdi, Christopher Stephen Petrick
  • Patent number: 9798634
    Abstract: A failover manager may be configured to determine a plurality of tenants executable on a server of a plurality of servers, each tenant being a virtual machine executable on the server in communication with at least one corresponding user. The failover manager may include a replicated tenant placement selector configured to dispatch a first replicated tenant for a first tenant of the plurality of tenants to a first standby server of the plurality of servers, and configured to dispatch a second replicated tenant for a second tenant of the plurality of tenants to a second standby server of the plurality of servers. The failover manager also may include a replicated tenant loader configured to activate, based on a failure of the server, the first replicated tenant on the first standby server to replace the first tenant, and the second replicated tenant on the second standby server to replace the second tenant.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: October 24, 2017
    Assignee: SAP SE
    Inventors: Mengjiao Wang, Yu Cheng, Wen-Syan Li
  • Patent number: 9798635
    Abstract: Allocating resources during failure recovery is provided. A set of one or more service level agreement tiers are identified corresponding to a client workload that was being processed by a failed computing environment. A highest level tier is selected in the set of one or more service level agreement tiers. Recovery resources are allocated in a failover computing environment to the highest level tier sufficient to meet a service level agreement associated with the highest level tier. The highest level tier is recovered in the set of one or more service level agreement tiers using the recovery resources in the failover computing environment. In response to recovering the highest level tier, tier resources of the highest level tier are reduced to a steady state level of processing in the failover computing environment.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Richard E. Harper, Valentina Salapura, Mahesh Viswanathan
  • Patent number: 9798636
    Abstract: Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage system is provided that includes storage drives each comprising a PCIe interface, and configured to store data and retrieve the data stored on associated storage media responsive to data transactions received over a switched PCIe fabric. The data storage system includes processors configured to each manage only an associated subset of the storage drives over the switched PCIe fabric. A first processor is configured to identify first data packets received over a network interface associated with the first processor within a network buffer of the first processor as comprising a storage operation associated with at least one of the plurality of storage drives managed by a second processor, and responsively transfer the first data packets into a network buffer of the second processor.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: October 24, 2017
    Assignee: Liqid Inc.
    Inventors: Jason Breakstone, Christopher R. Long, James Scott Cannata
  • Patent number: 9798637
    Abstract: An information processing apparatus including a removable storage device for storing data includes a control unit that determines whether communication is possible with the storage device and, if communication with the storage device is determined not to be possible, prohibit data from being written to the storage device. When the information processing apparatus is started up, the control unit again determines whether communication is possible with the storage device to which the control unit prohibits data writing and permits data writing to the storage device if communication with the storage device is determined to be possible.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 24, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Nobuyasu Ito
  • Patent number: 9798638
    Abstract: Systems and methods which provide mount catalogs to facilitate rapid volume mount are shown. A mount catalog of embodiments may be provided for each aggregate containing volumes to be mounted by a takeover node of a storage system. The mount catalog may comprise a direct storage level, such as a DBN level, based mount catalog. Such mount catalogs may be maintained in a reserved portion of the storage devices containing a corresponding aggregate and volumes, wherein the storage device reserved portion is known to a takeover node. In operation according to embodiments, a HA pair takeover node uses a mount catalog to access the blocks used to mount volumes of a HA pair partner node prior to a final determination that the partner node is in fact a failed node and prior to onlining the aggregate containing the volumes.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: October 24, 2017
    Assignee: NetApp, Inc.
    Inventor: Bipul Raj
  • Patent number: 9798639
    Abstract: A failover system, server, method, and computer readable medium are provided. The system includes a primary server for communicating with a client machine and a backup server. The primary server includes a primary session manager, a primary dispatcher a primary order processing engine and a primary verification engine. The method involves receiving an input message, obtaining deterministic information, processing the input message and replicating the input message along with the deterministic information.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: October 24, 2017
    Assignee: TSX INC.
    Inventors: Gregory A. Allen, Tudor Morosan, Adrian G. Dumitrache, Patrick J. Philips
  • Patent number: 9798640
    Abstract: Systems and methods are described for testing customer premise equipment in an offline fashion. According to certain embodiments, a testing system including one or more computing devices can identify a test scenario that includes information associated with one or more commands and expected results associated with the commands. Such commands can be executed by customer premise equipment. One or more respective images associated with the execution of a command can be captured, and information associated with the command, the associated expected result, and one or more respective images can be displayed for evaluation by a user to determine whether the command is operating properly in the customer premise equipment that executed the command. Certain embodiments describe a confidence level which can correspond to a number of images to be captured in order to decrease the possibility that content was not captured for evaluation.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: October 24, 2017
    Assignee: Cox Communications, Inc.
    Inventor: Michael David Rucker
  • Patent number: 9798641
    Abstract: Methods and apparatus to increase cloud availability and silicon isolation using secure enclaves. A compute platform is configured to host a compute domain in which a plurality of secure enclaves are implemented. In conjunction with creating and deploying secure enclaves, mapping information is generated that maps the secure enclaves to platform/CPU resources, such as Intellectual Property blocks (IP) belong to the secure enclaves. In response to platform error events caused by errant platform/CPU resources, the secure enclave(s) belonging to the errant platform/CPU are identified via the mapping information, and an interrupt is directed to that/those secure enclave(s). In response to the interrupt, a secure enclave may be configured to one or more of handle the error, pass information to another secure enclave, and teardown the enclave. The secure enclave may execute an interrupt service routine that causes the errant platform/CPU resource to reset without resetting the entire platform or CPU, as applicable.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: October 24, 2017
    Assignee: Intel Corporation
    Inventors: Robert C. Swanson, Theodros Yigzaw, Eswaramoorthi Nallusamy, Raghunandan Makaram, Vincent J. Zimmer
  • Patent number: 9798642
    Abstract: Methods for reducing power consumption and power leakage in hybrid storage clusters is provided. More specifically, the method is for allocating an appropriate server amongst a plurality of servers in a network by identifying an application to be executed in a network, wherein the network comprises a plurality of servers configured to execute the applications, and each server further comprising a hybrid memory system; based on the application to be executed, dynamically identifying resources to execute the application based on the hybrid memory system available and the power consumption for executing the application; and dynamically allocating the application to the identified resource for execution.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bhushan P. Jain, Sri Ramanathan, Sandeep R. Patil, Abhinay R. Nagpal
  • Patent number: 9798643
    Abstract: A system and method are provided for managing internal-computer system communications in an SPI management system. The system includes a storage device, at least one serial bus interface to interface with a serial bus, and a processing unit that accesses via the at least one serial bus interface, master data propagating from a master device along the serial bus. The processing unit stores, in the storage device, at least one of timing and phase data related to clock pulses associated with the master data, and a phase relationship between the clock pulses and at least one of the master data and return data propagating from a slave device in response to the master data.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 24, 2017
    Assignee: Goodrich Corporation
    Inventors: Jonathan C. Jarok, Scott W. Ramsey
  • Patent number: 9798644
    Abstract: A method includes receiving a plurality of metric-pattern combinations, each including a respective performance metric and a respective graph pattern. The method also includes receiving a corresponding parameter value for a parameter of each respective graph pattern. The method further includes determining an event equation comprising the plurality of metric-pattern combinations and a boolean operator. The method still further includes evaluating the event equation by determining a respective graph pattern fit curve by applying the corresponding parameter value to the respective graph pattern, and determining an operand value based on whether associated performance data for the respective performance metric exhibits the associated graph pattern by matching the respective graph pattern fit curve to the associated performance data. Evaluating the operand values using the boolean operator to determine a result. The method additionally includes displaying a notification, at a user interface, based on the result.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: October 24, 2017
    Assignee: CA, Inc.
    Inventors: Laura Beck, Rajagopal Marripalli, Timothy Smith
  • Patent number: 9798645
    Abstract: An electronic tracing process includes packing both stall (215) and reason (219) data into a single high priority timing information stream. An integrated circuit includes an electronic processor (110), and a tracing circuit (120) operable to pack both stall and events data into a single timing information stream. Other circuits, processes and systems are also disclosed.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: October 24, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Kanika Ghai Bansal, Dipan Kumar Mandal, Gary A. Cooper, Bryan J. Thome
  • Patent number: 9798646
    Abstract: A data processing apparatus has processing circuitry which can execute instructions at one of several privilege levels. A plurality of performance monitoring circuits are included. In response to an instruction executed at a first privilege level, first configuration data can be set for controlling performance monitoring by a first subset of performance monitoring circuits. A disable control flag can be set in response to an instruction executed at a second privilege level higher than the first privilege level. If the disable control flag has a predetermined value then performance monitoring control circuitry disables performance monitoring by the first subset of performance monitoring circuits while the processing circuitry is executing instructions at the second privilege level.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: October 24, 2017
    Assignee: ARM Limited
    Inventors: Michael John Williams, Simon John Craske
  • Patent number: 9798647
    Abstract: A method and system for displaying application performance data. In an embodiment, performance data collected from an application is logically associated with a display window generated by the application. A displayable performance indicator determined. The displayable performance indicator is visually modifiable to correlate to variations in the performance data. A performance category selection signal and a data collection filter metric selection signal are received by a performance analytics display module. The display module simultaneously displays, on a display device, an indicator of a performance category based on the performance selection signal, an indicator of a data collection filter metric based on the filter metric selection signal, and an image of the display window that includes the performance indicator.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 24, 2017
    Assignee: CA, Inc.
    Inventors: Jonathan B. Lindo, Seshadri Venkataraman, Vamsee K. Lakamsani, Harshit Bapna
  • Patent number: 9798648
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for matching and attributing code violations. One of the methods includes receiving a plurality of snapshots of a code base, including data representing a revision graph of the snapshots of the code base and data representing respective violations in each of the plurality of snapshots. A plurality of transitively matched violations in the code base are generated, wherein each transitively matched violation represents a respective sequence of matching violations from a first violation of a first snapshot to a second violation of a second snapshot, wherein each transitively matched violation identifies a respective first violation representing an initial occurrence of a coding defect in the code base and a respective second violation representing a last occurrence of the coding defect in the code base.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 24, 2017
    Assignee: Semmle Limited
    Inventors: Anders Starcke Henriksen, Ricardo Pescuma Domenecci
  • Patent number: 9798649
    Abstract: This disclosure involves debugging code for resource-constrained intelligent devices contemporaneously with executing object code on the intelligent device. For example, object code is transmitted to a radio device. A program counter entry is provided from the radio device to a computer via a communication link contemporaneously with a pause in execution of the object code at the radio device. A correspondence between the program counter entry and a portion of assembly code, which was used to generate the object code, is identified and is used to generate a list of additional program counter entries for pausing the object code's execution. The list is provided from the computer to the radio device and is used to pause the object code's execution at the radio device. Log data is provided from the radio device to the computer for display after pausing the object code's execution at one of these program counter entries.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: October 24, 2017
    Assignee: Landis+Gyr Innovations, Inc.
    Inventors: John Bettendorff, Tribhuwan Chandra Kandpal
  • Patent number: 9798650
    Abstract: Embodiments of the present invention are directed to a computer implemented web based application testing system and method for testing at least one software application. The system and method receiving at least one test selection from a user using a user interface at a display device. The test selection may include at least one of a feature, a scenario, a background and a predefined condition. A feature file generation engine may then generate at least one feature file based on the test selection. Also, the feature file may be stored in a non-transitory computer memory. A feature file execution engine may execute the feature file and generate at least one execution result. A reporting engine may then generate a report based on the execution result. The execution result may then be displayed at the web dashboard.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: October 24, 2017
    Assignee: JPMorgan Chase Bank, N.A.
    Inventor: Naveen Verma
  • Patent number: 9798651
    Abstract: A method of holding information for identifying a cause for an object becoming problematic and presenting the information to a user. The method ascertains the cause of memory consumption by a program in a computer system. This method includes: acquiring a first call path related to the creation of an object from a memory; acquiring a second call path related to the connection to the object from the memory; and determining a common part of the acquired first and second call paths, wherein the common part indicates the cause in the program.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kiyokuni Kawachiya, Kazunori Ogata, Michiaki Tatsubori
  • Patent number: 9798652
    Abstract: A computer-implemented method for automatically identifying a faulty behavior of a control system. The method includes receiving, at a test processor, a description of the faulty behavior. The method also includes selecting, using the test processor, a goal state based on a heuristic decision. The method also includes selecting, using the test processor, a selected system state. The method also includes selecting, using the test processor, a selected variable to the control system based on the goal state. The method also includes loading, from a memory, a control model of the control system. The method also includes performing, using the test processor, a simulation of the control model using the selected variable and the selected system state as parameters of the simulation. The method also includes determining, using the test processor, whether the faulty behavior was observed based on the simulation.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: October 24, 2017
    Assignees: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC., UNIVERSITY JOSEPH FOURIER
    Inventors: James P. Kapinski, Jyotirmoy V. Deshmukh, Xiaoqing Jin, Thao Dang, Tommaso Dreossi
  • Patent number: 9798653
    Abstract: Adapted speech models produce fluent synthesized speech in a voice that sounds as if the speaker were fluent in a language in which the speaker is actually non-fluent. A full speech model is obtained based on fluent speech in the language spoken by a first person who is fluent in the language. A limited set of utterances is obtained in the language spoken by a second person who is non-fluent in the language but able to speak the limited set of utterances in the language. The full speech model of the first person is then processed with the limited set of utterances of the second person to produce an adapted speech model. The adapted speech model may be stored to a multi-lingual speech model as a child node of a root with an associated language selection question and branches pointed to the adapted speech model and other speech models, respectively.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: October 24, 2017
    Assignee: Nuance Communications, Inc.
    Inventors: Xu Shao, Andrew Breen
  • Patent number: 9798654
    Abstract: Methods and systems for managing memory and stress to memory systems. A method for managing memory includes receiving from a software application memory retention requirements for application data. The memory retention requirements include storage duration length and/or criticality of data retention. The method also includes storing the application data in one of a plurality of memory regions in non-volatile memory based on the memory retention requirements and memory retention characteristics of the memory regions. Each memory region may have different memory retention characteristics.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: October 24, 2017
  • Patent number: 9798655
    Abstract: Flash memory on a flash memory device is virtualized using compression that is native to the flash memory device. Through compression, the flash memory device is used to logically store more data in a virtual address space that is larger than the physical address space of the flash memory device. Physical storage capacity of a flash memory device may prevent further storage of data even when the virtual address space is not fully populated. Because compressibility may vary, the extent to which the virtual address space may be populated before physical storage capacity is reached varies. The approaches for virtual memory described herein rely on the memory device client to monitor when this point is reached. In addition, the memory device client is responsible for freeing space as needed to accommodate subsequent requests to store data in the flash memory.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: October 24, 2017
    Assignee: Oracle International Corporation
    Inventors: Nilesh Coudhury, Selcuk Aya, Zheren Zhang, Kothanda Umamageswaran, Juan Loaiza
  • Patent number: 9798656
    Abstract: A method of operating a memory controller includes; counting a number of read operations directed to a page-group of data stored in a block and generating a first read count number, then comparing the first read count number with a first reference count threshold among a first set of reference count thresholds associated with the page-group, and upon determining that the first read count number exceeds the first reference count threshold, performing a copy-back operation of the page-group data from the block to another block.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: October 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Chul Lee, Moo Sung Kim
  • Patent number: 9798657
    Abstract: A method of operating a data storage device includes programming non-fully programmed memory blocks at a point in time when a reference time elapses from a point in time when each of the memory blocks is physically erased, acquiring a first interval and a second interval, calculating a disturb index based on the first interval and the second interval, selecting a victim block for garbage collection based on the disturb index, and copying valid page data of the victim block into a free block. The first interval is defined by a point in time when each of the memory blocks is physically erased and a point in time when each of the memory blocks is fully programmed. The second interval is an interval during which a fully programmed state is maintained after a point in time when each of the memory blocks is fully programmed.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: October 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangkwon Moon, Seung-Yeon Lee, Heewon Lee, In Hwan Doh, NamWook Kang
  • Patent number: 9798658
    Abstract: In a first process, based on data of a FLASH status 0 area included in a first block of a flash ROM, a rewriting process including erasing, writing and verifying on blocks of the flash ROM storing a user program to be rewritten based on contents of a user program for rewriting is controlled. In a second process, the rewriting process is carried out without regard to the data of the FLASH status 0 area. In the first process, writing on the FLASH status 0 area is not carried out in the rewriting process on the first block of the flash ROM, but writing on the FLASH status 0 area is carried out based on the contents of the user program for rewriting after carrying out the rewriting process on a last block of the flash ROM.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: October 24, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Satoshi Shizuka
  • Patent number: 9798659
    Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: October 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chi Weon Yoon, Dong Hyuk Chae, Sang-Wan Nam, Jung-Yun Yun
  • Patent number: 9798660
    Abstract: Data exchange between a memory mapped interface and a streaming interface may include receiving sub-packets of a packet from a first interface, storing the sub-packets within a memory at addresses determined according to a ratio of a width of the first interface and a width of a second interface, and determining occupancy, of the memory as the sub-packets are stored. Responsive to determining that the occupancy of the memory meets a trigger level, sub-packets may be read from the memory at addresses determined according to the ratio and sending the sub-packets using the second interface.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: October 24, 2017
    Assignee: XILINX, INC.
    Inventor: Robert Bellarmin Susai
  • Patent number: 9798661
    Abstract: A receiving controller which receives a read request out of first and second storage controllers transfers the read request to an associated controller which is associated with a read source storage area out of the first and second storage controllers when the receiving controller is not the associated controller. It is however the receiving controller that reads the read-target data from a read source storage device, writes the read-target data to a cache memory of the receiving controller, and transmits the read-target data written in the cache memory of the receiving controller to a host apparatus.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: October 24, 2017
    Assignee: HITACHI, LTD.
    Inventors: Yoshifumi Mimata, Yuko Matsui, Shintaro Kudo
  • Patent number: 9798662
    Abstract: In accordance with the present disclosure, a system and method for performing a system memory save in tiered or cached storage during transition to a decreased power state is disclosed. As disclosed herein, the system incorporating aspects of the present invention may include a solid-state drive, volatile memory, and at least one alternate storage media. Upon transition to a decreased power state, at least some of the data in the solid-state drive may be transferred to the at least one alternate storage media. After the SSD data is transferred, data stored in volatile system memory, such as a system context, may be transferred to the SSD memory. With the system context saved in SSD memory, power to the volatile system memory may be turned off.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 24, 2017
    Assignee: Dell Products L.P.
    Inventors: William F. Sauber, Mukund P. Khatri
  • Patent number: 9798663
    Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Vesselina K. Papazova, Hanno Ulrich
  • Patent number: 9798664
    Abstract: Provided method includes storing a first cache snap shot including cache profiling information regarding a cache when a first process being executed by a cycle accurate simulator is terminated; storing a second cache snap shot including the cache profiling information on the cache when a second process is executed in the cycle accurate simulator; comparing the second cache snap shot of the second process and the first cache snap shot of the first process to readjust any one value of a cache hit value and a cache miss value which are present in the second cache snap shot of the second process; and correcting the cache profiling information which is stored in the first cache snap shot of the first process by reflecting the readjusted any one value of the cache hit value and the cache miss value present in the second cache snap shot of the second process.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-seok Lee, Tai-song Jin
  • Patent number: 9798665
    Abstract: A method that may include determining, for each user of a group of users, a time difference between an event of a first type that is related to a storage of a user data unit of the user within a cache of a storage system and to an eviction of the user data unit from the cache, in response to (a) a service-level agreement (SLA) associated with the user and to (b) multiple data hit ratios associated with multiple different values of a time difference between events of the first type and evictions, from the cache, of multiple user data units of the user; and evicting from the cache, based upon the determination, one or more user data units associated with one or more users of the group.
    Type: Grant
    Filed: December 20, 2015
    Date of Patent: October 24, 2017
    Assignee: INFINIDAT LTD.
    Inventor: Yechiel Yochai
  • Patent number: 9798666
    Abstract: A processor implementing techniques to supporting fault information delivery is disclosed. In one embodiment, the processor includes a memory controller unit to access an enclave page cache (EPC) and a processor core coupled to the memory controller unit. The processor core to detect a fault associated with accessing the EPC and generate an error code associated with the fault. The error code reflects an EPC-related fault cause. The processor core is further to encode the error code into a data structure associated with the processor core. The data structure is for monitoring a hardware state related to the processor core.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 24, 2017
    Assignee: Intel Corporation
    Inventors: Rebekah M. Leslie-Hurd, Carlos V. Rozas, Francis X. McKeen, Ilya Alexandrovich, Vedvyas Shanbhogue, Bin Xing, Mark W. Shanahan, Simon P. Johnson
  • Patent number: 9798667
    Abstract: An aspect includes a method of streaming stress testing in a cache memory system. The method includes configuring, by a streaming stress generator, one or more streams of cache lines in the cache memory system to be accessed by a cache prefetch engine of a processor. One or more stream parameters are randomized to vary a streaming stress applied by the one or more streams to the cache memory system. The one or more streams are generated as read or write requests to the cache lines as prefetches from the cache prefetch engine absent a request for the cache lines from a processor core of the processor. A determination is made as to whether any faults are detected while the one or more streams are prefetched.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Shakti Kapoor