Abstract: A method for making a conductive film includes the steps of: depositing a conductive metal film on a substrate to form a metal-coated substrate; depositing a fiber pattern on the conductive metal film of the metal-coated substrate to form a masked substrate, the fiber pattern defining protected metal and exposed metal of the conductive metal film; removing the exposed metal from the conductive metal film of the masked substrate to form a protected conductive film; and removing the fiber pattern from the protected conductive film to expose the protected metal and provide a metal pattern on the substrate. An annealing step con be employed after depositing the fiber pattern to increase the surface area of contact between the fiber pattern and the conductive metal film.

Abstract: This application is directed to an apparatus for creating microwave radiation patterns for an object detection system. The apparatus includes a waveguide conduit having first slots at one side of the conduit and corresponding second slots at an opposite side of the conduit. The waveguide conduit is coupled to a microwave source for transmitting microwaves from the microwave source through the plurality of first slots. A plunger is moveably positioned in the waveguide conduit from one end thereof. The plunger allows the waveguide conduit to be tuned to generally optimize the power of the microwaves exiting the first slots. Secondary plungers are each fitted in one of the second slots to independently tune or detune microwave emittance through a corresponding first slot.

Abstract: A vacuum trap, a plasma etch system using the vacuum trap and a method of cleaning the vacuum trap. The vacuum trap includes a baffle housing; and a removable baffle assembly disposed in the baffle housing, the baffle assembly comprising a set of baffle plates, the baffle plates spaced along a support rod from a first baffle plate to a last baffle plate, the baffle plates alternately disposed above and below the support rod and alternately disposed in an upper region and a lower region of the baffle housing.

Abstract: Certain embodiments described herein are directed to detectors and systems using them. In some examples, the detector can include a plurality of dynodes, in which one or more of the dynodes are coupled to an electrometer. In some instances, an analog signal from a non-saturated dynode is measured and cross-calibrated with a pulse count signal to extend the dynamic range of the detector.

Abstract: An environmental radiation detector for detecting and distinguishing between all types of environmental radiation, including photons, charged particles, and neutrons. A large volume high pressure ionization chamber (HPIC) includes BF3 gas at a specific concentration to render the radiation detector sensitive to the reactions of neutron capture in Boron-10 isotope. A pulse-mode readout is connected to the ionization chamber capable of measuring both the height and the width of the pulse. The heavy charged products of the neutron capture reaction deposit significant characteristic energy of the reaction in the immediate vicinity of the reaction in the gas, producing a signal with a pulse height proportional to the reaction energy, and a narrow pulse width corresponding to the essentially pointlike energy deposition in the gas.

Abstract: A system for analyzing a sample includes a chromatographic device, a mass resolving device, and a data processor. The chromatographic device is configured to separate components of the sample using a chromatographic column. The mass resolving device is configured to characterize mass spectrographic properties of the separated components in an intact state, and fragment the separated components and characterize mass spectrographic properties of the resulting fragments.

Abstract: A device for mass spectroscopy comprising a chamber configured to provide an atomization source, a boost device configured to provide radio frequency energy to the chamber, and a mass analyzer in fluid communication with the chamber and configured to separate species based on mass-to-charge ratios is disclosed. In certain examples, a boost device may be used with a flame or plasma to provide additional energy to a flame or plasma to enhance desolvation, atomization, and/or ionization.

Abstract: Techniques can increase the resolution and accuracy of mass spectra obtained using ion traps through the use of the actual shape of the ion trap peaks, which is a series of smaller ion ejection events. The peak shapes are identified as changing over a common period of the trapping signal and the excitation signal, at which point the peak shapes repeat. Peak shapes can be characterized over the common period to create N basis functions, each for a different fractional mass for a given scan rate. The N basis functions over the common period can be duplicated (e.g., shifted by the common period) to obtain a set of mass functions that characterize fractional masses over the full scan range. The mass spectrum can be obtained by fitting the set of mass functions to the measured data to obtain a best fit contribution of each mass function to the measured data.

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a layer of material by placing the semiconductor wafer onto a carrier tape with the layer of material adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the layer of material within the singulation lines, and separating portions of the layer of material using a fluid.

Abstract: The present invention provides compounds of formula a process for their preparation, a solution comprising these compounds, a process for the preparation of a device using the solution, devices obtainable by the process and the use of the bis-azide-type compounds as cross-linkers.

Abstract: Silicon oxide layer is deposited on a semiconductor substrate by PECVD at a temperature of less than about 200° C. and is treated with helium plasma to reduce stress of the deposited layer to an absolute value of less than about 80 MPa. Plasma treatment reduces hydrogen content in the silicon oxide layer, and leads to low stress films that can also have high density and low roughness. In some embodiments, the film is deposited on a semiconductor substrate that contains one or more temperature-sensitive layers, such as layers of organic material or spin-on dielectric that cannot withstand temperatures of greater than 250° C. In some embodiments the silicon oxide film is deposited to a thickness of between about 100-200 ?, and is used as a hardmask layer during etching of other layers on a semiconductor substrate.

Abstract: Provided herein are methods and apparatus for improved flowable dielectric deposition on substrate surfaces. The methods involve improving nucleation and wetting on the substrate surface without forming a thick high wet etch rate interface layer. According to various embodiments, the methods may include single or multi-stage remote plasma treatments of a deposition surface. In some embodiments, a treatment may include exposure to both a reducing chemistry and a hydrogen-containing oxidizing chemistry. Apparatus for performing the methods are also provided.

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract: A semiconductor device includes: a substrate including a plurality of first active regions and a plurality of second active regions; a plurality of first gate structures formed above the first active regions, respectively, and a plurality of second gate structures formed above the second active regions, respectively; and a plurality of first source/drain layers corresponding to the first gate structures, respectively, and a plurality of second source/drain layers corresponding to the second gate structures, respectively, wherein a width of each of the first source/drain layers is smaller than a width of each of the second source/drain layers.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess.

Abstract: The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer.

Abstract: A method for forming patterns of a semiconductor device includes preparing an etch target layer defined with a first region and a second region; forming a regular first feature which is positioned over the etch target layer in the first region and a random feature which is positioned over the etch target layer in the second region; forming a regular second feature over the regular first feature; forming first and second cutting barriers which expose a portion of the random feature, over the random feature; cutting the regular first feature using the regular second feature, to form a regular array feature; cutting the random feature using the first cutting barrier and the second cutting barrier, to form a random array feature; and etching the etch target layer by using the regular array feature and the random array feature, to form a regular array pattern and a random array pattern.

Abstract: A method may include providing a substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane; directing an ion beam comprising angled ions to the substrate at a non-zero angle with respect to a perpendicular to the substrate plane, wherein a first portion of the substrate feature is exposed to the ion beam and wherein a second portion of the substrate feature is not exposed to the ion beam; directing molecules of a molecular species to the substrate wherein the molecules of the molecular species cover the substrate feature; and providing a second species to react with the molecular species, wherein selective growth of a layer comprising the molecular species and the second species takes place such that a first thickness of the layer grown on the first portion is different from a second thickness grown on the second portion.

Abstract: A method for forming a semiconductor device includes depositing an epitaxial layer on a semiconductor substrate, forming an oxygen diffusion region within the epitaxial layer by oxygen diffusion from the semiconductor substrate into a part of the epitaxial layer and tempering at least the oxygen diffusion region of the epitaxial layer at a temperature between 400° C. and 480° C. for more than 15 minutes.

Abstract: An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also include at least one group of dies placed in the frontside cavity and encapsulant that secures the position of the at least one group of dies relative to the cavity wafer. Further, a layer of the encapsulant can cover a backside of the cavity wafer.

Abstract: A method of etching an insulation layer on an object to be processed in a process chamber in which an upper electrode and a lower electrode are placed facing each other, includes supplying a process gas that includes fluorocarbon gas and silicon tetrafluoride (SiF4) gas into the process chamber; applying high frequency power to at least one of the upper electrode and the lower electrode, to generate plasma; and etching the insulation layer by the generated plasma via a mask.

Abstract: A pattern-forming method includes forming a base pattern having recessed portions on a front face side of a substrate. A first composition is applied on lateral faces of the recessed portions of the base pattern, to form a coating. The first composition includes a first polymer which includes on at least one end of a main chain thereof a group capable of interacting with the base pattern. A surface of the coating is contacted with a highly polar solvent. The recessed portions are filled with a second composition. The second composition includes a second polymer which is capable of forming a phase separation structure through directed self-assembly. Phase separation is permitted in the second composition to form phases. A part of the phases is removed to form a miniaturized pattern. The substrate is etched directly or indirectly using the miniaturized pattern as a mask.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion.

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

Abstract: A carrier substrate having a plurality of receptacles each for receiving and carrying a semiconductor chip is provided. Semiconductor chips are arranged in the receptacles, and metal is plated in the receptacles to form a metal structure on and in contact with the semiconductor chips. The carrier substrate is cut to form separate semiconductor devices.

Abstract: An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.

Abstract: Disclosed is a technique capable of preventing an encapsulating material from covering a heat-dissipating surface of a semiconductor module, which releases heat of a switching element. Specifically disclosed a step for manufacturing a semiconductor module including a submodule having a collector and an emitter with heat-dissipating surfaces, including a step for placing the submodule in the cavity so that the submodule is pressed by the pressing device while covering the heat-dissipating surface of the emitter with the pressing device and covering the heat-dissipating surface of the collector with the lower mold, and a step for feeding the encapsulating material to the cavity by moving the piston so that the pressure of the cavity measured by the pressure measuring device does not exceed the pressure at which the pressing device presses the submodule.

Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

Abstract: There is provided a substrate processing apparatus including: a substrate holder configured to hold a substrate on which a resist pattern is formed; a rinse solution supply unit configured to supply a rinse solution onto the substrate held by the substrate holder; a vapor supply unit configured to supply vapor of a first processing solution, which hydrophobicizes the resist pattern, onto the substrate on which the rinse solution is supplied from the rinse solution supply unit; and a rinse solution removing unit configured to remove the rinse solution from the substrate in an atmosphere including the vapor of the first processing solution supplied from the vapor supply unit.

Abstract: A workpiece support has a vessel having a top interior wall and a bottom interior wall. An interior cavity is defined between the top interior wall and bottom interior wall, wherein a support surface configured to support a workpiece. A plate is positioned within the interior cavity, dividing the interior cavity into a top cavity and a bottom cavity. The top and bottom cavities are fluidly coupled about a periphery of the plate. A first taper defined in one or more of the top interior wall and a top portion of the plate provides a substantially constant volume across a radial cross-section of the top cavity. A second taper defined in one or more of the bottom interior wall and a bottom portion of the plate provides a substantially constant volume across a radial cross-section of the bottom cavity. First and second ports fluidly couple the top and bottom cavities to respective first and second fluid channels.

Abstract: A transport module for loading and unloading a process module of a semiconductor production device includes a housing, which has a chamber that can be evacuated. The chamber has an opening that can be closed in a gas-tight manner by a closure device, which opens out into a first coupling duct associated with the transport module. The first coupling duct is connected with a flange plate using an elastic intermediate element, wherein the flange plate can be seated in a plane parallel, sealing manner on a flange plate of a second coupling duct associated with the process module. After opening the closure device, an evacuated loading and unloading duct to the process module is created. An inner and outer mounting section of the intermediate element is spaced apart from one another in the radial direction, with respect to the axis of the first coupling duct, by a deformation zone.

Abstract: The disclosure provides an apparatus for aligning first and second plates that are parallel to each other and have the same orientation. The apparatus includes a detector that detects composite small-angle X-ray scattering emitted from patterns of the first and second plates that are perpendicularly impinged by X-ray, and a moving unit that aligns the first and second plates according to a composite amplitude distribution of the composite small-angle X-ray scattering. Therefore, the first and second plates are aligned to each other accurately.

Abstract: A process for making a device comprising a thin functional substrate comprising bonding the functional substrate to a carrier substrate, forming functional components on the functional subsrate, and debonding the functional substrate from the carrier substrate by applying ultrasonic wave to the bonding interface. The application of ultrasonic wave aids the debonding step by reducing the tensile stress the functional substrate may experience.

Abstract: Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes an interconnect joint structure in the substrate creating a capture pad including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer. A method for making a semiconductor device is further disclosed.

Abstract: A method of filling cavities in a semiconductor structure during fabrication. A layer of a first material, e.g., a polysilazane, is deposited on the semiconductor, and subjected to a first thermal process to change its chemical composition, e.g., to change it to silicon dioxide. It is then etched back, and the cycle of deposition, and thermal processing is repeated. The etch-back may also be repeated in one or more of the cycles after the first cycle, and a second thermal process, that may increase the density of one or more of the deposited layers, may be performed in one or more of the cycles.

Abstract: A semiconductor device includes a buried epitaxially grown substrate and a silicon on insulator (SOI) layer. The device also includes a buried oxide (BOX) layer between the buried epitaxially grown substrate and the SOI layer, an isolation trench having first width (w1), a contact trench having a second width (w2) and a capacitive trench having a third width (w3). Methods are described that allow the formation of the trenches in a normal process flow.

Abstract: A method for filling gaps of semiconductor device and a semiconductor device with insulation gaps formed by the same are provided. First, a silicon substrate with plural protruding portions is provided, and the protruding portions are spaced apart from each other by gaps with predetermined depths. A nitride-containing layer is formed above the silicon substrate for covering the protruding portions and surfaces of the gaps as a liner nitride. Then, an amorphous silicon layer is formed on the nitride-containing layer. An insulating layer is formed on the amorphous silicon layer, and the gaps are filled up with the insulating layer.

Abstract: Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.

Abstract: A stack of layers is formed that includes first, second, and third dielectric layers. Contact plugs are then formed extending through the stack. Then a fourth dielectric layer is formed over the stack and contact plugs and trenches are formed through the fourth and third dielectric layers, extending to the second dielectric layer and exposing contact plugs.

Abstract: A flexible display and method of manufacturing the same are disclosed. In one aspect, the display includes a flexible substrate having a bending area and a non-bending area and a plurality of metal wirings formed over the flexible substrate in the bending area and the non-bending area. Each of the metal wirings which are formed in the bending area includes a pair of first hard wirings formed over the flexible substrate and a first soft wiring electrically connected to ends of the pair of first hard wirings.

Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.

Abstract: A method of processing a substrate includes: depositing an etch stop layer atop a first dielectric layer; forming a feature in the etch stop layer and the first dielectric layer; depositing a first metal layer to fill the feature; etching the first metal layer to form a recess; depositing a second dielectric layer to fill the recess wherein the second dielectric layer is a low-k material suitable as a metal and oxygen diffusion barrier; forming a patterned mask layer atop the substrate to expose a portion of the second dielectric layer and the etch stop layer; etching the exposed portion of the second dielectric layer to a top surface of the first metal layer to form a via in the second dielectric layer; and depositing a second metal layer atop the substrate, wherein the second metal layer is connected to the first metal layer by the via.

Abstract: A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package.

Abstract: A fingerprint sensor chip package structure including a circuit carrier and a fingerprint sensor chip is provided. The fingerprint sensor chip is disposed on the circuit carrier. The fingerprint sensor chip includes a chip body and a plurality of sensing structures. The chip body has an active surface, a fingerprint sensing back surface, a plurality of bond pads disposed on the active surface and a plurality of through holes. The chip body is electrically connected to the circuit carrier with the active surface facing the circuit carrier. The sensing structures are disposed in the through holes respectively. Each of the sensing structures includes a first dielectric layer, a first metal layer, a second dielectric layer and a second metal layer. The first dielectric layer is exposed on the fingerprint sensing back surface. The second metal layer extends to the active surface to be electrically connected to the corresponding bond pad.

Abstract: A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad.

Abstract: A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via (TSV) structure penetrating the first dielectric layer and extending into the semiconductor substrate. The TSV structure includes a conductive layer, a diffusion barrier layer surrounding the conductive layer and an isolation layer surrounding the diffusion barrier layer. A capping layer including cobalt is formed on the top surface of the conductive layer of the TSV structure.

Abstract: There is provided a laser processing method of laser-processing a wafer along a plurality of streets formed in a lattice manner on a top surface of the wafer, the wafer having devices formed in a plurality of regions partitioned by the streets, the laser processing method including: a wafer holding step of holding an undersurface of the wafer by a chuck table; a resin supplying step of supplying a water-soluble liquid resin to the top surface of the wafer; a protective film forming step of forming a protective film P on the wafer as a result of drying the water-soluble liquid resin by irradiating the water-soluble liquid resin with light from a xenon flash lamp; a laser irradiating step of irradiating the wafer with a laser beam through the protective film along the streets; and a cleaning step of cleaning the wafer after the laser irradiating step.

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.

Abstract: In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain regions are formed on opposite ends of the pair of fins and include silicon. A gate is wrapped around the pair of fins, between the source and drain regions.

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.