Abstract: A device comprising a III-N layer stack featuring a two-dimensional electron gas is disclosed, comprising: —a III-N layer; —a AI-III-N layer on top of the III-N layer; —a passivation layer on top of said AI-III-N layer, the passivation layer comprising Silicon Nitride (SiN); wherein said passivation layer comprises a fully crystalline sub layer at the AI-III-N interface and at least part of the fully crystalline sub layer comprises Al and/or B; and associated methods for manufacturing the device.

Abstract: N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate).

Abstract: A semiconductor device provided herein includes a trench in which a gate insulating layer (GIL) and a gate electrode are located. A step is provided in a lateral surface of the trench. The step surface descends toward a center of the trench. First and second regions are of a first conductivity type. A body region, a lateral region and a bottom region are of a second conductivity type. The first region, a body region, and the second region are in contact with the GIL at the upper lateral surface of the trench. The second region is in contact with the GIL at the lower lateral surface of the trench. A lateral region is in contact with the GIL at the lower lateral surface. A bottom region is in contact with the GIL at the bottom surface of the trench.

Abstract: A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

Abstract: Disclosed are performance-enhanced vertical devices (e.g., vertical field effect transistors (FETs) or complementary metal oxide semiconductor (CMOS) devices, which incorporate vertical FETs) and methods of forming such devices. A strained dielectric layer is positioned laterally adjacent to the gate of a vertical FET, increasing the charge carrier mobility within the channel region and improving performance. In a vertical n-type FET (NFET), the strain is compressive to improve electron mobility given the direction of current within the vertical NFET; whereas, in a vertical p-type FET (PFET), the strain is tensile to improve hole mobility given the direction of current within the vertical PFET. Optionally, the orientation of a vertical FET relative to the surface plane of the semiconductor wafer on which it is formed is also preplanned as function of the type of FET (i.e., NFET or PFET) for optimal charge carrier mobility and, thereby enhanced performance.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: A method includes forming a fin on a substrate. A first liner is formed on the fin. A first dielectric layer is formed above the first liner. A patterned hard mask is formed above the first dielectric layer and has a fin cut opening defined therein. Portions of the first dielectric layer and the first liner disposed below the fin cut opening are removed to expose a portion of the fin. The patterned hard mask layer is removed. The exposed portion of the fin is oxidized to define a diffusion break in the fin.

Abstract: The present disclosure provides a fabrication method for forming a semiconductor device, including: forming a substrate, the substrate including first fins, second fins, and a first trench located in the substrate between a first fin and an adjacent fin; forming a first mask layer on the substrate, the first fins, and the second fins; and removing portions of the first mask layer neighboring a first trench to expose a portion of a top surface of a first fin and a portion of a top surface of the adjacent second fin to form a first opening, a portion of the top surface of the first fin covered by a remaining portion of the first mask layer being a first fin device region, a portion of the top surface of the second fin covered by a remaining portion of the first mask layer being a second fin device region.

Abstract: A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

Abstract: A semiconductor device is provided that includes a deep trench defining an active region, and a fin-type pattern protruding within the active region. The fin-type pattern having a lower portion, an upper portion of a narrower width than the lower portion, and a first stepped portion formed at a boundary between the upper portion and the lower portion. The device also includes a first field insulating film surrounding the lower portion and a second field insulating film formed on the first field insulating film and partially surrounding the upper portion.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; removing part of the fin-shaped structure and part of the STI to form a first trench and removing part of the STI adjacent to the fin-shaped structure to form a second trench; and forming a dielectric layer into the first trench and the second trench to form a first single diffusion break (SDB) and a second single diffusion break.

Abstract: Semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a representative semiconductor device includes a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less, and a group III-V material over the group III material.

Abstract: A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second hard mask to remove horizontal portions of the second hard mask, and performing a second anisotropic etch on the semiconductor substrate using the first hard mask and vertical portions of the second hard mask as an etching mask to extend the recesses down. The method further includes removing the vertical portions of the second hard mask, and forming isolation regions in the recesses. The isolation regions are recessed, and a portion of the semiconductor strip between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin.

Abstract: According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second semiconductor layer, a gate line, a first source line, a second source line, a switching element, and a pixel electrode, wherein an area in which the first light shielding layer and the pixel electrode are opposed to each other and an area in which the second light shielding layer and the pixel electrode are opposed to each other are equal in size.

Abstract: An array substrate and a method for fabricating the same, and a display device are disclosed. The array substrate comprises light-transmissive regions for display and shading regions, a plurality of thin film transistors are provided in the shading region, the thin film transistor comprises: a base substrate; an active layer, a gate insulating layer, a gate and a passivation layer sequentially provided on the base substrate; and a source and a drain provided on the passivation layer, the source and the drain comprise a conductive shading layer connected to the active layer and a copper layer provided on the conductive shading layer, the conductive shading layer is provided between the active layer and the copper layer, and at least a part of region of the shading region other than the source and the drain is provided with the conductive shading layer.

Abstract: An oxide semiconductor device includes an oxide semiconductor transistor including a first gate electrode, a second gate electrode, a third gate electrode, a first oxide semiconductor channel layer, a second oxide semiconductor channel layer, and two source/drain electrodes. The second gate electrode is disposed above the first gate electrode. The third gate electrode is disposed above the second gate electrode. At least a part of the first oxide semiconductor channel layer is disposed between the first gate electrode and the second gate electrode. At least a part of the second oxide semiconductor channel layer is disposed between the second gate electrode and the third gate electrode. At least a part of each source/drain electrode is disposed between the first oxide semiconductor channel layer and the second oxide semiconductor channel layer. Each source/drain electrode contacts the first oxide semiconductor channel layer and the second oxide semiconductor channel layer.

Abstract: A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm.

Abstract: High field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a bottom-gate transistor including an oxide semiconductor layer, an oxide semiconductor layer functioning as a current path (channel) of the transistor is sandwiched between oxide semiconductor layers having lower carrier densities than the oxide semiconductor layer. In such a structure, the channel is formed away from the interface of the oxide semiconductor stacked layer with an insulating layer in contact with the oxide semiconductor stacked layer, i.e., a buried channel is formed.

Abstract: Provided is a semiconductor device including a first insulator, a second insulator, a first oxide semiconductor, a second oxide semiconductor, a first conductor, and a second conductor. The first oxide semiconductor is over the first insulator. The second oxide semiconductor is over the first oxide semiconductor. The first conductor includes a region in contact with a top surface of the second oxide semiconductor. The second insulator includes a region in contact with the top surface of the second oxide semiconductor. The second conductor is over the second oxide semiconductor with the second insulator therebetween. The second oxide semiconductor includes a first layer and a second layer. The first layer includes a region in contact with the first oxide semiconductor. The second layer includes a region in contact with the second insulator. The first layer has a lower proportion of oxygen vacancies than the second layer.

Abstract: Methods of forming high voltage (111) silicon nano-structures are described. Those methods and structures may include forming a III-V device layer on (111) surface of a silicon fin structure, forming a 2DEG inducing polarization layer on the III-V device layer, forming a source/drain material on a portion of the III-V device layer on terminal ends of the silicon fin. A middle portion of the silicon fin structure between the source and drain regions may be removed, and backfilled with a dielectric material, and then a gate dielectric and a gate material may be formed on the III-V device layer.

Abstract: Each of varicaps 50A to 50C configured to be connected in parallel is an MOS capacitor III produced under a common and single process condition. Each of the varicaps 50A to 50C has a conductor layer serving as a second electrode and formed via a capacitance insulating film on a first conductivity-type semiconductor substrate serving as a first electrode, and a second conductivity-type impurity region formed near a surface in proximity to a region of the first conductivity-type semiconductor substrate opposing the conductor layer. Each of the varicaps 50A to 50C is configured such that a capacitance value as a capacitance element between the first conductivity-type semiconductor substrate serving as the first electrode and the conductor layer serving as the second electrode is changed by applying a control voltage to the conductor layer while applying any one of a plurality of types of direct-current voltages having different voltages to the second conductivity-type impurity region.

Abstract: A multi-channel receiver optical subassembly (ROSA) such as an arrayed waveguide grating (AWG), with outputs directly optically coupled to respective photodetectors such as photodiodes. In one embodiment, the photodetectors are mounted on a photodetector mounting bar that includes a multiple conductive photodetector pads (PD pads). Each of the PD pads may be configured to receive a photodetector, and the PD pads are electrically isolated from ground such that the photodetectors are floating. The photodetector bar further includes multiple conductive transimpedance amplifier pads (TIA pads). Each of the TIA pads may be configured to receive a TIA, associated with one of the photodetectors, and to be electrically coupled to one or more ground ports of the TIA. The TIA pads are electrically connected to a common ground shared be each of said TIAs.

Abstract: To improve characteristics, reliability, and the like of a solar cell element, the solar cell element includes: a semiconductor substrate which includes a first main surface and a second main surface that is positioned opposite to the first main surface, and in which a p-type semiconductor region and an n-type semiconductor region are stacked in such a manner that the p-type semiconductor region is positioned closest to the first main surface and the n-type semiconductor region is positioned closest to the second main surface; a first passivation layer which is disposed on the p-type semiconductor region that is positioned closest to the first main surface, and which includes aluminum oxide; and a first protective layer that is disposed on the first passivation layer. The first protective layer includes an oxide that contains at least one kind of zirconium and hafnium.

Abstract: A method of manufacturing a solar cell, including providing a patterned silicon wafer having a covered area and an uncovered area, and forming at least one electrode layer in the uncovered area in a low-temperature process.

Abstract: Conductive thick-film paste is useful in forming front-side contact of a solar cell or other semiconductor devices. Unlike conventional conductive frit pastes, a conductive paste according to the present invention does not include frit particles, and contains silver particles, nano-sized inorganic additives and an organic solvent. The conductive paste according to the present invention provides better etching ability through the anti-reflecting coating on the semiconductor substrate than conventional conductive frit pastes.

Abstract: A solar cell, having a front side which faces the sun during normal operation, and a back side opposite the front side can include a silicon substrate having doped regions and a polysilicon layer disposed over the doped regions. The solar cell can include a conductive filling formed between a first metal layer and doped regions and through or at least partially through the polysilicon layer, where the conductive filling electrically couples the first metal layer and the doped region. In an embodiment, a second metal layer is formed on the first metal layer, where the first metal layer and the conductive filling electrically couple the doped regions and the second metal layer. In some embodiments, the solar cell can be a front contact solar cell or a back contact solar cell.

Abstract: Titania is a semiconductor and photocatalyst that is also chemically inert. With its bandgap of 3.0, to activate the photocatalytic property of titania requires light of about 390 nm wavelength, which is in the ultra-violet, where sunlight is very low in intensity. A method and devices are disclosed wherein stress is induced and managed in a thin film of titania in order to shift and lower the bandgap energy into the longer wavelengths that are more abundant in sunlight. Applications of this stress-induced bandgap-shifted titania photocatalytic surface include photoelectrolysis for production of hydrogen gas from water, photovoltaics for production of electricity, and photocatalysis for detoxification and disinfection.

Abstract: An aspect of present invention is to provide a temperature control system for a solar cell module, capable of controlling a solar cell module to maintain a proper temperature, the temperature control system comprises: a temperature sensor configured to measure a temperature of the solar cell module; a fluid tube having therein a path along which a temperature controlling fluid flows; a pump configured to supply a temperature controlling fluid which flows along the fluid tube; and an inverter configured to drive the pump such that the temperature controlling fluid is supplied, if the current temperature of the solar cell module is not lower than the pre-stored first pump driving reference temperature, or if the current temperature of the solar cell module is not higher than the pre-stored second pump driving reference temperature.

Abstract: An epitaxial grown avalanche photodiode (APD), the avalanche photodiode comprising an anode, a cathode, an absorber, and a doped multiplier. The absorber and the doped multiplier are about between the cathode and the anode. The doped multiplier has a multiplier dopant concentration. The doped multiplier substantially depleted during operation of the epitaxial grown photodiode. The doped multiplier may comprise of a plurality of multiplication regions, each of the multiplication regions substantially depleted during operation of the avalanche photodiode.

Abstract: Photovoltaic structures are provided with field-effect inversion/accumulation layers as emitter layers induced by work-function differences between gate conductor layers and substrates thereof. Localized contact regions are in electrical communication with the gate conductors of such structures for repelling minority carriers. Such localized contact regions may include doped crystalline or polycrystalline silicon regions between the gate conductor and silicon absorption layers. Fabrication of the structures can be conducted without alignment between metal contacts and the localized contact regions or high temperature processing.

Abstract: A method of hydrogenation of a silicon photovoltaic junction device is provided, the silicon photovoltaic junction device comprising p-type silicon semiconductor material and n-type silicon semiconductor material forming at least one p-n junction. The method comprises: i) ensuring that any silicon surface phosphorus diffused layers through which hydrogen must diffuse have peak doping concentrations of 1×1020 atoms/cm3 or less and silicon surface boron diffused layers through which hydrogen must diffuse have peak doping concentrations of 1×1019 atoms/cm3 or less; ii) Providing one or more hydrogen sources accessible by each surface of the device; and iii) Heating the device, or a local region of the device to at least 40° C.

Abstract: Provided is a photonic device in which emission intensity in a short wavelength region is suppressed even in the case of increasing carrier injection density so as to obtain a wide spectrum half-maximum width as well as a high output. The photonic device includes: a first cladding layer; a second cladding layer; and an active layer including an emitting layer and a barrier layer and being provided between the first cladding layer and the second cladding layer, the emitting layer emitting light in a spectrum having a center wavelength ?c and a spectrum half-maximum width ??, in which at least one of the first cladding layer and the second cladding layer includes a light absorbing part for absorbing light having a wavelength of ?s or less represented by the following Expression (1): ?s<(?c?(??/2))??(1).

Abstract: LED dies are partially singulated while on an unthinned depth growth substrate. Slots are made through the streets separating the LED dies, but not through the growth substrate, leaving the now separated LED dies on the growth substrate. A secondary support is attached to the LED dies on the opposite surface from the growth substrate, and the growth substrate is thinned or removed, leaving the LED dies on the secondary support. Because the LED dies are separated while on the unthinned growth substrate, the likelihood of distortion before slicing is virtually eliminated, and the width of the streets between the LED dies may be correspondingly reduced.

Abstract: An electroluminescent device comprises a structure comprising a set of nanowires on the surface of a substrate, comprising: a first series of primary so-called emission nanowires (NTie) comprising nanowires connected to first electrical contacts and capable of emitting light under the action of a forward first voltage from a forward voltage or current source; a second series of secondary detection nanowires (NTid) adjacent to the primary nanowires, connected to second electrical contacts and capable of generating a photocurrent under the action of an ambient light and/or of a portion of the light emitted by some of the primary nanowires, under the control of a second reverse voltage, from a voltage or current source; means for controlling the forward voltage as a function of the photocurrent. A method for controlling the luminance of an electroluminescent device is provided.

Abstract: A semiconductor light-emitting element includes a semiconductor stacked body that includes a light emitting layer in which n well layers (where n is, for example, an integer of 1 to 10) formed of Inx (Ga1-yAly)1-xAs (0<X?0.2, 0<y<1), and (n+1) barrier layers formed of Ga1-zAlzAs (0<z<1) and are alternately stacked with the well layer. The light emitting layer in some embodiments can emit light having a peak wavelength in a range of from 700 nm or more to 870 nm or less.

Abstract: Methods of forming III-V LED structures on silicon fin templates are described. Those methods and structures may include forming an n-doped III-V layer on a silicon (111) plane of a silicon fin, forming a quantum well layer on the n-doped III-V layer, forming a p-doped III-V layer on the quantum well layer, and then forming an ohmic contact layer on the p-doped III-V layer.

Abstract: A nitride semiconductor light-emitting device with periodic gain active layers includes an n-type semiconductor layer, a p-type semiconductor layer and a resonator. The device further includes a plurality of active layers disposed between the n-type and p-type semiconductor layers so as to correspond to a peak intensity position of light existing in the resonator and at least one interlayer disposed between the active layers. The active layer disposed at the p-type semiconductor layer side has a larger light emission intensity than the active layer disposed at the n-type semiconductor layer side.

Abstract: The present disclosure provides a light-emitting device and manufacturing method thereof. The light-emitting device comprising: a light-emitting stack; and a semiconductor layer having a first surface connecting to the light-emitting stack, a second surface opposite to the first surface, and a void; wherein the void comprises a bottom part near the first surface and an opening on the second surface, and a dimension of the bottom part is larger than the dimension of the opening.

Abstract: A light-emitting device comprises a substrate having a top surface and a plurality of patterned units protruding from the top surface; and a light-emitting stack formed on the substrate and having an active layer with a first surface substantially parallel to the top surface, wherein one of the plurality of patterned units comprises a plurality of connecting sides constituting a polygon shape in a top view of the light-emitting device, the one of the plurality of patterned units comprises a vertex and a plurality of inclined surfaces respectively extending from the plurality of connecting sides, the plurality of inclined surfaces commonly join at the vertex in a cross-sectional view of the light-emitting device, the vertex being between the top surface of the substrate and the first surface of the active layer, and six of the plurality of patterned units forms a hexagon in the top view of the light-emitting device.

Abstract: Provided is a light emitting device comprising an optical member provided on a light extracting surface side of a semiconductor light emitting element via a first light transmissive layer, wherein bonding surfaces of the semiconductor light emitting element and the first light transmissive layer are roughened surfaces, bonding surfaces of the first light transmissive layer and the optical member are flat, and the first light transmissive layer and the optical member are directly bonded.

Abstract: A light-emitting device is provided. The light-emitting device comprises a light-emitting stack comprising a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer. The light-emitting device further comprises a third semiconductor layer on the light-emitting stack and comprising a first sub-layer, a second sub-layer and a roughened surface, wherein the first sub-layer has the same composition as that of the second sub-layer, and the composition of the first sub-layer is with a different atomic ratio from that of the second sub-layer. A method for manufacturing the light-emitting device is also provided.

Abstract: A light emitting device includes a metal support structure comprising Cu; an adhesion structure on the metal support structure and comprising Au; a reflective conductive contact on the adhesion structure; a GaN-based semiconductor structure on the reflective conductive contact, the GaN-based semiconductor structure comprising a first-type GaN layer, an active layer, and a second-type GaN layer; a top interface layer on the GaN-based semiconductor structure and comprising Ti; and a contact pad on the top interface layer and comprising Au, wherein the GaN-based semiconductor structure is less than 1/20 thick of a thickness of the metal support structure.

Abstract: Embodiments provide a light emitting diode and a method of fabricating the same. The light emitting diode includes a base, a light emitting structure disposed on the base, at least one first electrode disposed on the light emitting structure; and a second electrode disposed under the light emitting structure, wherein at least a portion of the second electrode is covered by the base and the base includes a supporting insulator and at least one bulk electrode embedded in the supporting insulator and electrically connected to the light emitting structure, and a surface of the at least one bulk electrode is exposed through the supporting insulator. The light emitting diode has excellent reliability and efficiency.

Abstract: A light emitting diode is provided to include a first conductive-type semiconductor layer; a mesa including a second conductive-type semiconductor layer disposed on the first conductive-type semiconductor layer and an active layer interposed between the first and the second conductive-type semiconductor layers; and a first electrode disposed on the mesa, wherein the first conductive-type semiconductor layer includes a first contact region disposed around the mesa along an outer periphery of the first conductive-type semiconductor layer; and a second contact region at least partially surrounded by the mesa, the first electrode is electrically connected to at least a portion of the first contact region and at least a portion of the second contact region, and a linewidth of an adjoining region between the first contact region and the first electrode is greater than the linewidth of an adjoining region between the second contact region and the first electrode.

Abstract: A light emitting diode includes an n-type semiconductor layer disposed on a substrate; a p-type semiconductor layer disposed on a portion of the n-type semiconductor layer; an active layer disposed between the n-type semiconductor layer and the p-type semiconductor layer and generating light through recombination of electrons and holes; an ohmic contact layer disposed on the p-type semiconductor layer and including an indium tin oxide (ITO) layer doped with a metal, a transparent conductive layer disposed on the ohmic contact layer to a different thickness than the ohmic contact layer and including an undoped ITO layer, and a reflective layer disposed on the transparent conductive layer and including an oxide layer. Accordingly, the light emitting diode exhibits excellent current-voltage characteristics through improvement in reliability and electrical conductivity of the ohmic contact layer while improving luminous efficacy through the reflective layer formed of an oxide.

Abstract: Disclosed are a light emitting device, a method of manufacturing a light emitting device, a light emitting device package and a lighting system.

Abstract: A light-emitting device includes a semiconductor light emitting stack; an electrode on the semiconductor light emitting stack, the electrode including a mirror layer, an adhesion layer inserted between the mirror layer and the semiconductor light emitting stack, a bonding layer; and a plurality of pits between the bonding layer and the semiconductor light emitting stack, wherein one of the plurality of pits is not filled up by the adhesion layer.

Abstract: An optoelectronic semiconductor component has a volume-emitting sapphire flip-chip with an upper side and a lower side. This optoelectronic semiconductor component is embedded in an optically transparent mold body with an upper side and a lower side.

Abstract: Provided is an array substrate for mounting a chip. The array substrate includes a plurality of conductive layers unidirectionally stacked with respect to an original chip substrate; a plurality of insulating layers alternately stacked with the plurality of conductive layers, and electrically separate the plurality of conductive layers; and a cavity having a groove of a predetermined depth with respect to a region including the plurality of insulating layers in an upper surface of the original chip substrate. Accordingly, since the optical device array of a single structure is used as a line source of light, an emission angle emitted from the optical device is great, it is not necessary to form an interval for supplying an amount of light, and a display device can be simply constructed. Further, since it is not necessary to perform soldering a plurality of LED packages on a printed circuit board, a thickness of a back light unit can be reduced.