Abstract: Disclosed are methods, systems, apparatuses and computer programs for estimating a measure of the gain and offset of a converter that generates, based on digital settings, reference voltages to be used as thresholds by a comparator in a photon-counting detector in an x-ray imaging system. Steps include selecting a first converter as a reference converter and a second converter as a target converter; assigning different digital settings to the reference converter to generate at least two different reference voltages to be used as thresholds by a comparator associated with the reference converter; and obtaining, based on photon count measurements, the number of photons registered in a photon counter associated with a comparator whose reference voltage is generated by the target converter. Based on the number of photons and the at least two digital settings, an estimate of the gain and offset of the target converter relative the reference converter results.

Abstract: Systems and methods for calibrating a conducted electrical weapon (“CEW”) to provide a predetermined amount of current for each pulse of the stimulus signal. Providing the predetermined amount of current, close thereto, increases the effectiveness of the stimulus signal in impeding locomotion of a human or animal target. The calibration process enables a CEW to calibrate the amount of charge in a pulse of the stimulus signal in the environmental conditions where the tester operates and also in the field where the environmental conditions may be different from the environmental conditions during calibration.

Abstract: Circuitry and methods for measuring the voltage at a node are disclosed. A capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.

Abstract: The Rogowski coil type sensor for measuring current includes a carrier and at least one secondary winding. The winding includes: at least one internal layer with a high turn density, which layer is wound in an “outward” first winding direction from the first end to a second opposite end of the winding, and at least one external layer with a low turn density, which layer is wound in a “return” second winding direction. The external layer with a low turn density includes: a first compensating portion with a high turn density, which portion is of small length and close to the first end, a central portion with a low turn density, which portion is of large length, and a second compensating portion with a high turn density, which portion is of small length and close to the second end.

Abstract: Disclosed herein are methods, systems, and devices for identifying computational operations based on power measurements. Disclosed herein are systems that may include a phase measurement unit configured to generate a first measurement based on a power signal, the first measurement characterizing a phase angle of the power signal. The systems may also include a power measurement unit configured to generate a second measurement based on the power signal, the second measurement characterizing an amplitude of one or more aspects of the power signal. The systems may further include a processing unit configured to identify a computational operation implemented by a target processing device, the identifying of the computational operation being based on a comparison of the first measurement and the second measurement with reference measurements.

Abstract: A method determines the frequency of an alternating input signal includes storing the input signal, sampling the input signal at a first sampling frequency, a first calculation and a first angular comparison of two phasors representing the input signal at two respective instants, as a function of the input signal sampled at the first sampling frequency, estimating the frequency of the input signal, and searching for a modification of frequency of the input signal. When a modification is detected the method includes, determining a second sampling frequency, sampling the stored input signal with the second sampling frequency, a second calculation and a second angular comparison of two phasors representing the input signal, at two respective instants, as a function of the input signal sampled at the second sampling frequency and of the stored input signal sampled at the second sampling frequency, and estimating the frequency of the input signal.

Abstract: A sound processing device performs obtaining a first frequency spectrum that corresponds to a first sound signal and a second frequency spectrum that corresponds to a second sound signal, calculating a level difference between a level of each of frequency components in the first frequency spectrum and a level of each of frequency components in the second frequency spectrum, calculating a spread of a distribution of the level difference during a prescribed period for each of the frequency components, and determining a gain to be multiplied to the frequency component in the first frequency spectrum and a gain to be multiplied to the frequency component in the second frequency spectrum in accordance with the spread of the distribution of the level difference.

Abstract: An apparatus is provided which comprises: an amplifier; a first slicer coupled to the amplifier; a de-serializer coupled to an output of the first slicer; a multiplexer which is operable to select one of data or a test signal for the amplifier; a filter coupled to an input of the multiplexer to provide test signal; and a frequency modulator coupled to the filter, wherein the frequency modulator is operable to modulate frequency of the test signal. An apparatus is also provided which comprises: an analog multiplexer having a first input to receive serial data, and a second input; an analog front-end (AFE) coupled to an output of the analog multiplexer; and a filter coupled to the second input of the analog multiplexer.

Abstract: A method for measuring the impedance of a DUT having a capacitance of less than 1 pF includes applying a voltage or current signal to the DUT, the voltage or current signal including an AC component having a non-zero frequency of less than 1 kHz; monitoring a current or voltage signal, respectively, through the DUT in response to the voltage or current signal; digitizing the voltage signal and the current signal synchronously; and calculating the impedance from the digitized voltage and current signals.

Abstract: The described technology includes an apparatus comprising a proximity sensor pad and booster element located between an antenna and the proximity sensor pad, wherein voltage level of the booster element at least ten percent higher than voltage level of the proximity sensor pad. Implementations of the booster element may be made of metal or metal-ink and may have U-shape or L-shape.

Abstract: An integrated circuit with clock detection and selection function for use in a storage device includes: an embedded oscillator, a detection circuit and a selection circuit. The embedded oscillator is configured to generate an embedded clock signal. The detection circuit includes a sampling and counting circuit and a clock determination circuit. The detection circuit, and is configured to detect existence of a reference clock signal provided by a host based on sampling and counting operations that are performed according to a signal on a clock signal lane and the embedded clock signal. The selection circuit is coupled to the detection circuit and the embedded oscillator, and is configured to select one of the embedded clock signal and the signal on the clock signal lane according to the existence of the reference clock signal as an output clock signal, thereby to provide the output clock signal to the storage device.

Abstract: The invention relates to methods and apparatus for determining properties of a surface.

Abstract: A device outage detector, comprising: a microcontroller; a plurality of shunt resistors, each connected to at least one of a plurality of vehicle elements; a current sensor configured to measure a plurality of instantaneous currents passing through the plurality of shunt resistors, respectively; and a voltage sensor configured to measure a plurality of instantaneous voltages across the plurality of shunt resistors, respectively, wherein the microcontroller is configured to issue a warning for a given shunt resistor if its corresponding instantaneous current is below the first threshold value and its instantaneous voltage is zero, or if its corresponding instantaneous current is above a second threshold value.

Abstract: A machine vision system for identifying optical fibers is provided that includes a support plate supporting one or more optical fibers. The one or more optical fibers each include a jacket. A light source is configured to emit light onto the one or more optical fibers. An imager is positioned above the light source. The imager is configured to receive reflected light from the light emitted onto the one or more optical fibers. A display system is configured to receive a signal from the imager and display an augmented image.

Abstract: A quick-action leakage detection protection circuit with a regular self-checking function is provided. The quick-action leakage detection protection circuit may include a power input end, a power load end, a power user end, twin induction coils for detecting leakage current and low resistance failure, a control chip, a trip coil in which an iron core is disposed, a reset button, a self-checking chip, and a self-checking silicon controlled rectifier. The reset button may be linked with a main circuit switch, an analog path switch, and a normally-open self-checking path switch. The main circuit switch may include a pair of dynamic contact levers extended from the power load end, a first pair of static contact ends extended from the power input end passing through the twin induction coils, and a second pair of static contact ends extended from the power user end.

Abstract: A method for characterizing a segment of a transmission line, a reference signal being injected into the line and a time-domain measurement of the reflection of the reference signal in the line being carried out, the method comprises the following steps: applying a deconvoluting step to the time-domain measurement so as to generate a deconvoluted temporal sequence comprising a plurality of amplitude peaks each corresponding to an impedance discontinuity; removing, from the amplitude of at least one obtained peak, the contribution of at least one secondary reflection of the signal from an impedance discontinuity; deducing, from the temporal position of each peak, a position of an associated impedance discontinuity in the line segment; and deducing, from the amplitude of each peak, an estimate of the real part of the reflection coefficient of a wave reflected from each identified impedance discontinuity.

Abstract: Provided is a method for inspecting a heat sink that enables an accurate inspection of an insulating film formed on a surface of heat sink fins. The method including a metallic housing that includes a plurality of cooling fins arranged side by side on an outer surface thereof, and an insulating film formed on a surface of the cooling fins and between the cooling fins. The method includes disposing, in an electrolyte solution, an inspection electrode including a plurality of electrode fins insertable between the cooling fins to face the housing with a predetermined distance therebetween in such a way that the cooling fins and the electrode fins are alternately arranged; and applying a voltage between the housing and the inspection electrode, which are arranged to face each other, and inspecting a formation state of the insulating film based on a measured value of a current.

Abstract: In accordance with an embodiment, a circuit includes: a gate drive circuit; an output transistor, and a gate coupled to the gate drive circuit; a normally-on transistor including a load path coupled to the gate drive circuit and to the gate of the output transistor; and a pull-up device, where the output transistor is configured to provide a test leakage current in a test mode when a measurement voltage is applied to a current test node coupled to the gate of the output transistor and a turn-off voltage is applied to the gate of the normally-on transistor; and the gate drive circuit is configured to provide a gate drive voltage to the gate of the output transistor in a nominal operation mode when a voltage of the gate of the normally-on transistor is pulled-up to a voltage of the pull-up node via the pull-up device.

Abstract: A testing pluggable module includes a pluggable body extending between a front end and a mating end defining a mating interface with a communication connector of a receptacle assembly. The mating end is receivable in a module cavity of the receptacle assembly to mate with the communication connector. The pluggable body has an exterior forward of the mating end. The testing pluggable module includes an internal circuit board held in the pluggable body having a testing circuit operating at least one testing function. The testing pluggable module includes a user interface on the exterior of the pluggable body. The user interface has an input configured to operably control the at least one testing function of the testing circuit.

Abstract: A method of diagnosing an abnormal state of a substrate-processing apparatus includes measuring a temperature of a chuck in the substrate-processing apparatus. The temperature of the chuck is compared to a target temperature of the chuck, with a temperature-controlling unit. A control signal is analyzed to diagnose an abnormal state of the substrate-processing apparatus. The control signal is transmitted from the temperature-controlling unit to a drive parameter-applying unit configured to provide the chuck with a drive parameter.

Abstract: The system includes an integrated sequenced arrangement of parametric type instruments, automated guided prober test instruments, and a test instrument system using analog signature analysis for identifying faults in circuit card assemblies, under control of a software system with a mass interconnect system.

Abstract: A method for inspecting a laminated board, includes: performing a reflow process to solder an electronic component to a surface of a laminated board in which at least one of a plurality of wiring layers which are laminated with each other is coupled to another adjacent wiring layer via a via; and inspecting, in the reflow process, a conduction state of the via after a temperature of the laminated board reaches a melting point of a solder, and when the temperature of the laminated board is at a temperature range lower than the melting point and higher than room temperature.

Abstract: Embodiments of the present disclosure include a microcontroller with a frequency test circuit, a device-under-test (DUT) input, and a calculation engine circuit. The calculation engine circuit is configured to compare a measured frequency from the frequency test circuit measured from the DUT input to a reference frequency stored in memory, and, based on the comparison, adjust frequency of the DUT generating the DUT input.

Abstract: An example test system includes: multiple channels, where each of the multiple channels is configured to force voltage and to source current; and circuitry to combine current sourced by the multiple channels to produce a combined current for output on a single channel to a device under test (DUT), where each of the multiple channels includes a load sharing resistor to control a contribution of the channel to the combined current.

Abstract: We disclose a circuit board that hosts at least first and second types of resistance sensors. The resistance of each sensor of the first type tends to increase, and the resistance of each sensor of the second type tends to decrease if the sensor is exposed to an aggressive environment. The circuit board also hosts a control circuit that operates to monitor respective resistances of the various resistance sensors and to process the digital values representing the resistances to estimate the working condition of one or more other electrical circuits located on the circuit board and/or in relatively close proximity to the circuit board in the corresponding equipment cabinet. The control circuit further operates to transmit out an appropriate alarm message if the estimated working condition is deemed unsatisfactory.

Abstract: A chip package assembly testing system and method for testing a chip package assembly are provided herein. In one example, an IC test system is provide that includes a robot, an input queuing station, an output queuing station, and a test station. The test station includes a first and second test interfaces. The first test interface is configurable to receive and communicatively connect with a first chip package assembly having one arrangement of solder ball connections. The second test interface is configurable to receive and communicatively connect with a second chip package assembly having a different arrangement of solder ball connections. The test station also includes a first test processor configured to test the chip package assembly connected through the first interface utilizing a predetermined first test routine and a second test processor configured to test the chip package assembly connected through the second interface utilizing a predetermined second test routine.

Abstract: An electrical safety product circuit topology and its equivalent variations for sensing, control, and reporting of household AC wall current, voltage, power, and energy use, and status of its Ground-and-Arc-Fault-Interrupting internal circuit breaker, is presented herein. The architecture includes any choice of telemetry platform, presumes a plurality of its kind join a wireless network with a plurality of other products endowed with the same platform faculty. Topology variations claimed include current and differential current sensing by toroid or other transformer or by Hall semiconductor means, and include fault condition recognition by microprocessor-based algorithms, or by various analog circuit or digital signal processing (DSP) means. Embodiment variations claimed include any modular circuit breaker panel component form factor, any in-wall outlet or switch-box form factor, and any plug-in AC socket module, in-cord module, and outlet strip form factor.

Abstract: An offline vision assisted calibration system includes: a bottom side socket assembly that is mountable in an integrated circuit device handler and comprises: a socket plate that comprises a hole grid array; and a top contactor assembly that is mountable in an integrated circuit device handler and comprises: a guide plate, a plurality of fiducials located on a lower side surface of the guide plate, a contact holder plate comprising a top contactor contact array, and a plurality of adjustment actuators configured to move the contact holder plate with respect to the guide plate; and a calibration jig comprising an array of contacts on a bottom side thereof, wherein the calibration jig is configured to be placed in the socket plate such that the contacts engage with the hole grid array of the socket plate.

Abstract: An integrated circuitry includes a first logic block coupled between a first power supply terminal and a second power supply terminal. The first logic block includes a first scan chain and a configurable defect coupled to a scan output node of the first scan chain. The configurable defect has a logic node and a conductive element coupled between the logic node and the first or the second power supply terminal. The configurable defect is configured to, during a quiescent current testing mode, place a predetermined logic state on the logic node such that a current flows through the conductive element. The current can be detected by external equipment.

Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches that receives a first input signal and the second latch signal, and generates a scan data output signal depending on an input trigger signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the input trigger signal.

Abstract: An automatic instrument searching method and an automatic control system are provided. The automatic control system includes a computer, plural serial ports and at least one measuring instrument. The at least one measuring instrument is connected with computer through the plural serial ports. Firstly, the computer detects a number of the plural serial ports and arranges the serial ports. Then, the plural serial ports are inquired according to plural different communication protocols. Then, the at least one measuring instrument makes a response to a setting of the matched communication protocol. If one of the inquired serial ports receives the response, the computer judges that the serial port is connected with one measuring instrument and issues a verification command to the connected measuring instrument. If the measuring instrument complies with the verification command, the measuring instrument is addressed.

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

Abstract: A semiconductor device may be provided. The semiconductor device may include a latch comparison circuit configured for generating a latched address by latching a pattern signal inputted through an address, and generate a comparison signal by comparing a pattern signal inputted through the address and the latched address. The semiconductor device may include a failure flag generation circuit configured for generating a failure flag signal based on the comparison signal.

Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.

Abstract: A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.

Abstract: The JTAG debug apparatus includes: a TAP controller, configured to communicate with outside by using an external JTAG port, and generate, based on a signal received from the JTAG port, a debug signal including an address of the to-be-debugged unit and a debug instruction, where the debug signal is a JTAG port signal based on the JTAG protocol; a signal conversion unit, configured to receive the debug signal that is output from the TAP controller, and convert the debug signal from the JTAG port signal to a bus slave port signal that can access a slave port of the to-be-debugged unit; and a bus, configured to obtain the debug signal that is converted to the bus slave port signal and that is output from the signal conversion unit, and transmit, based on the debug signal, the debug instruction to the to-be-debugged unit indicated by the address of the to-be-debugged unit.

Abstract: This monitoring unit (1) for monitoring an electrical circuit breaker (D) includes: a central body including: an interconnection device (120) capable of receiving primary voltages (V1) from the circuit breaker, and comprising an electrical power circuit (1220) for converting the primary voltages to secondary voltages (V2); a control device (110), for measuring the secondary voltages (V2) delivered by the power circuit (1220), a removable electrical power supply module (20), comprising a power converter (203), configured to transform the collected primary voltages (V1) into an additional secondary voltage (V2?) and to supply electrical power to a shared electrical power supply bus (1102) of the control device (110).

Abstract: Provided are a high-voltage circuit breaker opening and closing time online monitoring apparatus, a smart multi-dimensional big data analyzing expert system for a high-voltage circuit breaker in a power grid, and methods therefor. The opening and closing time online monitoring apparatus includes a circuit breaker opening and closing events database, a circuit breaker opening and closing time online monitoring module, and a human machine interaction interface. Data in the circuit breaker opening and closing events database is derived from a SCADA and a measurement and control apparatus thereof, a circuit breaker phase selection opening and closing apparatus, a relay protection apparatus and a relay protection information system, and a fault recording apparatus and a fault recording system of each of a substation and a converter station. The circuit breaker opening and closing time online monitoring module includes various modules, and cloud databases for such online monitoring are created.

Abstract: A modular device is used to inspect a confined space in a machine. The entire inspection coverage area and corresponding status are mapped so that the inspection location and associated data are graphically visualized. An accelerometer mounted on the device serves as a tilt sensor and also provides data about a collision of the device with the space being inspected or defects therein. The accelerometer data in combination with an odometry system determines the axial position of the device. A gyroscope mounted on the device is used to determine the device heading. The locational information is used to generate an inspection map that provides inspection history, logged data and a reference that are useful in scheduling the next inspection. The output of the gyroscopes can be used to provide haptic feedback to the device operator to maintain proper device orientation.

Abstract: A method for determining the operating status of a spring charging motor of a LV or MV switching apparatus.

Abstract: An electrical system (2) comprises a battery (26) for storing electrical energy; a battery monitoring device (22) which is configured for determining a numerical value representing the charging state of the battery (26) by setting an initial numerical value representing the charging state of the battery (26); and repeatedly determining a current operational state of the electrical system (2) and a time period (T1-T10) for which said current operational state is active; calculating a change of the charging state of the battery (26) as a function of the determined current operational state of the electrical system (2) and the time period (T1-T10) for which said current operational state is active; and updating the numerical value representing the charging state of the battery (26) by adding or subtracting the calculated change of the charging state to/from the numerical value.

Abstract: A number of variations may include products and methods for estimating the state of an energy system. At least one sensor may monitor a voltage and a current of the energy storage system. An electronic controller may be communicatively coupled with the energy storage system and may receive input from the sensor. A circuit may be representative of the energy storage system and may be appropriately defined in the electronic controller. The circuit may estimate a state of the energy storage system from a reading of the voltage and the current.

Abstract: Methods, apparatuses, and systems for measuring impedance spectrum, power or energy density, and/or spectral density using frequency component analysis of power converter voltage and current ripple are described herein. An example method for measuring impedance spectrum, power spectrum, or spectral density can include measuring an alternating current (AC) ripple associated with a power converter, where the AC ripple includes an AC current ripple and an AC voltage ripple. The method can also include performing a frequency analysis to obtain respective frequency components of the AC current ripple and the AC voltage ripple, and calculating an impedance spectrum, a power spectrum, or a spectral density of an electrical component based on the respective frequency components of the AC current ripple and the AC voltage ripple.

Abstract: An apparatus for estimating a degree of aging of a secondary battery is configured to: determine a current and a temperature of the secondary battery; determine a state of charge from the current of the secondary battery; determine a degree of calendar aging by applying a cumulative degree-of-aging model to a degree-of-calendar-aging profile corresponding to the determined state of charge and the determined temperature while the secondary battery is in a calendar state; determine a degree of cycle aging by applying the cumulative degree-of-aging model to a degree-of-cycle-aging profile corresponding to the state of charge, the temperature, and the current of the secondary battery while the secondary battery is in a cycle state; and determine, as the degree of aging of the secondary battery, a weighted average value calculated for the determined degree of calendar aging and the determined degree of cycle aging based on calendar time and cycle time.

Abstract: Provided is a sensor circuit that has little possibility of being accidentally put into a test mode in response to an external input of noise or the like. The sensor circuit includes a clock generation circuit configured to output a control signal that is used to control intermittent operation to a physical quantity detection unit, and to output a sampling signal in a sleep period, a potential detection circuit configured to detect a potential at an output terminal and to output a detection signal, and a clock control circuit configured to output a mode switching signal that is a command to switch the clock generation circuit to a test mode, when a given signal pattern is detected in data that is obtained by sampling the detection signal based on the sampling signal.

Abstract: A gas cell includes a cell having a principal chamber having a coating material film formed on an inside wall, a reservoir arranged with the principal chamber along the longitudinal direction and communicating with to the principal chamber, a reinforcement section extending from the reservoir side of the principal chamber in an X-axis direction along the reservoir, an opening section disposed on an opposite side of the reservoir to the principal chamber, and a sealing section adapted to block the opening section, and an alkali metal gas encapsulated in the principal chamber, and the reinforcement section is provided with one of at least one hole and at least one groove.

Abstract: The present invention provides a magnetic resonance imaging method and system, the method comprising performing the following steps at least once: a composition step: performing image composition processing on raw images received by a receiving coil that is pre-determined as an artifact coil and a receiving coil that is pre-determined as a non-artifact coil to obtain a composite image; and a correction step: obtaining a product of the above composite image and space sensitivity of the above artifact coil to replace the raw image received by the above artifact coil, and performing the above composition step again.

Abstract: A magnetic resonance imaging apparatus according to an embodiment includes a static magnetic field magnet, a gradient coil, a space forming structure, a magnet supporting member, and a space forming structure supporter. The gradient coil is provided on an inner circumferential side of the static magnetic field magnet. The space forming structure forms a patient space on an inner circumferential side of the gradient coil. The magnet supporting member supports the static magnetic field magnet on a floor surface. The space forming structure supporter is attached to the magnet supporting member and supports the space forming structure.

Abstract: Methods, devices and systems for providing a high-precision and fast changing driving current for a gradient coil to generate a gradient magnetic field to acquire a high-quality image in an MRI device are provided. An example gradient amplifier includes a controller, a power amplifying circuit and a filtering circuit. The controller is configured to output pulse signals. The power amplifying circuit includes a first H bridge circuit and a second H bridge circuit and is configured to perform power conversion on an input power supply according to the pulse signals to output a driving current to a gradient coil. The filtering circuit is configured to filter the driving current output by the power amplifying circuit. A phase difference between the pulse signals output by the controller to drive switching tubes on a same position in the first H bridge circuit and the second H bridge circuit is a particular degree.

Abstract: Provided is a technique in calculating a magnetic susceptibility distribution by using an MRI, for reducing artifacts and noise and improving precision in the magnetic susceptibility distribution being calculated. According to this technique, a magnetic field distribution is obtained via a phase image from a complex image acquired through MRI. Under the constraint based on a relational expression between the magnetic field and the magnetic susceptibility, smoothing process is performed iteratively on the magnetic susceptibility distribution calculated from the magnetic field distribution. Specifically, a minimization process for minimizing through the iterative operation, an error function defined by a predetermined initial magnetic susceptibility distribution and the magnetic field distribution is performed, thereby calculating the magnetic susceptibility distribution.