Abstract: A semiconductor device includes a wiring embedded in an insulating layer, an oxide semiconductor layer over the insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate electrode provided to overlap with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. The insulating layer is formed so that part of a top surface of the wiring is exposed. The part of the top surface of the wiring is positioned higher than part of a surface of the insulating layer. The wiring in a region exposed from the insulating layer is electrically connected to the source electrode or the drain electrode. The root-mean-square roughness of a region which is part of the surface of the insulating layer and in contact with the oxide semiconductor layer is 1 nm or less.

Abstract: A semiconductor device that is suitable for miniaturization is provided. The semiconductor device has a plurality of different transistors, active layers of the plurality of transistors are each an oxide semiconductor, and in the plurality of transistors, field-effect mobility of a transistor whose channel length is maximum and field-effect mobility of a transistor whose channel length is minimum are substantially constant. Alternatively, when channel lengths ranges from 0.01 ?m to 100 ?m, a reduction in field-effect mobility of a transistor whose channel length is minimum with respect to field-effect mobility of a transistor whose channel length is maximum is less than or equal to 70%.

Abstract: The present invention belongs to the field of display technology and particularly relates to an electrode lead-out structure, an array substrate and a display device. The electrode lead-out structure comprises a substrate electrode, an isolating layer and an lead-out electrode. The isolating layer covers the substrate electrode to expose a part of region of the substrate electrode through a via formed in the isolating layer, and the lead-out electrode is in contact with the exposed region of the substrate electrode, wherein the lead-out electrode covers the wall and bottom of the via of the isolating layer and extends from an upper edge of the via of the isolating layer along an upper surface of the isolating layer to overlap with the upper layer of the isolating layer.

Abstract: Provided is a method to manufacture a liquid crystal display device in which a contact hole for the electrical connection of the pixel electrode and one of the source and drain electrode of a transistor and a contact hole for the processing of a semiconductor layer are formed simultaneously. The method contributes to the reduction of a photography step. The transistor includes an oxide semiconductor layer where a channel formation region is formed.

Abstract: An array substrate including a display area and a non-display area surrounding the display area. The non-display area includes a pad portion including one or more first pads that each have a parallelogram shape.

Abstract: A display panel is provided, which includes a first substrate, a first insulating layer on the first substrate, a semiconductor layer on the first insulating layer, and a second insulating layer on the semiconductor layer and the first insulating layer. The second insulating layer has a surface in contact with the first insulating layer. The second insulating layer has a first region. The first region has a thickness of 40 nm from the surface of the second insulating layer, and the second insulating layer has a fluoride ion gain ratio of 80% to 95% in the first region.

Abstract: A semiconductor device includes a first conductive layer, a first insulating layer over the first conductive layer, first and second oxide semiconductor layers over the first insulating layer, a second conductive layer over the first oxide semiconductor layer, a third conductive layer over the second oxide semiconductor layer, a fourth conductive layer over the first oxide semiconductor layer and the second oxide semiconductor layer, a second insulating layer over the second conductive layer, the third conductive layer, and the fourth conductive layer, a fifth conductive layer electrically connected to the first conductive layer over the second insulating layer, and a sixth conductive layer over the second insulating layer. Each of the first and fifth conductive layers includes an area overlapping with the first oxide semiconductor layer. The sixth conductive layer includes an area overlapping with the second oxide semiconductor layer.

Abstract: A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device includes a transistor over a substrate, a first light-transmitting conductive film over the substrate, an oxide insulating film covering the transistor and having an opening over the first light-transmitting conductive film, a nitride insulating film over the oxide insulating film and in contact with the first light-transmitting conductive film in the opening, a second light-transmitting conductive film connected to the transistor and having a depressed portion in the opening, and an organic resin film with which the depressed portion of the second light-transmitting conductive film is filled.

Abstract: A method of fabricating a display device including forming one or more thin-film transistors (“TFTs”) each configured to include an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate. A storage capacitor including a first storage electrode and a second storage electrode overlapping the first storage electrode with the gate insulating layer interposed there between is also formed on the substrate. A top surface of the first storage electrode may include hillocks and the gate insulating layer is formed between the first storage electrode and the second storage electrode to conform to the shape of the top surface of the first storage electrode with the hillocks.

Abstract: The present invention is directed to photodiode arrays comprising a dielectric structure containing an array of face conductive areas (pads) and. Each photodiode is fully separated from each other. Every photodiode has a face electrode formed on sensitive side of the semiconductor substrate and an individual back electrode formed on the opposite side. The number of conductive areas on the dielectric structure is equal to number of photodiodes in the array. The photodiodes of the array are installed on the conductive areas so that their back electrodes have electrical contact with the corresponding conductive area. Each conductive area contains at least one individual conductive hole penetrating the dielectric package from the face side to the opposite side of the dielectric structure. The conductive holes going to backside of the dielectric structure are connected with the back conductive areas formed on back side of dielectric package.

Abstract: An imaging device includes: a unit pixel cell comprising: a photoelectric converter generating an electric signal and comprising a first and second electrodes and a photoelectric conversion film located therebetween, the first electrode being located on a light receiving side of the photoelectric conversion film, a signal detection circuit detecting the electric signal and comprising a first transistor and a second transistor that are connected to the second electrode, the first transistor amplifying the electric signal, and a capacitor circuit comprising a first capacitor and a second capacitor having a capacitance value larger than that of the first capacitor that are serially connected to each other, the capacitor circuit being provided between the second electrode and a reference voltage; and a feedback circuit comprising the first transistor and an inverting amplifier and negatively feeding back the electric signal to the second transistor via the first transistor and the inverting amplifier.

Abstract: A CMOS image sensor may have back-side illuminated pixels and operate in a global shutter scanning mode. The CMOS image sensor may be implemented using three-layer chip stacking. The chip to chip electrical connections between the upper chip and the middle chip may be formed via hybrid bonding. Two bonding pads may be included in each pixel. The electrical connections between the middle chip and the lower chip may be formed at the periphery of the array. Using three-layer chip stacking with hybrid bonding allows for the transferring and storing of signals from the upper chip on the middle chip. A signal from low light level illumination and a charge overflow signal from high light level illumination may both be transferred to the middle chip. The image sensor may be able to use a global shutter scanning mode having high dynamic range.

Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.

Abstract: A structure includes a silicon substrate; silicon readout circuitry disposed on a first portion of a top surface of the substrate and a radiation detecting pixel disposed on a second portion of the top surface of the substrate. The pixel has a plurality of radiation detectors connected with the readout circuitry. The plurality of radiation detectors are composed of at least one visible wavelength radiation detector containing germanium and at least one infrared wavelength radiation detector containing a Group III-V semiconductor material. A method includes providing a silicon substrate; forming silicon readout circuitry on a first portion of a top surface of the substrate and forming a radiation detecting pixel, on a second portion of the top surface of the substrate, that has a plurality of radiation detectors formed to contain a visible wavelength detector composed of germanium and an infrared wavelength detector composed of a Group III-V semiconductor material.

Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together.

Abstract: An image sensor arranged inside and on top of a semi-conductor substrate having a front surface and a rear surface, the sensor including a plurality of pixels, each including: a photosensitive area, a reading area, and a storage area extending between the photosensitive area and the reading area; a vertical insulated electrode including an opening of transfer between the photosensitive area and the storage area; and at least one insulation element among the following: a) a layer of an insulating material extending under the surface of the photosensitive area and of the storage area and having its front surface in contact with the rear surface of the electrode; and b) an insulating wall extending vertically in the opening, or under the opening.

Abstract: A back-side imager includes a matrix of photosites in an active layer. An interconnect layer covers the active layer. A layer of germanium is positioned between the active layer and the interconnect layer.

Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.

Abstract: According to embodiments of the present invention, a pixel arrangement is provided. The pixel arrangement includes a plurality of pixels arranged adjacent to each other; and a substrate configured to receive the plurality of pixels, wherein each pixel of the plurality of pixels comprises a plurality of optical cells electrically coupled to each other; and an electrical interconnection electrically isolated from the plurality of optical cells, the electrical interconnection arranged to provide electrical communication between two separate conducting terminals external to the pixel.

Abstract: A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.

Abstract: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate.

Abstract: Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises an oxide grid comprising a first oxide grid portion and a second oxide grid portion. A metal grid is formed between the first oxide grid portion and the second oxide grid portion. The oxide grid and the metal grid define a filler grid. The filler grid comprises a filler grid portion, such as a color filter, that allows light to propagate through the filler grid portion to an underlying photodiode. The oxide grid and the metal grid confine or channel the light within the filler grid portion. The oxide grid and the metal grid are formed such that the filler grid provides a relatively shorter propagation path for the light, which improves light detection performance of the image sensor.

Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.

Abstract: A semiconductor device includes a substrate, light sensing devices, at least one infrared radiation sensing device, a transparent insulating layer, an infrared radiation cut layer, a color filter layer and an infrared radiation color filter layer. The light sensing devices and the at least one infrared radiation sensing device are disposed in the substrate and are adjacent to each other. The transparent insulating layer is disposed on the substrate overlying the light sensing devices and the at least one infrared radiation sensing device. The infrared radiation cut layer is disposed on the transparent insulating layer overlying the light sensing devices for filtering out infrared radiation and/or near infrared radiation. The color filter layer is disposed on the infrared radiation cut layer. The infrared radiation color filter layer is disposed on the transparent insulating layer overlying the at least one infrared radiation sensing device.

Abstract: An optoelectronic device is disclosed. The optoelectronic device includes a flexible substrate, a thin film transistor (TFT) array disposed on a first surface of the flexible substrate, a photodiode layer disposed on the TFT array, and a plurality of data lines and scan lines connected to the TFT array and disposed on the first surface of the flexible substrate. The device further includes a electronics signal module assembly disposed on a second surface of the flexible substrate opposite the TFT array, and an interconnect disposed through the flexible substrate, connecting the data lines and scan lines to the electronics signal module assembly.

Abstract: A method of fabricating an image sensor includes the following steps. A substrate is provided. A first infrared filter is formed on a first region of the substrate. A second infrared filter is deposited on the substrate and the first infrared filter. The deposited second infrared filter covers the first infrared filter. The second infrared filter is lowered to expose the first infrared filter. The lowered second infrared filter is on a second region of the substrate and neighbors the first infrared filter.

Abstract: A method of manufacturing a solid-state image sensor is provided. The method comprises: depositing a gate electrode film above the semiconductor layer; etching the gate electrode film to form a first gate electrode patterned in a pixel region, leaving the gate electrode film in a peripheral region; depositing a first insulating film above the semiconductor layer after the forming the first gate electrode; removing the first insulating film formed in the peripheral region; etching the gate electrode film left in the peripheral region to form a second gate electrode patterned in the peripheral region after the removing the first insulating film; forming a second insulating film above the semiconductor layer after the forming the second gate electrode; and forming a side wall on side surface of the second gate electrode by etching the second insulating film.

Abstract: An LED chip for use in an LED chip array forming a continuous array of LEDs. The LED chip comprises an array of LEDs on a substrate. LEDs in a row of the array are longitudinally offset from corresponding LEDs in another row. Adjacent LEDs in each row of the array are separated by a longitudinal pitch. At least part of an end face of the substrate is angled with respect to a transverse axis of the LED chip such that the LED chip is positionable adjacent another LED chip to maintain the longitudinal pitch between adjacent LEDs on different chips.

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.

Abstract: A semiconductor device according to the embodiment includes a plurality of semiconductor layers arranged along a first direction and a second direction, wherein each of the semiconductor layers includes a first semiconductor layer and second semiconductor layers positioned at both upper and lower sides of the first semiconductor layer, and a gate electrode which faces the first semiconductor layer. A row of the semiconductor layer in the first direction is oblique to a row of the semiconductor layer in the second direction. At least one part of peripheral faces of the first semiconductor layer is in contact with the gate electrode along the first direction.

Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

Abstract: A method for manufacturing a photoelectric converter includes a first step of preparing a semiconductor substrate including a metal oxide semiconductor (MOS) transistor, a second step of forming a plurality of interlayer insulating films above the semiconductor substrate, and a third step of forming a photoelectric conversion portion above the semiconductor substrate. The second step includes a step of forming a first film containing hydrogen. The third step includes a step of forming a first electrode, a step of forming a photoelectric conversion film, and a step of forming a second electrode. The method includes a step of performing heat treatment between the step of forming the first film and the step of forming the photoelectric conversion film.

Abstract: There is provided a light emitting device which enables a color display with good color balance. A triplet compound is used for a light emitting layer of an EL element that emits red color, and a singlet compound is used for a light emitting layer of an EL element that emits green color and a light emitting layer of an EL element that emits blue color. Thus, an operation voltage of the EL element emitting red color may be made the same as the EL element emitting green color and the EL element emitting blue color. Accordingly, the color display with good color balance can be realized.

Abstract: An organic light emitting display device includes a plurality of pixels defined on a substrate. Each of the plurality of pixels has a plurality of sub-pixels, and each of the plurality of sub-pixels has a light emitting area and a driving area. Widths in a first direction of the driving areas of the plurality of sub-pixels are identical to each other. A size of a light emitting area of a first sub-pixel of the plurality of sub-pixels is greater than a size of a light emitting area of a second sub-pixel of the plurality of sub-pixels.

Abstract: An organic light emitting diode display includes a substrate and a first red organic light emitting element disposed on the substrate. The first red organic light emitting element may include a first light emission region and a second light emission region, wherein the first light emission region emits a first red light having a first peak wavelength, and the second light emission region emits a second red light having a second peak wavelength different from the first peak wavelength.

Abstract: A display panel includes an EL panel section, a CF panel section, and a sealing resin layer. In the EL panel section, the surface of a sealing layer has a projected and recessed shape in a Z-axis direction as a whole, wherein a light-emitting region corresponding to a region between banks is a recessed section, and a non-light-emitting region corresponding to a top portion of the bank is a projected section. The sealing resin layer includes a first sealing resin layer and a second sealing resin layer. Prior to performing heating or light irradiation in a step of forming the first and second sealing resin layers, the viscosity of a second non-fluid resin constituting the second sealing resin layer is lower than the viscosity of a first non-fluid resin constituting the first sealing resin layer.

Abstract: A light-emitting device includes a drive transistor for controlling the quantity of current supplied to a light-emitting element, a capacitor element electrically connected to a gate electrode of the drive transistor, and an electrical continuity portion for electrically connecting the drive transistor and the light-emitting element, these elements being disposed on a substrate. The electrical continuity portion is disposed on the side opposite to the capacitor element with the drive transistor disposed therebetween.

Abstract: An integrated capacitor includes a substrate with a first main surface area and an opposing second main surface area. A capacitor structure with a dielectric layer is integrated in the first main surface area. A compensation structure with a compensation layer is integrated in the second main surface area. The ratio between a surface enlargement of the second main surface area effected by the compensation structure corresponds to at least 30% of the surface enlargement of the first main surface area effected by the capacitor structure.

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

Abstract: The present invention is notably directed to a method of fabrication of a microfluidic chip (1), comprising: providing (S10-S20) a wafer (10, 12) of semiconductor material having a diamond cubic crystal structure, exhibiting two opposite main surfaces (S1, S2), one on each side of the wafer, and having, each, a normal in the <100> or <110> direction; and performing (S30) self-limited, anisotropic wet etching steps on each of the two main surfaces on each side of the wafer, to create a via (20, 20a) extending transversely through the thickness of the wafer, at a location such that the resulting via connects an in-plane microchannel (31) on a first one (S1) of the two main surfaces to a second one (S2) of the two main surfaces, the via exhibiting slanted sidewalls (20s) as a result of the self-limited wet etching. The invention further concerns microfluidic chips accordingly obtained.

Abstract: A diode includes a second semiconductor layer over a first semiconductor layer. The diode further includes a third semiconductor layer over the second semiconductor layer, where the third semiconductor layer includes a first semiconductor element over the second semiconductor layer. The third semiconductor layer additionally includes a second semiconductor element over the second semiconductor layer, wherein the second semiconductor element surrounds the first semiconductor element. Further, the third semiconductor layer includes a third semiconductor element over the second semiconductor element. Furthermore, a hole concentration of the second semiconductor element is less than a hole concentration of the first semiconductor element.

Abstract: Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.

Abstract: A method for forming a multi-stack nanowire device includes forming a common release layer on a substrate, the common release layer comprising a common release material. The method also includes forming a first multi-layer stack on a first portion of the common release layer, the first multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material, and forming a second multi-layer stack on a second portion of the common release layer, the second multi-layer stack comprising at least two layers separated by at least one layer comprising the common release material. The method further includes patterning each of the first multi-layer stack and the second multi-layer stack into one or more fins and forming two or more multi-stack nanowires from the one or more fins by removing the common release material using a common etch process.

Abstract: A method of forming a semiconductor device and resulting device. The method may form a first gate on a gate region of a starting substrate. The starting substrate includes alternating sacrificial layers and semiconductor layers above a buffer sacrificial layer located on a bulk substrate. The method may remove the starting substrate located between the gates. Etching the starting substrate creates a trench into the bulk substrate. The method may form an insulating layer on the inside of the trench. The method may form a masking layer over in the trench in the starting substrate covering a portion of the insulating layer, but below a top surface of the buffer layer. The method may remove the unmasked portion of the insulating layer. The method may form a source/drain in the trench. The method may remove the buffer sacrificial layer, and the sacrificial layers in the layered nanosheet.

Abstract: A crystalline layer is produced from a crystalline substrate made from a first material on which a masking layer has previously been deposited; the masking layer containing at least one trench forming an access to the substrate, by: forming a crystalline buffer layer situated at least partly in the trench in the masking layer, extending from the substrate and forming a projection beyond the masking layer so that an upper part of the lateral flanks of said buffer layer is left uncovered, the formation step comprising a growth of the buffer layer from the substrate, and forming a crystalline epitaxial layer in a second material, different from the material of the buffer layer, by growth from said upper part of the lateral flanks of the buffer layer left uncovered.

Abstract: Embodiments are directed to a method of forming a feature of a semiconductor device. The method includes forming the feature from a semiconductor material having compressive strain that extends throughout a cut region of the feature and throughout a preserve region of the feature. The method further includes converting the cut region of the feature to a dielectric.

Abstract: A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

Abstract: Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.

Abstract: The present disclosure provides a TFT, an array substrate, their manufacturing method, and a display device. The method for manufacturing the TFT includes a step of forming a pattern of a semiconductor active layer on a transparent substrate through a patterning process, and the pattern of the semiconductor active layer includes a lanthanum boride pattern.

Abstract: A semiconductor device can include a channel region with a first semiconductor material for a majority carrier in the channel region during operation (on state) of the device and a metal contact. A source/drain region can include a semiconductor material alloy including a second semiconductor material and at least one heterojunction located between the metal contact and the channel region, wherein the heterojunction forms a band-edge offset for the majority carrier that is less than or equal to about 0.2 eV.