Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate. A buffer layer is formed on a surface of the substrate between the first and second semiconductor fins and a semiconducting layer is formed on the buffer layer. The buffer layer is selectively removed and replaced with a dielectric layer. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a second channel region of the first semiconductor fin. Source and drain epitaxy regions are selectively formed on surfaces of the first gate.

Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.

Abstract: The present disclosure provides a transistor structure, including a self-aligned source-drain structure surrounded by an insulating structure and a gate of a second conductive type separated from the source and the drain by the insulating structure. The self-aligned source-drain structure includes a source and a drain of a first conductive type, a channel between the source and the drain, and a polysilicon contact over and aligned with the channel. A method for manufacturing the transistor structure is also provided in the present disclosure.

Abstract: A photovoltaic module has at least one solar cell having an irradiation surface for receiving light. The photovoltaic module is configured to provide a voltage. The photovoltaic module also includes a carrier unit which is arranged laterally offset from the solar cell at least on one side. A first surface of the carrier unit is oriented flush with the irradiation surface of the solar cell within a predefined tolerance range. The photovoltaic module also includes at least one electrical conductor, which contacts a carrier contact connection on a second surface of the carrier unit opposite the first surface via a cell contact connection of an electronic component on the solar cell or the solar cell in an electrically conductive manner. The cell contact connection is arranged on a contacting side of the solar cell opposite the irradiation surface.

Abstract: A solar photovoltaic panel disposed in a matrix for use, wherein the solar photovoltaic panel comprises a plurality of antennas configured to communicate with antennas placed on adjoining solar photovoltaic panels, a receptor configured to receive a search command via the plurality of antennas, a transmitter configured to transmit a search command from the antennas excluding the antenna having received the search command in response to the received search command, and a responder configured to create a response signal including the panel ID of its own solar photovoltaic panel and transmit the response signal from the antenna having received the search command when no response signal to the search command transmitted from the transmitter is received, and when a response signal to the search command transmitted from the transmitter is received, transmit the response signal with the addition of information from the antenna having received the search command.

Abstract: A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer.

Abstract: Kesterite-based photovoltaic devices formed on flexible ceramic substrates are provided. In one aspect, a method of forming a photovoltaic device includes the steps of: forming a back contact on a flexible ceramic substrate; forming a kesterite absorber layer on a side of the back contact opposite the flexible ceramic substrate; annealing the kesterite absorber layer; forming a buffer layer on a side of the kesterite absorber layer opposite the back contact; and forming a transparent front contact on a side of the buffer layer opposite the kesterite absorber layer. A roll-to-roll-based method of forming a photovoltaic device and a photovoltaic device are also provided.

Abstract: A solar antenna array may comprise an array of randomly placed carbon nanotube antennas that may capture and convert sunlight into electrical power. Methods for constructing the solar antenna array may use a mold and self aligning processing steps to minimize cost. Designs may be optimized for capturing a broad spectrum of non-polarized light. Alternatively, the array may generate light, and when connected in to an array of independently controllable sections may operate as either a reflective or light transmitting display.

Abstract: The present invention presents a process for preparing a quantum dot array comprising at least the steps of: (a) providing a crystalline semiconductor substrate surface; (b) depositing quantum dots on the said substrate surface by a process of successive ionic layer adsorption and reaction (SILAR). The steps can be repeated to build up a quantum dot superlattice structure.

Abstract: A solar cell includes: a crystal silicon substrate of a first conductivity type including a first principal surface and a second principal surface; a first amorphous silicon film of a second conductivity type provided on a side of the first principal surface; and a second amorphous silicon film of the first conductivity type provided on a side of the second principal surface. At least one of the first amorphous silicon film and the second amorphous silicon film has a multi-layer structure comprising layers. An oxygen-rich layer is provided between any adjacent two of the amorphous silicon layers in the multi-layer structure.

Abstract: Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a doped germanium-free silicon base material. The buffer layer has a work function that falls within barrier energies of the transparent electrode and the p-type layer. An intrinsic layer and an n-type layer are formed on the p-type layer. Devices are also provided.

Abstract: Solar power conversion system. The system includes a cavity formed within an enclosure having highly specularly reflecting in the IR spectrum inside walls, the enclosure having an opening to receive solar radiation. An absorber is positioned within the cavity for receiving the solar radiation resulting in heating of the absorber structure. In a preferred embodiment, the system further contains an energy conversion and storage devices thermally-linked to the absorber by heat conduction, convection, far-field or near-field thermal radiation.

Abstract: A frameless solar module having a carrier substrate and a top layer connected thereto, between which there is a layer structure which forms a plurality of solar cells connected in series for the photovoltaic generation of power is described. The carrier substrate and/or the top layer of the frameless solar module is/are provided with mounting holes for mounting the solar module on a module bracket or for connection to at least one further solar module. The mounting holes are produced in a coating-free zone within a photovoltaically active region. Mounting arrangements having such a solar module which contain fixing elements which pass through the mounting holes are also described. Furthermore, a method for producing such a solar module in which the mounting holes are produced in the carrier substrate and/or in the top layer is also described.

Abstract: A solar cell panel is discussed. The solar cell panel includes a plurality of solar cells each including a substrate and an electrode part positioned on a surface of the substrate, an interconnector for electrically connecting at least one of the plurality of solar cells to another of the plurality of solar cells, and a conductive adhesive film including a resin and a plurality of conductive particles dispersed in the resin. The conductive adhesive film is positioned between the electrode part of the at least one of the plurality of solar cells and the interconnector to electrically connect the electrode part of the at least one of the plurality of solar cells to the interconnector. A width of the interconnector is equal to or greater than a width of the conductive adhesive film.

Abstract: A concentrated photovoltaic receiver and backplane assembly is described herein. A thermally conductive heat spreader is configured between the receiver and the backplane for dissipating at least a portion of the thermal energy in a direction including a horizontal component towards a portion of the heat spreader which is not directly in contact with a receiver portion. In some embodiments, the heat spreader is electrically conductive and is adapted for conducting current from the receiver to the backplane. In some embodiments, a surface area of a receiver substrate is less than 5 times larger than a surface area of a solar cell that is mounted onto the receiver substrate. In some embodiments, the receiver substrate comprises vias for conducting current from a top face to a bottom face of the receiver.

Abstract: A solar antenna array may comprise an emitter that may convert visible light into black body infrared radiation, and an array of antennas that may capture and convert the black body radiation into electrical power. Methods for constructing the solar antenna array may include using thermal insulation, high-gain low-e glass, and gasses with minimal heat transfer. A black body infrared antenna array may augment the electrical power from a visible light antenna array by converting its waste heat into additional electrical power.

Abstract: Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in relation to a substrate. In some cases, embodiments include a substrate including a plurality of wells each having a sidewall where a through hole via extends from a bottom of at least one of the plurality of wells; and a post enhanced diode including a post extending from a top surface of a diode structure.

Abstract: Techniques for controlling oxygen concentration levels during annealing of highly-reflective contacts for LED devices together with lamps, LED device and method embodiments thereto are disclosed.

Abstract: A semiconductor optical device has a multilayer structure 30 including a first compound semiconductor layer 31, an active layer 33, and a second compound semiconductor layer 32. A second electrode 42 is formed on the second compound semiconductor layer 32 through a contact layer 34. The contact layer 34 has a thickness of four or less atomic layers. When an interface between the contact layer 34 and the second compound semiconductor layer 32 is an xy-plane, a lattice constant along an x-axis of crystals constituting an interface layer 32A which is a part of the second compound semiconductor layer in contact with the contact layer 34 is x2, a lattice constant along a z-axis is z2, a length along an x-axis in one unit of crystals constituting the contact layer 34 is xc?, and a length along the z-axis is zc?, (zc?/xc?)>(z2/x2) is satisfied.

Abstract: An electrical contact structure (10) for a semiconductor component (100) is specified, comprising a transparent electrically conductive contact layer (1), on which a first metallic contact layer (2) is applied, a second metallic contact layer (3), which completely covers the first metallic contact layer (2), and a separating layer (4), which is arranged between the transparent electrically conductive contact layer (1) and the second metallic contact layer (3) and which separates the second metallic contact layer (3) from the transparent electrically conductive contact layer (1). Furthermore, a semiconductor component (100) comprising a contact structure (10) is specified.

Abstract: An optoelectronic semiconductor chip is disclosed. In an embodiment the chip includes a semiconductor layer sequence having a bottom face and a top face, wherein the semiconductor layer sequence comprises a first layer of a first conductivity type, an active layer for generating electromagnetic radiation, and a second layer of a second conductivity type and a bottom contact element located at the bottom face and a top contact element located at the top face for injecting current into the semiconductor layer sequence. The chip further includes a current distribution element located at the bottom face, the current distribution element distributes current along the bottom face during operation and a plurality of vias extending from the current distribution element through the first layer and through the active layer into the semiconductor layer sequence, wherein the vias are not in direct electrical contact with the active layer.

Abstract: A fluoride phosphor may include: a fluoride represented by a composition formula: AxMFy:Mnz4+, where A is at least one selected from among Li, Na, K, Rb, and Cs, M is at least one selected from among Si, Ti, Zr, Hf, Ge and Sn, a composition ratio (x) of A satisfies 2?x?3, a composition ratio (y) of F satisfies 4?y?7, and a composition ratio (z) of Mn satisfies 0<z?0.17.

Abstract: A set of light emitting devices can be formed on a substrate. A growth mask having a first aperture in a first area and a second aperture in a second area is formed on a substrate. A first nanowire and a second nanowire are formed in the first and second apertures, respectively. The first nanowire includes a first active region having a first band gap and a second active region having a second band gap. The first band gap is greater than the second band gap. The second nanowire includes an active region having the first band gap and does not include, or is adjoined to, any material having the second band gap.

Abstract: The present disclosure provides a light emitting diode (LED) package structure, a backlight module and a display device, and relates to the field of display technologies. The LED package structure includes an encapsulation housing and an LED chip encapsulated in the encapsulation housing. The encapsulation housing is a polyhedron which includes at least one inclined plane. One inclined plane of the encapsulation housing is a light exiting surface of the LED package structure.

Abstract: A method of manufacturing a light emitting device includes: arranging a first light emitting element and a second light emitting element, each having a pair of first and second electrodes disposed on a surface opposite to a main light emitting surface, on a base body adjacent to each other with the pair of electrodes facing upward; forming a pair of electrically conductive members each extending between one of the pair of electrodes of the first light emitting element and a corresponding one of the pair of electrodes of the second light emitting element; forming a light shielding member at least covering between the first and second light emitting elements; and cutting the pair of electrically conductive members and the light shielding member between the first and second light emitting elements, along a direction substantially perpendicular to the main light emitting surface of each of the first and second light emitting elements.

Abstract: A display apparatus includes a substrate, a light-emitting diode (“LED”) provided above the substrate, an insulating layer provided above the LED, and a wire grid polarizer (“WGP”) provided above the insulating layer.

Abstract: A light emitting device includes a semiconductor light emitting element; and a light reflective member having a multilayer structure and covering the side faces of the semiconductor light emitting element. The light reflective member includes: a first layer disposed on an inner, semiconductor light emitting element side, the first layer comprising a light-transmissive resin containing a light reflective substance, and a second layer disposed in contact with an outer side of the first layer, the second layer comprising a light-transmissive resin containing the light reflective substance at a lower content than that of the first layer.

Abstract: A flexible lighting element is provided, comprising: a first substrate; first and second conductive elements over the first substrate; a light-emitting element having first and second contacts that are both on a first surface of the light-emitting element, the first and second contacts being electrically connected to the first and second conductive elements, respectively, and the light-emitting element emitting light from a second surface opposite the first surface; a transparent layer located adjacent to the second surface; and a transparent affixing layer located between the first substrate and the transparent layer, wherein the transparent layer and the transparent affixing layer are both sufficiently transparent to visible light that they will not decrease light transmittance below 70%, and the first and second conductive layers are at least partially transparent to visible light, or are 300 ?m or smaller in width, or are concealed by a design feature from a viewing direction.

Abstract: A thermoelectric element includes a p-type/n-type semiconductor element having an upper end surface and a lower end surface, a lower electrode that is joined to the lower end surface of the p-type/n-type semiconductor element to connect the p-type/n-type semiconductor element and another n-type/p-type semiconductor element adjacently thereto and has an area less than that of the lower end surface in a joint region therebetween. A joint portion is made of a solder and has a surface joint part joining the lower end surface of the p-type/n-type semiconductor element and a surface of the lower electrode while the lower end surface of the p-type/n-type semiconductor element and the surface of the lower electrode are opposed to each other A fillet part is formed to fill a space produced between intersecting surfaces, i.e., the lower end surface and a lateral side of the lower electrode, and composes a step part formed by the lower end surface and the lower electrode.

Abstract: A thermoelectric conversion device includes: a thermoelectric conversion element in which a p-type thermoelectric material and an n-type thermoelectric material that are provided between an upper electrode and a lower electrode of the thermoelectric conversion element are alternately connected in series via the upper electrode and the lower electrode; an insulating layer that is provided between the upper electrode and the lower electrode and covers the p-type thermoelectric material and the n-type thermoelectric material; and an electric storage element that is provided between the upper electrode and the lower electrode and is covered by the insulating layer.

Abstract: A thermoelectric element is provided as follows. First and second semiconductor fin structures are disposed on a semiconductor substrate. Each semiconductor fin structure extends in a first direction, protruding from the semiconductor substrate. First and second semiconductor nanowires are disposed on the first and second semiconductor fin structures, respectively. The first semiconductor nanowires include first impurities. The second semiconductor nanowires include second impurities different from the first impurities. A first electrode is connected to first ends of the first and second semiconductor nanowires. A second electrode is connected to second ends of the first semiconductor nanowires. A third electrode is connected to second ends of the second semiconductor nanowires.

Abstract: A thermoelectric conversion apparatus includes a substrate, and a power generation part formed on the substrate for generating a thermoelectric power. The power generation part includes a magnetic layer with magnetization and an electrode layer including a material exhibiting a spin-orbit interaction and formed on the magnetic layer. The substrate and the power generation part have flexibility, respectively. The thermoelectric conversion apparatus further includes a cover layer having flexibility and formed on the substrate so as to cover at least the power generation part. The magnetic layer includes magnetic layer pieces separated in a layer direction with a gap portion interposed between the magnetic layer pieces.

Abstract: A sensor device, a sensor package, and method for fabricating a sensor device are described that include an integrated light blocker disposed on the thermopile device and a lens configured to direct light to the thermopile device. In an implementation, the thermopile device includes a substrate; a thermopile membrane disposed on the substrate, the thermopile membrane including at least one passivation layer; a thermopile disposed within the thermopile membrane, the thermopile including at least one thermocouple; and a light blocking layer disposed proximate to the thermopile membrane, the light blocking layer including an aperture disposed proximate to the thermopile.

Abstract: A single photo mask can be used to define the three critical layers for the piezoelectric MEMS device, specifically the top electrode layer, the piezoelectric material layer, and the bottom electrode layer. Using a single photo mask removes the misalignment source caused by using multiple photo masks. Furthermore, in certain exemplary embodiments, all electrical interconnects use underpass interconnect. This simplifies the process for defining the device electrodes and the process sequence for achieving self-alignment between the piezoelectric element and the top and bottom electrodes. This self-alignment is achieved by using an oxide hard mask to etch the critical region of the top electrode, the piezoelectric material, and the bottom electrode with one mask and different etch chemistries depending on the layer being etched.

Abstract: A resonant body high electron mobility transistor is described with resonance frequencies in gigahertz regime, limited by the cutoff frequency of the readout transistor. Piezoelectric materials form the resonating membrane of the device. Different modes of acoustic resonance, such as a thickness-mode, can be excited and amplified by applying an AC signal to the transducer electrode and proper biasing of all electrodes. The drain electrode reads out the acoustic resonance and amplifies it. The drain electrode is placed at or near where the piezoelectric charge pickup is maximum; whereas, the source electrode is placed at a nodal point with minimum displacement.

Abstract: Provided is a piezoelectric element including a substrate, electrodes, and a piezoelectric film, the piezoelectric film including an oxide including Ba, Ca, Ti, and Zr, and at least one element of Mn and Bi in which: 0.09?x?0.30 is satisfied, where x is a mole ratio of Ca to a sum of Ba and Ca; 0.025?y?0.085 is satisfied, where y is a mole ratio of Zr to a sum of Ti, Zr, and Sn; and 0?z?0.02 is satisfied, where z is a mole ratio of Sn to the sum of Ti, Zr, and Sn; a total content Save of Mn and Bi is 0.0020 moles or more and 0.0150 moles or less for 1 mole of the oxide; and a total content Sbou of Mn and Bi in a region of the piezoelectric film adjacent to one of the electrodes is smaller than Save.

Abstract: A composite substrate production method of the invention includes (a) a step of mirror polishing a substrate stack having a diameter of 4 inch or more, the substrate stack including a piezoelectric substrate and a support substrate bonded to each other, the mirror polishing being performed on the piezoelectric substrate side until the thickness of the piezoelectric substrate reaches 3 ?m or less; (b) a step of creating data of the distribution of the thickness of the mirror-polished piezoelectric substrate; and (c) a step of performing machining with an ion beam machine based on the data of the thickness distribution so as to produce a composite substrate have some special technical features.

Abstract: A mechanism is provided for fabricating a thermally assisted magnetoresistive random access memory device. A bottom thermal barrier is formed on a bottom contact. A magnetic tunnel junction is formed on the bottom thermal barrier. The magnetic tunnel junction includes a top ferromagnetic layer formed on a tunnel barrier. The tunnel barrier is formed on a bottom ferromagnetic layer. A top thermal barrier is formed on the top ferromagnetic layer. A top contact is formed on the top thermal barrier. The top contact is reduced to a first diameter. The tunnel barrier and the bottom ferromagnetic layer each have a second diameter. The first diameter of the top contact is smaller than the second diameter.

Abstract: A memory element including a layered structure including a memory layer having magnetization perpendicular to a film face in which a direction of the magnetization is changed depending on information stored therein, a magnetization-fixed layer having magnetization perpendicular to the film face, which becomes a base of the information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer.

Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction resides on a substrate and is usable in a magnetic device. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The pinned layer has a pinned layer perpendicular magnetic anisotropy energy greater than a pinned layer out-of-plane demagnetization energy. The pinned layer includes a high perpendicular magnetic anisotropy (PMA) layer including at least one nonmagnetic component, a magnetic layer and a magnetic barrier layer between the high PMA layer and the magnetic layer. The magnetic barrier layer includes Co and at least one of Ta, W and Mo. The magnetic barrier layer is for blocking diffusion of the nonmagnetic component of the high PMA layer.

Abstract: A switching device includes a first electrode and a second electrode that are disposed over a substrate, and an electrolyte layer disposed between the first electrode and the second electrode and including a porous oxide. The switching device performs threshold switching operation on the basis of oxidation-reduction reactions of metal ions that are provided from the first electrode or the second electrode to the electrolyte layer.

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed.

Abstract: A Ga—Sb—Ge family of phase change memory materials is described, including GaxSbyGez, wherein a Ga atomic concentration x is within a range from 20% to 45%, a Sb atomic concentration y is within a range from 25% to 40% and a Ge atomic concentration z is within a range from 25% to 55%, is described wherein the material has a crystallization transition temperature Tx greater than 360° C. Adding impurities including one or more element selected from silicon Si, carbon C, oxygen O and nitrogen N, can also increase the crystallization transition temperature Tx to temperatures greater than 400° C., and also reduce reset current.

Abstract: Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.

Abstract: An OLED encapsulation package, a display device and a packaging method are disclosed. The OLED encapsulation package includes a substrate, a cover board and a encapsulation unit located between the substrate and the cover board; the substrate is provided with display components thereon, and the encapsulation unit encapsulates the periphery of the display components; the encapsulation unit includes at least a moisture sensitive layer therein, and the moisture sensitive layer is capable of discoloring upon encountering with water.

Abstract: A method of forming a graphene oxide based layer includes preparing a dispersion of graphene oxide and nanostructures, and spin coating the dispersion on a surface of a substrate to form a spin coated film thereon; and thermally annealing the spin coated film to form the graphene oxide based layer, where the mass ratio of the graphene oxide and the nanostructures in the graphene oxide based layer is in a range of about 1:0.01 w/w to 1:0.8 w/w. The nanostructures are functionalized with carboxylic acid. The nanostructures include carbon nanotubes, or nanofibers. The carbon nanotubes include single walled carbon nanotubes (SWCNTs) or multi-walled carbon nanotubes (MWCNTs).

Abstract: This invention relates to a compound for an organic electroluminescent device and to an organic electroluminescent device including the same. This compound for an organic electroluminescent device including the same is improved in thermal stability and light emission efficiency. When this compound is used as a hole transport layer material, a triplet energy of a phosphorescent light emitting material is increased, thus improving the efficiency of the organic electroluminescent device.

Abstract: Disclosed is an organic electric element comprising a first electrode, a second electrode, and an organic material layer between the first electrode and the second electrode, wherein the organic material layer comprises the compound of Formula 1 and Formula 2 to improve driving voltage, luminous efficiency, color purity, and life span.

Abstract: Provided are an organic light emitting device including: a substrate; a first electrode; a second electrode; and an organic layer interposed between the first electrode and the second electrode and including an emission layer, wherein one of the first electrode and the second electrode is a reflective electrode and the other is a semitransparent or transparent electrode, and wherein the organic layer includes a layer having at least one of the compounds having at least one carbazole group, and a flat panel display device including the organic light emitting device. The organic light emitting device has low driving voltage, excellent current density, high brightness, excellent color purity, high efficiency, and long lifetime.

Abstract: A light-emitting element is provided, in which n (n is a natural number of two or more) EL layers are provided between an anode and a cathode. Between the m-th (m is a natural number, 1?m?n?1) EL layer and the (m+1)-th EL layer, a first layer containing any of an alkali metal, an alkaline earth metal, a rare earth metal, an alkali metal compound, an alkaline earth metal compound, and a rare earth metal compound, a second layer containing a substance having high electron-transport properties in contact with the first layer, and a charge-generation layer containing a substance having high hole-transport properties and an acceptor substance in contact with the second layer are provided in this order over the anode. The charge-generation layer does not have a peak of an absorption spectrum in a visible light region.