Abstract: A sound processing circuit comprises a first input for receiving a first input signal, and a second input for receiving a second input signal. A first adaptive filter receives the first input signal, and an error calculation block calculates an error between the second input signal and the output of the first adaptive filter, and outputting an error signal. A second adaptive filter receives the error signal, and an output calculation block subtracts an output of the second adaptive filter from the first input signal to generate an output signal. The adaptation of first and second adaptive filters is controlled based on a magnitude coherence between the first and second input signals.

Abstract: Method for user micro context recognition using sound signatures. The method includes: recording an environment sound sample from a microphone into a mobile device by a trigger stimulus; simultaneous to recording an environment sound sample, collecting hardware and software macro context data from available mobile devices; extracting a sound signature from the recorded sound sample based on sound features and spectrograms; comparing for similar patterns the recorded sound signature with reference sound signatures stored in a sound database; updating the sound database; checking if the recorded sound was recognized; performing a logical association between the sound label and the available macro context data; comparing for similar patterns the recorded context with a reference context stored in a context database; updating the context database; checking if the micro context was recognized; and returning to a mobile context-aware application the micro context label.

Abstract: The various implementations described enable voice activity detection and/or pitch estimation for speech signal processing in, for example and without limitation, hearing aids, speech recognition and interpretation software, telephony, and various applications for smartphones and/or wearable devices. In particular, some implementations include systems, methods and/or devices operable to detect voice activity in an audible signal by determining a voice activity indicator value that is a normalized function of signal amplitudes associated with at least two sets of spectral locations associated with a candidate pitch. In some implementations, voice activity is considered detected when the voice activity indicator value breaches a threshold value. Additionally and/or alternatively, in some implementations, analysis of the audible signal provides a pitch estimate of detectable voice activity.

Abstract: An automatic speech recognition system and a method performed by an automatic speech recognition system are provided. The method includes performing at least two passes of speech activity detection on an acoustic utterance uttered by a speaker. The at least two passes include an initial pass and a subsequent pass. The method further includes estimating at least one of feature statistics and transforms for acoustic feature extraction and acoustic modeling based on an output of an initial pass. The method further includes performing automatic speech recognition using an output of the subsequent pass while bypassing an output of the initial pass to recognize the acoustic utterance.

Abstract: A user wearing headphones (e.g., to listen to music, to engage in a voice call, etc.) may speak while receiving an audio signal through the headphones, which may cause the user to produce Lombard speech. Because the Lombard effect is generally involuntary, the user may be unaware that he or she is producing Lombard speech. The Lombard speech may inconvenience proximate individuals and/or embarrass the user (e.g., in an office, in an airport, etc.). An apparatus may be configured to receive, through a microphone communicatively coupled to the apparatus, an audio signal. The apparatus may be configured to determine whether the audio signal indicates speech by a user. The apparatus may be further configured to alert the user based on the determination that the audio signal indicates Lombard speech by the user.

Abstract: Three systems for the destruction of the data storage portion of electronic media storage devices such as hard disk drives, solid state drives and hybrid hard drives. One system utilizes a mill cutter with which the hard drive has relative motion in the direction of the axis of the mill cutter to destroy the data storage portion. A second system utilizes a laser to physically destroy the data storage portion. The third system utilizes a chemical solvent to chemically destroy the data storage portion.

Abstract: A magnetoresistive device that can include a magnetoresistive stack and an etch-stop layer (ESL) disposed on the magnetoresistive stack. A method of manufacturing the magnetoresistive device can include: depositing the magnetoresistive stack, the ESL and a mask layer on a substrate; performing a first etching process to etch a portion of the mask layer to expose a portion of the ESL; and performing a second etching process to etch the exposed portion of the ESL. The second etching process can also etch a portion of the magnetoresistive stack. The first and second etching processes can be different. For example, the first etching process can be a reactive etching process and the second etching process can be a non-reactive etching process.

Abstract: A method for correcting a mounting position of a disk device on a rack, includes performing a normal seek to position a head of the disk device above a target position on the disk, determining that the normal seek has failed, and performing an excitation seek that causes a position of a base supporting the disk to move and reposition the disk. The disk device includes a carriage arm supporting the head, a voice coil motor configured to drive the carriage arm to position the head, the base supporting the magnetic disk, the voice coil motor, and the carriage arm, and a control unit configured to control a current to the voice coil motor to be supplied with a first current profile during the normal seek and with a second current profile during the excitation seek.

Abstract: Some embodiments of the present invention logically eliminate an end region of a user-data area of a magnetic storage tape during formatting (or re-formatting) of the tape, if the position error signal (PES) variance corresponding to the end region exceeds a threshold. An adjacent region, having a PES variance less than the threshold is designated as a new end region, thereby shortening the user-data area of the tape and extending its usable life.

Abstract: An apparatus comprises a slider having an air bearing surface (ABS) and a near-field transducer (NFT) at or near the ABS. An optical waveguide is configured to couple light from a laser source to the NFT. A resistive sensor comprises an ABS section situated at or proximate the ABS and a distal section extending away from the ABS to a location at least lateral of or behind the NFT. The resistive sensor is configured to detect changes in output optical power of the laser source and contact between the slider and a magnetic recording medium.

Abstract: The magnetic tape comprises a nonmagnetic layer comprising nonmagnetic powder and binder on a nonmagnetic support, and comprises a magnetic layer comprising ferromagnetic powder and binder on the nonmagnetic layer, wherein a fatty acid ester, a fatty acid amide, and a fatty acid are contained in either one or both of the magnetic layer and the nonmagnetic layer, with the magnetic layer and nonmagnetic layer each comprising at least one selected from the group consisting of a fatty acid ester, a fatty acid amide, and a fatty acid, a quantity of fatty acid ester per unit area of the magnetic layer in extraction components extracted from a surface of the magnetic layer with n-hexane falls within a range of 1.00 mg/m2 to 10.

Abstract: A method for manufacturing a magnetic recording medium is provided. An orientation control layer is deposited on a non-magnetic substrate to control an orientation of a layer located directly thereon, and a perpendicular magnetic layer whose easy axis of magnetization is mainly oriented perpendicular to the non-magnetic substrate is deposited thereon. In depositing the orientation control layer, a first granular structure layer containing Ru or a material mainly made of Ru and a first oxide having a melting point of 1000 degrees C. or lower are deposited by sputtering. In depositing the perpendicular magnetic layer, a second granular structure layer containing magnetic particles and a second oxide having a melting point of 1000 degrees C. or lower are deposited by sputtering, and the magnetic particles are grown so as to form a columnar crystal continuing in a thickness direction. The columnar crystal includes crystal grains constituting the orientation control layer.

Abstract: An optical disc drive includes a spindle motor, a first control module and a second control module. The spindle motor includes a turn table for supporting and rotating an optical disc. The first control module includes a first optical pickup head corresponding to a first data layer of the optical disc. The first control module is connected with a host through a first bus to execute a first control command. The second control module includes a second optical pickup head corresponding to a second data layer of the optical disc. The second control module is connected with the host through a second bus to execute a second control command. The first control module and the second control module communicate with each other according to a negotiation signal. Moreover, the spindle motor is operated at a target rotation speed under control of the first control module.

Abstract: User inputs are received from one or more of a plurality of sources at an input interpreter agent. The plurality of sources comprises a remote control device and an on-screen keyboard application. The received user inputs are provided to a digital video object player application, wherein the input interpreter agent is separate from the digital video object player application.

Abstract: A magnetic disk device includes a magnetic disk having a plurality of tracks, a magnetic head used for writing data on the magnetic disk and reading data from the magnetic disk, a controller configured to control seek operations of the magnetic head, and a vibration sensor. The controller predicts a first vibration caused by a currently executed seek operation, based on a seek control signal, predicts a second vibration based on vibration detected by the sensor, and determines an adjusted start time of the currently executed seek operation so that a phase of the first vibration does not match a phase of the second vibration.

Abstract: A signal conversion device includes a first converting section configured to convert a clock signal input through a first signal line, a data signal input through a second signal line, and a control signal input through a third signal line, into pulse signals including a first pulse train and a second pulse train; and a transmitting section configured to transmit the first pulse train through a fourth signal line and the second pulse train through a fifth signal line, wherein the control signal is a signal that, through a level transition, causes a control target device to switch between an active state and an inactive state, and wherein the first converting section is configured to put successive pulses into at least one of the first pulse train and the second pulse train in response to the level transition of the control signal.

Abstract: Operations include compensating for a Tracking Error Signal (TES) offset in an optical tape drive. The tracking error offset compensation system detects a control signal for controlling movement of an optical head across a surface of a tape. The tracking error offset compensation system computes an estimated movement of the optical head, based on the initial control signal. The tracking error offset compensation system determines an estimated TES offset, based on the estimated movement of the optical head. The tracking error offset compensation system uses the estimated TES offset to correct a TES. The tracking error offset compensation system transmits the corrected TES, for controlling additional movement of the optical head.

Abstract: An inspection method for a recordable optical disc includes focusing laser light on a recording layer and obtaining a data signal dependent on the laser light reflected by the recording layer. The inspection method also includes determining whether the optical disc includes a defect or not by identifying a first period every second period in the obtained data signal obtained, the first period being a period in which a signal level of the data signal is lower than a predetermined value, and each of the second periods corresponding to an ECC block, and outputting a result of the determination.

Abstract: Methods and systems for receiving information descriptive of a pace at which a user is exercising; presenting video content depicting a race at a playback speed dependent on the pace; and displaying a dashboard including an indication of the pace.

Abstract: A video playback method and a video playback apparatus are provided. The object path extraction module of the video playback apparatus extracts at least one object path from an original video. The video synthesizing module of the video playback apparatus selectively adjusts said object path, so as to synthesize the object path into the synthesis video. The video synthesizing module determines the time length of the synthesis video based on the playback time length set by user, wherein the time length of the synthesis video less than the time length of the original video.

Abstract: A reproduction control apparatus comprises an instruction unit configured to give an instruction so as to move a reproduction position of time series data; and a control unit configured to perform, when there is an instruction from the instruction unit to move the reproduction position forward, control to move a current reproduction position forward by a first period in a case where a remaining time from the current reproduction position to a terminal end is longer than a total period of the first period and a second period, and to move the current reproduction position to a position that is the second period before the terminal end in a case where the remaining time is less than or equal to the total period and longer than the second period.

Abstract: In accordance with example embodiments, the method and system for 360-degree video post-production generally makes use of points of view (POVs) to facilitate the 360-degree video post-production process. A POV is a rectilinear subset view of a 360-degree composition based on a particular focal length, angle of view, and orientation for each frame of the 360-degree composition. Video post-production editing can be applied to a POV by the user, using rectilinear video post-production methods or systems. The rectilinear video post-production editing done on the POV is integrated back into the 360-degree environment of the 360-degree composition. In accordance with example embodiments, the method and system for 360-degree video post-production comprises identifying a point of view in a 360-degree composition; applying video post-production editing to the point of view; and aligning a new layer containing the video post-production editing with the point of view in the 360-degree composition.

Abstract: A method and a receiver device configured to mark a media content sequence comprising a succession of media frames. A decoder included in the receiver device selects at least two decoded consecutive media frames from the media content sequence according to a predefined information code previously stored in a configuration setting memory of the receiver device. A marking module associated to the decoder inserts a transition effect between the at least two selected decoded consecutive media frames including a preceding media frame and at least one immediately following media frame. The transition effect is retrieved from a library of transition effects stored in a memory associated to the marking module and applied on the basis of the preceding media frame and the at least one immediately following media frame.

Abstract: A computer-implemented method can include displaying, within a user interface in a digital media system, a media pane, and a project pane, displaying, within the media pane, a thumbnail group representing a media item, the thumbnail group comprising one or more thumbnails, a thumbnail comprising a plurality of frames, enabling a user to select, from the thumbnail group, a frame of the media item, and upon detecting that the user has selected a frame, creating a group of frames, the group of frames including the selected frame and one or more adjacent frames.

Abstract: An exemplary system includes a content processing subsystem configured to record at least a subset of a media content program and detect a defective portion of the recorded media content program that failed to be properly recorded. The content processing subsystem is further configured to provide a recording status indicator to an output device for presentation to a user, the recording status indicator identifying the defective portion of the recorded media content program. In certain implementations, the content processing subsystem is further configured to heal at least a subset of the defective portion of the recorded media content program and provide a healing status indicator to the output device for presentation to the user, the healing status indicator identifying the healed portion of the recorded media content program.

Abstract: A hard disk drive (HDD) tray adapted to carry a HDD includes a base and a cover pivoted to the base. The base includes a bottom plate and two base lateral plates connected to the bottom plate. The cover includes a top plate and two cover lateral plates connected to the top plate. One of each of the cover lateral plates and the corresponding base lateral plate includes a first fixing member which is retractable, and the other includes a fixing hole corresponding to the first fixing member. The HDD is located between the base and the cover. When the cover covers the base, the first fixing members extend into the corresponding fixing holes to fix the relative location of the cover and the base. When the cover is pivoted upward relative to the base, each first fixing member is drawn back along an inner wall of the fixing hole to exit the corresponding fixing hole. A HDD rack assembly is also provided.

Abstract: The present invention discloses an offset-printing method for a three-dimensional printed memory. The mask-patterns for different memory levels are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different memory levels.

Abstract: A memory array includes a first column of memory cells, a second column of memory cells and a set of switching elements. The first column of memory cells includes a first bit line, a first word line and a second bit line. The second column of memory cells includes the second bit line, a second word line and a third bit line. The first and second column of memory cells are configured to share the second bit line. The first and second bit lines are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane. An amount of bit line switching elements in the set of bit line switching elements is equal to N*2, where N is an amount of columns of memory cells in the memory array.

Abstract: A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Abstract: A memory system includes a memory controller with multiple command/address ports and a memory device having corresponding request ports. The memory controller issues commands to memory device to cause the memory device to “loop-back” signals conveyed to memory device over one of the command/address ports via a bidirectional data link; these signals can be deterministic test patterns. The memory controller compares the returned information with the originally transmitted patterns to perform calibration. In one embodiment, because the return links are already calibrated, errors can be attributed to issues in the forward links; the memory controller then adjusts timing of the forward links to minimize the errors.

Abstract: The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.

Abstract: A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

Abstract: An output timing control circuit of a semiconductor apparatus may include a strobe signal generation path configured to control a latency and a delay time of an internal signal, and generate a strobe signal. The output timing control circuit may include a first detection block configured to detect a phase difference of the strobe signal and a clock signal, and control the delay time according to the detected phase difference. The output timing control circuit may include a second detection block configured to detect a latency difference of the strobe signal and the internal signal, and control the latency according to the detected latency difference. The internal signal may be generated according to a preset timing of a command received by the strobe signal generation path.

Abstract: An operating method of a memory device includes entering into a command bus training mode, generating a plurality of internal clock signals by dividing a received clock signal, generating a plurality of internal chip selection signals by latching a received chip selection signal according to the plurality of internal clock signals, generating a second command/address signal by encoding a received first command/address signal based on the plurality of internal chip selection signals, and outputting the second command/address signal.

Abstract: A memory system has a non-volatile memory of which access speed is electrically controlled, a control circuitry that selects a first region which is a portion of a memory region of the non-volatile memory, and a boost circuit that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region.

Abstract: A memory device includes a semiconductor layer with an in-plane polarization component switchable between a first direction and a second direction. A writing electrode is employed to apply a writing voltage to the semiconductor layer to change the in-plane polarization component between the first direction and the second direction. A reading electrode is employed to apply a reading voltage to the semiconductor layer to measure a tunneling current substantially perpendicular to the polarization direction of the in-plane polarization component. The directions of the reading voltage and the writing voltage are substantially perpendicular to each other. Therefore, the reading process is non-destructive. Thin films (e.g., one unit cell thick) of ferroelectric material can be used in the memory device to increase the miniaturization of the device.

Abstract: Apparatuses and methods of for refresh control of a semiconductor device are described. An example apparatus includes a command control circuit that provides a plurality of pulses on a first control signal in series responsive to a plurality of refresh commands issued in series; a signal generation circuit that produces a plurality of pulses on a second control signal in sequence; and a refresh control circuit that receives two or more of the plurality of pulses on the first control signal during a period of time between one pulse and a succeeding pulse of the plurality of pulses on the second control signal, disables refresh operations responsive to at least one of the two or more of the plurality of first control signal and executes a refresh operation responsive to remaining one or more pulses of the two or more of the plurality of pulses on the first control signal.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command/address signal. The second semiconductor device extracts an active signal, a pre-charge signal, and addresses from the command/address signal, performs an active operation on a memory cell corresponding to the addresses, and performs a refresh operation on the memory cell corresponding to counting signals generated by counting a number of pulses in a refresh signal.

Abstract: Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in the active mode; a second power source line which accepts the supply of power in the active mode and the standby mode; a memory circuit to be coupled with the first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line.

Abstract: Write assist circuitry is disclosed to assist a memory device in changing logical states during a write operation. The write assist circuit includes write assist circuits which can be coupled to a shared boost capacitor to provide write assistance to the memory device. The write assist circuit includes boost switch circuit to selectively couple one or more of the write assist circuits and the shared boost capacitor. The one or more write assist circuits, when coupled to the shared capacitor, provide negative bitline assistance by selectively driving one of its corresponding bitlines pairs to be negative during a write operation.

Abstract: A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.

Abstract: A method to program a programmable resistance memory cell includes performing one or more iterations until a verifying passes. The iterations include a) applying a programming pulse to the memory cell, and, b) after applying the programming pulse, verifying if the resistance of the memory cell is in a target resistance range. After an iteration of the one or more iterations in which the verifying passes, c) a stabilizing pulse with a polarity the same as the programming pulse is applied to the memory cell. After applying the stabilizing pulse, a second verifying determines if the resistance of the programmable element is in the target resistance range. Iterations comprising steps a), b), c), and d) are performed until the second verifying passes. Methods and apparatus are described to program a plurality of such cells, including applying a stabilizing pulse of the same polarity after programming.

Abstract: A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.

Abstract: A method for writing data into a reprogrammable non-volatile memory, wherein a marking pattern including several bits is added at the beginning of the data and the set formed of the marking pattern and of the data is written from an address in the memory varying from one write operation to another, the marking pattern being identical for each write operation.

Abstract: A method includes determining, internal to a memory device, a number of program pulses required to program a sample of memory cells of the memory device during a first programming operation, comparing the determined number of program pulses required to program the sample of memory cells of the memory device to a target number of program pulses, and adjusting a program starting voltage level of one or more program pulses applied to one or more memory cells of the sample of memory cells during a second programming operation subsequent to the first programming operation when the determined number of program pulses required to program the sample of memory cells in the first programming operation is different than the target number so that the number of program pulses applied during the second programming operation tends toward the target number.

Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.

Abstract: A method of operating a non-volatile memory device includes selecting a first select transistor from among a plurality of select transistors included in a NAND string, and performing a check operation on a first threshold voltage of the first select transistor. The check operation includes comparing the first threshold voltage with a first lower-limit reference voltage level, and performing a program operation on the first select transistor when the first threshold voltage is lower than the first lower-limit reference voltage level. When the first threshold voltage is equal to or higher than the first lower-limit reference voltage level, the check operation on the first threshold voltage is ended.