Abstract: A method, which forms an air-bubble-free thin film with a high-viscosity fluid resin, initially dispenses the fluid resin on an outer region of a semiconductor wafer while the semiconductor wafer is spinning, and then dispenses the fluid resin onto the center of the semiconductor wafer after the semiconductor wafer has stopped spinning.

Abstract: Methods and apparatus for processing a substrate are described herein. A vacuum multi-chamber deposition tool can include a degas chamber with both a heating mechanism and a variable frequency microwave source. The methods described herein use variable frequency microwave radiation to increased quality and speed of the degas process without damaging the various components.

Abstract: Atomic Layer Deposition (ALD) is used for heteroepitaxial film growth at reaction temperatures ranging from 80-400° C. The substrate and film materials are preferably matched to take advantage of Domain Matched Epitaxy (DME). A laser annealing system is used to thermally anneal deposition layer after deposition by ALD. In preferred embodiments, a silicon substrate is overlaid with an AlN nucleation layer and laser annealed. Thereafter a GaN device layer is applied over the AlN layer by an ALD process and then laser annealed. In a further example embodiment, a transition layer is applied between the GaN device layer and the AlN nucleation layer. The transition layer comprises one or more different transition material layers each comprising a AlxGa1-xN compound wherein the composition of the transition layer is continuously varied from AlN to GaN.

Abstract: A method for forming a compound on a substrate is provided. The method includes depositing a composition onto a surface of a substrate; illuminating the composition and the substrate with pulsed energy; melting the substrate and decomposing the composition simultaneously; and forming a compound on the substrate. A first component of the compound is derived from the substrate and a second component of the compound is derived from the composition.

Abstract: Methods of forming microelectronic structure are provided. The methods comprise the formation of T-shaped structures using a controlled undercutting process, and the deposition of a selectively etchable composition into the undercut areas of the T-shaped structures. The T-shaped structures are subsequently removed to yield extremely small undercut-formed features that conform to the width and optionally the height of the undercut areas of the T-shaped structures. These methods can be combined with other conventional patterning methods to create structures having extremely small feature sizes regardless of the wavelength of light used for patterning.

Abstract: A method of forming a pattern includes forming a first level pattern layer on a feature layer on a substrate. The first level pattern layer includes a plurality of first line patterns and a plurality of first space burying patterns. The first line patterns extend parallel to one another in a first direction and the first space burying patterns extend parallel to one another in the first direction with first line patterns alternately disposed with first space burying patterns A portion of the plurality of first space burying patterns may be removed to form a second direction pattern space extending intermittently or continuously in the first level pattern layer. A second burying layer filling the second direction pattern space may be formed to form a network structure pattern. The feature layer may be etched with the network structure pattern as an etch mask to form a pattern of holes.

Abstract: In producing a MOS silicon carbide semiconductor device, after a first heat treatment (oxynitride) is performed in an oxidation atmosphere including nitrous oxide or nitric oxide, a second heat treatment including hydrogen is performed, whereby in the front surface of a SiC epitaxial substrate, a gate insulating film is formed. A gate electrode is formed and after an interlayer insulating film is formed, a third heat treatment is performed to bake the interlayer insulating film. After contact metal formation, a fourth heat treatment is performed to form a reactive layer of contact metal and the silicon carbide semiconductor. The third and fourth heat treatments are performed in an inert gas atmosphere of nitrogen, helium, argon, etc., and a manufacturing method of a silicon carbide semiconductor device is provided achieving a normally OFF characteristic and lowered interface state density.

Abstract: A deposition apparatus including a crucible to receive the deposition material and in which a deposition material is evaporated; a linear deposition source having a sprayer to spray the evaporated deposition material; a first connection portion and a second connection portion spaced apart from each other by a predetermined interval, the first connection portion and the second connection portion connecting the linear deposition source to the crucible at an upper surface of the crucible; and a heater in the crucible to apply heat to the deposition material, wherein the upper surface of the crucible has a first convex portion and a second convex portion successively formed between the first connection portion and the second connection portion.

Abstract: Ion implantation processes and systems are described, in which carbon dopant source materials are utilized to effect carbon doping. Various gas mixtures are described, including a carbon dopant source material, as well as co-flow combinations of gases for such carbon doping. Provision of in situ cleaning agents in the carbon dopant source material is described, as well as specific combinations of carbon dopant source gases, hydride gases, fluoride gases, noble gases, oxide gases and other gases.

Abstract: A process of forming a semiconductor device using plasma processes is disclosed. The semiconductor device includes a device area, a scribed area, and a peripheral area on a wafer, where these areas have respective conductive regions. The process includes steps of (a) implanting ions to isolate the conductive regions in the device area from the conductive region in the scribed area; (b) forming a metal film so as to cover a back surface, a side, and the peripheral area in the top surface of the wafer; (c) deposing insulating film on a whole surface of the wafer; and (d) selectively etching, by the plasma process, the insulating film so as to expose the conductive regions in the device area and the scribed area. During the plasma process, the metal film in the back surface of the wafer is connected the apparatus ground that effectively dissipates charges induced by the plasm to the apparatus ground through the metal film.

Abstract: A method for forming a semiconductor device includes implanting doping ions into a semiconductor substrate. A deviation between a main direction of a doping ion beam implanting the doping ions and a main crystal direction of the semiconductor substrate is less than ±0.5° during the implanting of the doping ions into the semiconductor substrate. The method further includes controlling a temperature of the semiconductor substrate during the implantation of the doping ions so that the temperature of the semiconductor substrate is within a target temperature range for more than 70% of an implant process time used for implanting the doping ions. The target temperature range reaches from a lower target temperature limit to an upper target temperature limit. The lower target temperature limit is equal to a target temperature minus 30° C., and the target temperature is higher than 80° C.

Abstract: In a 3D NAND device, the charge trap region of a memory cell is formed as a separate charge-trap “island.” As a result, the charge-trap region of one memory cell is electrically isolated from charge-trap regions in adjacent memory cells. The charge trap region of one memory cell is separated from the charge trap regions of adjacent memory cells by a dielectric structure, such as a silicon oxide film. Alternatively, the charge trap region of a memory cell is separated from the charge trap regions of adjacent memory cells by an air, gas, or vacuum gap.

Abstract: A method of manufacturing a semiconductor device includes forming insulation layers and sacrificial layers that are alternately and repeatedly stacked on top of each other a substrate, forming a vertical hole that penetrates the insulation layers and the sacrificial layers, and forming a vertical channel structure in the vertical hole. The forming the vertical channel structure includes forming a blocking insulation layer, a charge storage layer, a tunnel insulation layer, and a semiconductor pattern. The forming the blocking insulation layer includes forming a first oxidation target layer, oxidizing the first oxidation target layer to form a first sub-blocking layer, and forming a second sub-blocking layer. The first sub-blocking layer is formed between the second sub-blocking layer and an inner sidewall of the vertical hole.

Abstract: A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench (14) formed on a substrate (1); the trench (14) comprises a bottom surface and two side surfaces extending from the bottom surface; the trench (14) is formed on the substrate (1) with a preset angle of non-90° formed between the longitudinal direction (L) thereof and the longitudinal direction (X) of a wafer scribing trench. The test pattern can extend the scanning length of a step scanning equipment without changing the width of the trench.

Abstract: A surface machining method for a single crystal SiC substrate, including: a step of mounting a grinding plate which includes a soft pad and a hard pad sequentially attached onto a base metal having a flat surface, a step of generating an oxidation product by using the grinding plate, and a step of grinding the surface while removing the oxidation product, wherein abrasive grains made of at least one metallic oxide that is softer than single crystal SiC and has a bandgap are fixed to the surface of the hard pad.

Abstract: In one implementation, a method of removing a metal-containing layer is provided. The method comprises generating a plasma from a fluorine-containing gas. The plasma comprises fluorine radicals and fluorine ions. The fluorine ions are removed from the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions. A substrate comprising a metal-containing layer is exposed to the reactive gas. The reactive gas dopes at least a portion of the metal-containing layer to form a metal-containing layer doped with fluorine radicals. The metal-containing layer doped with fluorine radicals is exposed to a nitrogen and hydrogen containing gas mixture and the reactive gas to remove at least a portion of the metal-containing layer doped with fluorine radicals.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: The present invention relates to an activation composition for activation of silicon substrates, which is an aqueous solution comprising a source of palladium ions, a source of fluoride ions and at least two aromatic acids. The present invention further relates to a method for its use and optionally for subsequent metallization of such treated substrates. The method can be employed in semiconductor and solar cell manufacturing.

Abstract: Embodiments of the present invention provide methods for patterning a metal layer, such as a copper layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of patterning a metal layer on a substrate includes (a) supplying an etching gas mixture comprising a hydro-carbon gas into a processing chamber having a substrate disposed therein, the substrate having a metal layer disposed thereon, (b) exposing the metal layer to an ashing gas mixture comprising a hydrogen containing gas to the substrate, and (c) repeatedly performing steps (a) and (b) until desired features are formed in the metal layer. During the patterning process, the substrate temperature may be controlled at greater than 50 degrees Celsius.

Abstract: A method and structure for providing conformal doping of FinFET fin structures, for example by way of a thermal treatment process, includes forming a gate stack at least partially over a fin extending from a substrate. In various embodiments, a barrier metal layer is deposited over the gate stack. By way of example, a thermal fluorine treatment is performed, where the thermal fluorine treatment forms a fluorinated layer within the barrier metal layer, and where the fluorinated layer includes a plurality of fluorine atoms. In some embodiments, after forming the fluorinated layer, an anneal is performed to drive at least some of the plurality of fluorine atoms into the gate stack (e.g., into the interfacial layer and the high-K dielectric layer), thereby conformally doping the gate stack with the at least some of the plurality of fluorine atoms.

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

Abstract: In a mold die, a tip-end surface of each push-up pin provided on the rear surface side of a lower die cavity block and a part of the rear surface of the lower die cavity block with which the tip-end surface of each push-up pin is contacted are inclined in such a manner that a distance to a top surface of the lower die cavity block becomes longer towards the pot side where mold resin is supplied. When the lower die cavity block is returned to the initial position, the lower die cavity block is lifted while being slightly moved towards the pot block side. No gap is formed between a side surface of the pot block and a side surface of the lower die cavity block.

Abstract: In order to remove a deposit adhered to the backside of the peripheral portion of a wafer, a cleaning gas containing carbon dioxide gas is set to a pressure that is slightly lower than the pressure corresponding to a vapor pressure line of carbon dioxide at a temperature in the nozzle, and a gas cluster of carbon dioxide is generated. A gas cluster of carbon dioxide generated under such a condition is in a state immediately prior to undergoing a phase change to a liquid and therefore is a gas cluster having a large cluster diameter and having molecules that are firmly solidified.

Abstract: A device for measuring the distribution and/or impulse of a series of droplets comprises a piezoelectric sensor positioned relative to a source of droplets such that each of a plurality of droplets contacts the piezoelectric sensor in succession, thereby to generate an electrical signal. Logic circuitry is configured to calculate one or more frequencies from the electrical signal.

Abstract: A device and method for treatment of a substrate treatment surface of a substrate with a fluid by immersion of the substrate treatment surface into the fluid. The device includes: receiving means for receiving the fluid with an immersion opening and immersion means for immersion of the substrate treatment surfaces through the immersion opening into the receiving means, Rotation means are provided for rotation of the receiving means for at least predominant discharge of the fluid from the receiving means.

Abstract: A honeycomb heater includes a lamp housing having an outer edge that forms a partial circle. The lamp housing has an opening extending from a top surface to a bottom surface of the lamp housing. The opening further extends from the outer edge into a center region of the lamp housing. A plurality of lamps is distributed throughout the lamp housing, and is configured to emit light out of the top surface of the lamp housing.

Abstract: A platen assembly includes a base and a clamping layer fixed to the base. A portion of the base that faces the clamping layer and a portion of the clamping layer that faces the base define a gap between the base and the clamping layer. The gap is configured to circulate a fluid during a first operating mode and provide a thermal break during a second operating mode. The platen assembly is capable of operating over a wide temperature range.

Abstract: A method for curing at least in part a photoresist applied to a substrate comprises the following steps: The substrate coated with the photoresist is arranged on a support. The photoresist is subjected to a suitable temperature for curing the photoresist for a first predetermined time period. After the first predetermined time period has passed, the substrate is lifted from the support, rotated, re-placed onto the support and subjected to a suitable temperature for curing the photoresist for a second predetermined time period. This method can be performed with a device for curing at least in part a photoresist applied to a substrate, comprising a chamber, a support which is arranged in the chamber and on which the substrate can be arranged, and a rotating device for rotating the substrate between a first and a second phase of the curing of the photoresist.

Abstract: An apparatus, method, and system for collecting data related to effluent emitted from tools in semiconductor fabrication facilities using one or more sensors to take continuous real-time samples of the effluent to indicate one or more properties and characteristics of effluent, and based at least in part on the properties and characteristics indicated in the samples taken by at least one or more sensors, determining the proper processing, recyclability, and treatment of the effluent.

Abstract: An apparatus for transporting a substrate includes a base, a holding device which retracts relative to the base and holds multiple substrates in multiple stages, respectively, a detection device including three detection components such that the three detection components are positioned to detect peripheries of the substrates held by the holding device from different positions, respectively, and a control device including circuitry which estimates a position of the substrates based on detection result of the detection device, calculates an amount of shifting between a base position and an estimated position of the substrates, determines whether a calculated amount of shifting is within a threshold value, and executes transport of the substrates held by the holding device when the calculated amount of shifting is determined to be within the threshold value.

Abstract: The lateral substrate support part has: a plurality of plate parts, which have a parallel positional relationship, and support end portions of a plurality of substrates; and a plate-part support part, which supports the plate part, and is fixed to a side wall. The plate-part support part has: a groove-forming portion having a groove formed therein, said groove linearly extending over the whole plate parts in the direction intersecting the plate parts; a protrusion, which is formed in the groove, and which protrudes such that the protrusion reduces the width of the groove in the direction orthogonal to the direction in which the groove extends; and a positioned part that is formed at a center portion of the groove in the direction in which the groove extends.

Abstract: Provided are a substrate processing apparatus, a method of manufacturing a semiconductor device, and a non-transitory computer-readable recording medium, which are capable of reducing an effect on a substrate, which is caused by a change in an atmosphere in a substrate storage container, by appropriately supplying an inert gas into the substrate storage container.

Abstract: According to an aspect of an embodiment of the invention, there is provided an electrostatic chuck including: a ceramic dielectric substrate including a first major surface for mounting a clamped target, a second major surface on opposite side from the first major surface, and a through hole provided from the second major surface to the first major surface; a metallic base plate supporting the ceramic dielectric substrate and including a gas feed channel communicating with the through hole; and an insulator plug including a ceramic porous body provided in the gas feed channel and a ceramic insulating film provided between the ceramic porous body and the gas feed channel and being denser than the ceramic porous body, the ceramic insulating film biting into the ceramic porous body from a surface of the ceramic porous body.

Abstract: An assembly used in a process chamber for depositing a film on a wafer including a pedestal assembly having a pedestal movably mounted to a main frame. A lift pad rests upon the pedestal and moves with the pedestal. A raising mechanism separates the pad from the pedestal, and includes a hard stop fixed to the main frame, a roller attached to the pedestal assembly, a slide moveably attached to the pedestal assembly, a lift pad bracket interconnected to the slide and a pad shaft extending from the lift pad, a lever rotatably attached to lift pad bracket, a ferroseal assembly surrounding the pad shaft, and a yoke assembly offsetting a moment to the ferroseal assembly when the lever rotates. When the pedestal assembly moves upwards, the lever rotates when engaging with the upper hard stop and roller, and separates the pad from the pedestal by a process rotation displacement.

Abstract: A joining device for joining substrates together includes a first holding member configured to vacuum-suck a first substrate to draw and hold the first substrate on a lower surface thereof, and a second holding member disposed below the first holding member and configured to vacuum-suck a second substrate to draw and hold the second substrate on an upper surface thereof. The second holding member includes a body portion formed into a size larger than the second substrate when seen in a plan view and configured to vacuum-suck the second substrate, a plurality of pins provided on the body portion and configured to make contact with a rear surface of the second substrate, and an outer wall portion annularly provided on the body portion at an outer side of the plurality of pins and configured to support an outer periphery portion of the rear surface of the second substrate.

Abstract: A vacuum chuck has at least one suction assembly that pulls a wafer surface toward a chucking surface. The suction assembly may be used with a wafer that is warped. A suction force engages a pad of a suction assembly with the wafer surface and retracts a bellows of the suction assembly. As the bellows retracts and draws the wafer surface closer to the chucking surface, the suction force provided by the vacuum chuck can pull the wafer flat.

Abstract: A polishing apparatus according to an embodiment includes a first polishing part, a second polishing part, and an annular part. The second polishing part includes a mounting surface for a semiconductor substrate, and rubs the semiconductor substrate mounted on the mounting surface while pressing the semiconductor substrate against the first polishing part. The annular part includes a support part provided in the second polishing part, and a plurality of convex portions that project from the support part toward the first polishing part, are arranged in a circumferential direction around the mounting surface while being supported by the support part, and are movable in a radial direction of the semiconductor substrate.

Abstract: A vertical adjustment assembly is disclosed in order to provide for matching vertical positions of two substrates within separate chambers or cavities of a reaction system for processing of semiconductor substrates. The vertical adjustment assembly, in cooperation with a main lift driver, can provide for a more accurate positioning of the substrates to account for a tolerance stack-up error.

Abstract: Disclosed is a substrate processing apparatus and method which facilitate to improve uniformity of thin film material and also facilitate to control quality of thin film by the use of plasma forming space and source gas distributing space separately provided from each other, wherein the substrate processing apparatus includes a process chamber; a substrate support for supporting a plurality of substrates, the substrate support rotatably provided inside the process chamber; and an electrode unit arranged above the substrate support and provided with the plasma forming space and the source gas distributing space, wherein the plasma forming space is spatially separated from the source gas distributing space.

Abstract: A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into the trenches. The first dielectric layer fills lower portions of the trenches. A Ultra-Violet (UV) treatment is performed on the first dielectric layer in an oxygen-containing process gas. The method further includes depositing a second dielectric layer into the trenches. The second dielectric layer fills upper portions of the trenches. A thermal treatment is performed on the second dielectric layer in an additional oxygen-containing process gas. After the thermal treatment, an anneal is performed on the first dielectric layer and the second dielectric layer.

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract: A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.

Abstract: Methods of forming a self-aligned CT pillar with the same CD width as the device fins to enable PC isolation and the resulting devices are provided. Embodiments include forming a plurality of fins over a substrate; forming an oxide layer over the substrate and between each fin; removing a portion of a central fin among the plurality, a trench formed in the oxide layer; forming a CT pillar in the trench; recessing the oxide layer below an upper surface of the plurality of fins; forming a gate over the plurality of fins and CT pillar; planarizing the gate down to the CT pillar; and forming a cap layer over the gate and CT pillar.

Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly. The IC device or devices in the upper wafer or wafers have contact structures that serve as masks for the etching of the TSV opening. A conformal isolation liner is deposited in the TSV opening, and subsequently removed from the bottom and any horizontal areas in the TSV opening, while maintaining the liner on the sidewalls, followed by deposition of a TSV plug in the TSV opening. The removal of the liner is done without applying a lithography step.

Abstract: A method for selective etching using a dry film photoresist includes forming an opening through a substrate from a first surface to expose a stop layer at a second surface of the substrate. A material layer is formed over an inner surface of the opening and over the stop layer. The dry film photoresist is applied over the first surface of the substrate and over the opening. A second photoresist is applied on the dry film photoresist. First and second aligned holes are formed in the second photoresist and the dry film photoresist, respectively. The holes are approximately centered over the opening and are smaller in diameter than the opening so that a composite structure of the dry film photoresist and the second photoresist overhangs edges of the opening. The material layer is removed from the stop layer by etching via the first and second holes.

Abstract: A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of active layers stacked on the semiconductor substrate, and a gate structure overlapping the plurality of active layers. The gate structure includes a side gate region overlapping sides of the plurality of active layers and a top gate region overlapping a top of an uppermost active layer.

Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.

Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.