Abstract: Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array.

Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.

Abstract: A memory cell unit and a recurrent neural network including memory cell units are provided. The memory cell unit includes a first time gate configured to control a cell state value of the memory cell unit, based on a phase signal of an oscillatory frequency, and a second time gate configured to control an output value of the memory cell unit, based on the phase signal.

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic body and a second magnetic body. The first magnetic body extends in a first direction. The second magnetic body extends in the first direction. A distance between the second magnetic body and the first magnetic body changes periodically along the first direction.

Abstract: Methods and systems are described herein for determining if bit cell read or write rates require a refresh of the accessed or neighboring bit cells. The refresh of VLT memory bit cells that undergo a high frequency of page address read operations and write operations helps to maintain integrity of data stored in the VLT memory bit cells. The methods and systems determine, during each RAS cycle, if a rate of Page Address read operations or write operations exceeds a maximum rate across an interval, and conditionally cause a refresh operation if the rate exceeds the maximum rate. The methods and systems output a write back signal to cause a refresh of the associated VLT memory bit cells to prevent corruption of data stored in the associated VLT memory bit cells.

Abstract: A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a corresponding one of the plurality of memory cells MC; and a control circuit that intermittently monitors accesses to the plurality of word lines WL, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines WL in a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the Row Hammer problem, etc. can be taken.

Abstract: A method for calibrating capturing read data in a read data path for a DDR memory interface circuit is described. In one version, the method includes the steps of delaying a core clock signal by a capture clock delay value to produce a capture clock signal and determining the capture clock delay value. The capture clock signal is a delayed version of the core clock signal. The timing for the read data path with respect to data propagation is responsive to at least the capture clock signal. In another version, timing for data capture is responsive to a read data strobe or a signal derived therefrom, and a core clock signal or a signal derived therefrom.

Abstract: A semiconductor memory device including a weak cell storage circuit suitable for programming therein weak cell information, and outputting the weak cell information in an initialization operation; a cell array region including a first cell region which stores the weak cell information received from the weak cell storage circuit, in the initialization operation; a refresh address generation block suitable for generating a refresh address by counting a refresh signal, and outputting a weak cell address corresponding to the weak cell information outputted from the first cell region, as the refresh address, with a predetermined cycle; and a refresh circuit suitable for performing a refresh operation for a word line corresponding to the refresh address, among a plurality of word lines.

Abstract: A semiconductor memory device may include a sense amplifier for sensing and amplifying data of a bit line pair with pull-up and pull-down driving voltages; a voltage supplier for supplying a power supply voltage or an internal voltage lower than the power supply voltage as the pull-up driving voltage through a pull-up power supply line in response to a first or second pull-up control signal, and supplying a ground voltage as the pull-down driving voltage through a pull-down power supply line in response to a pull-down control signal; a voltage detector for detecting a voltage level of the power supply voltage and outputting a detection signal; and a control signal generator for generating the first and second pull-up control signals, and the pull-down control signal and delaying an enabling timing of one of the first pull-up and pull-down control signals in response to the detection signal.

Abstract: Techniques are disclosed for dynamic random access memory (DRAM) cell. The DRAM cell comprises a first bit line and a first complementary bit line, a storage capacitor having a first node coupled with the first complementary bit line, and a transistor selectable by a word line to couple a second node of the storage capacitor to the first bit line, wherein a voltage potential across the first bit line and the first complementary bit line when the transistor is selected is indicative of a bit of data.

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.

Abstract: Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell including a variable resistance element, a first circuit including a first resistance element and a first transistor, a first bit line, a second transistor, and a sense circuit. The memory cell and the first circuit are connected to the first bit line. One end and the other end of the second transistor are connected to the first bit line and the sense circuit respectively. During a first operation before reading data of the memory cell a voltage of the first bit line falls to a first voltage and the first and second transistors are turned off in response to a fall of the voltage of the first bit line to the first voltage.

Abstract: A multimodal memristor memory provides selectable or reconfigurable operation in a plurality of operational modes of a memristor. The multimodal memristor memory includes a memristor having a plurality of operational modes. The multimodal memristor memory further includes a reconfigurable interface driver to select an operational mode of the plurality of operational modes of the memristor. The memristor is to operate in the operational mode selected by the reconfigurable interface driver.

Abstract: For a memory array including a plurality of bit lines, and a set of write drivers having a number N members configured for connection in parallel to a selected set of N bit lines in the plurality of bit lines, write logic is coupled to the set of write drivers which enables a permissible number less than said number N of said members of the set of write drivers to apply a write pulse in parallel in a write operation. The write logic can dynamically assign permissible numbers to iterations in an iterative write sequence. A power source, such as charge pump circuitry, coupled to the set of write drivers can be utilized more efficiently in systems applying permissible bit write logic, enabling higher throughput or utilizing lower peak power.

Abstract: A non-volatile semiconductor memory device includes a memory array 20, including a plurality of memory elements; a selection part, selecting the memory elements of the memory array based on address data; a mode selection part 30, selecting any one of a RAM mode and a flash mode, where the RAM mode is a mode adapted to overwrite data of the memory element according to writing data, and the flash mode is a mode adapted to overwrite data of the memory element when the writing data is a first value and prohibit overwrite when the writing data is a second value; and a write control part, writing the writing data to the selected memory element according to the RAM mode or the flash mode selected by the mode selection part 30.

Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Abstract: A memory system includes a main memory array, a redundant memory array, and a content addressable memory (CAM). The CAM includes a plurality of entries, wherein each entry includes a plurality of column address bits and a plurality of maskable row address bits. When an access address for a memory operation matches an entry of the CAM, the memory system is configured to access the redundant memory array to perform the memory operation.

Abstract: Disclosed is a content addressable memory (CAM). The content addressable memory array includes a memory array and a data match module. The memory array includes multiple memory rows. Each memory row is configured to store a first data word and a second data word. The data match module includes a first match circuitry configured to compare a first match word to the first data word of a memory row, and to generate a first match output based on the comparison between the first match word and the first data word of the memory row. The data match module further includes a second match circuitry configured to compare a second match word to the second data word of the memory row, and to generate a second match output based on the comparison between the second match word and the second data word of the memory row.

Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation or erase operation of the memory cell array, and a control logic controlling the peripheral circuit. The control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell array during a first program operation of the program operation and a second program allowable voltage applied during a second program operation of the program operation are different from each other.

Abstract: A semiconductor memory device includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier electrically connected to the bit line and including a first latch, and a controller configured to execute a write operation on the memory cell. The write operation includes a first program operation followed by a verify operation that includes a step of updating data of the first latch and a second program operation that includes a step of pre-charging the bit line, wherein the step of pre-charging the bit line is initiated prior to the data of the first latch is updated.

Abstract: A power system with detecting function includes a power source, a power level detector, and a power floating detector. The power source includes multiple voltage sources for operations in multiple voltage domains, respectively. The power level detector is configured to constantly monitor the voltage level of each voltage domain. The power floating detector is configured to detect the presence of floating voltages in each voltage domain. Therefore, the present power system with detection function can guarantee stable operations and detect glitch attacks.

Abstract: A method and system are used to generate random values for Physical Unclonable Function (PUF) for use in cryptographic applications. A PUF value generation apparatus comprises two dielectric breakdown based anti-fuses and at least one current limiting circuit connected between anti-fuses and power rails. Two anti-fuses are connected in parallel for value generation in programming by applying high voltage to both anti-fuses at the same time. Time for dielectric breakdown under high voltage stress is of random nature and therefore unique for each anti-fuse cell. Therefore the random time to breakdown causes one cell to break before another, causing high breakdown current through the broken cell. Once high breakdown current through one broken or programmed cell is established, a voltage drop across a current limiting circuit leads to decreased voltage across both cells, thereby slowing the time dependent breakdown process in the second cell and preventing it from breakage under programming conditions.

Abstract: An OTP (One-Time Programmable) memory cell in an array has a programming MOSFET and symmetrically placed access transistors on either side of the programming MOSFET. The balanced layout of the memory cell improves photolithographic effects with a resulting improved process results. Results of programming the memory cell is also improved.

Abstract: A memory device includes a memory cell array, a multiplexing circuit, and a control logic circuit. The memory cell array includes a first sub memory cell array, a second sub memory cell array, and a third sub memory cell array. The multiplexing circuit selects the first sub memory cell array, the second sub memory cell array, and the third sub memory cell array in a first mode of operation, and when the first sub memory cell array is defective in a second mode of operation, the multiplexing circuit selects the second sub memory cell array and the third sub memory cell array. The control logic circuit selects the first mode of operation or the second mode of operation. The control logic circuit controls the multiplexing circuit so that the first, second and third sub memory cell arrays are connected to input or output pads.

Abstract: Techniques are presented for the determination defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defective blocks, a reference current is determined based on the amount of current drawn by the local interconnects when a high voltage is applied and all of the blocks are de-selected. The amount of leakage current is determined when a selected block is biased to ground and the high voltage is applied to the interconnects. By comparing the reference current to the leakage current, a determination can be made on whether the selected block has defects related to the local interconnect structure.

Abstract: A fuse circuit may include a plurality of first fuse sets and a plurality of second fuse sets. The plurality of first fuse sets may be used to store a defect address detected before packaging of a semiconductor apparatus. The plurality of second fuse sets may be used to store a defect address detected after the packaging. The plurality of first fuse sets may be shared by a plurality of first redundant word lines, and the plurality of second fuse sets may be in one-to-one correspondence with a plurality of second redundant word lines.

Abstract: A processor-based system for analyzing physiologic data and medical care is provided wherein the patient data is analyzed to construct images that are representative of a patient's condition. The processor provides a self-modulating analysis, which is responsive to the occurrence of additional data items to increase the information contained in the images. Identifications of modes of physiologic failure by the analysis of the generated images provides for earlier recognition and intervention and improved protocolization of testing and treatment.

Abstract: A method for fabricating assemblies includes providing first and second components that include ceramic, metal, or composite; positioning a multiphase joining interlayer between the first and second components, wherein the joining interlayer includes a first phase that melts at a first temperature and a second phase interspersed throughout the first phase, and wherein the second phase melts at a second temperature that is lower than the melting temperature of the first phase; and heating the joining interlayer to a temperature in the range of 725° C. to 1450° C. for a predetermined period of time to soften the first phase and melt the second phase, wherein the first phase remains in a solid or a semi-solid state, and wherein the second phase segregates to the boundaries of the first phase and transforms the joining interlayer into a substantially porosity-free adherent material that joins the first component to the second component.

Abstract: A fuel pellet for a nuclear reactor includes a plurality of tristructural-isotropic fuel particles embedded in a structural silicon carbide matrix. A method of manufacturing a fuel pellet includes the steps of coating a plurality of tristructural-isotropic fuel particles with a coating slurry including silicon carbide powder to form a plurality of coated fuel particles; compacting the plurality of fuel particles; and sintering the compacted plurality of fuel particles to form the fuel pellet.

Abstract: A magnetic jack control rod drive rod drive system having the magnetic coils that operate the moving parts of the drive system wound from anodized aluminum magnet wire or ceramic coated nickel clad copper and enclosed within a hermetically sealed housing that is pressurized with helium.

Abstract: A remote heat removal system that pumps a secondary fluid from a remote reservoir through a secondary side of a heat exchanger in heat exchange relationship with a primary fluid to be cooled. The secondary fluid drives a motive device that drives the primary fluid through the primary side of the heat exchanger.

Abstract: A chemical solution injection system 30 of an embodiment includes: a chemical solution reservoir 31 that stores a chemical solution containing a depositing substance to deposit to a member in contact with cooling water for absorbing heat in a plant; a pipe 32 through which the chemical solution passes; a first heat exchanger and a second heat exchanger that exchange heat between the cooling water and the chemical solution; a cooling water pipe 49 which connects the heat exchangers in series and in which the cooling water passes; and a pump 34 that conveys the chemical solution. The temperature of the chemical solution in the chemical solution reservoir 31 is lower than that of the cooling water. The pipe 32 sequentially connects the chemical solution reservoir 31, the first heat exchanger, the second heat exchanger and the plant. The cooling water guided from the inside of the plant passes through the second heat exchanger and subsequently passes through the first heat exchanger.

Abstract: Embodiments herein disclose a shielding curtain that is configured to block electromagnetic radiation from passing through it. The shielding curtain may be a flap portion of a larger shielding curtain or a single, unitary body that includes a single mounting bead and a plurality of flaps. The shielding curtain is formed of a polymer material that has a uniformly dispersed particulate material. Electromagnetic radiation emitted by an inspection system is blocked by the uniformly dispersed particulate material.

Abstract: Systems and methods of transferring nuclear fuel from fuel pools having size and/or weight limitations to a storage or transport cask are disclosed. A canister containing spent nuclear fuel is inserted into a transfer cask. A shielding sleeve is then placed around the transfer cask. A lifting device simultaneously lifts the transfer cask and the shielding sleeve over a storage cask and the spent fuel is transferred from the transfer cask to the storage or transport cask.

Abstract: A method for processing a radioactive liquid waste containing boron of the present invention includes: a molar ratio control step of adding an alkali metal or an alkali metal compound to a radioactive liquid waste containing boron to control an alkali metal/boron molar ratio in the radioactive liquid waste to be 0.8 or more; a drying step of drying the radioactive liquid waste having the controlled molar-ratio using a dryer to form a powdered waste; a dissolving step of mixing the powdered waste with kneading water to prepare a solution; and a kneading step of adding a hydraulic inorganic solidifying material to the solution, and kneading the hydraulic inorganic solidifying material and the solution for solidification.

Abstract: A system and method of disposing nuclear waste and other hazardous waste includes means for, and the steps of, blending a waste stream, which includes either a radioactive waste or a hazardous waste (or both), with a liquid and, optionally, a solid material to produce a dense fluid and pumping the dense fluid into a tubing string of an injection boring. The dense fluid then exits a perforation in a casing of the injection boring and enters a fracture in a rock strata, where it continues to propagate downward until it reaches an immobilization point. The dense fluid may be a slurry formed by a metal and a cross-linked polymer gel or hydrated clay slurry. The metal can be one that has a melting temperature less than the temperature at the bottom of the injection boring. The solid material could also be other nuclear waste or a radionuclide.

Abstract: One aspect of this copper alloy for an electronic device is composed of a binary alloy of Cu and Mg which includes Mg at a content of 3.3 to 6.9 atomic %, with a remainder being Cu and inevitable impurities, and a conductivity ? (% IACS) is within the following range when the content of Mg is given as A atomic %, ??{1.7241/(?0.0347×A2+0.6569×A+1.7)}×100. Another aspect of this copper alloy is composed of a ternary alloy of Cu, Mg, and Zn which includes Mg at a content of 3.3 to 6.9 atomic % and Zn at a content of 0.1 to 10 atomic %, with a remainder being Cu and inevitable impurities, and a conductivity ? (% IACS) is within the following range when the content of Mg is given as A atomic % and the content of Zn is given as B atomic %, ??{1.7241/(X+Y+1.7)}×100, X=?0.0347×A2+0.6569×A and Y=?0.0041×B2+0.2503×B.

Abstract: A thin plate is prepared by an ultraquenching transition control injector with a mixture of a metal powder having corrosion resistance to form a matrix and a powder having conductivity, as a raw material. When the matrix of the thin plate is crystal-structure metal, the plate can be formed at room temperature, and when the matrix is metallic glass, the plate can be formed in a supercooled liquid state. Therefore the plate can be finished into a separator with an intended shape.

Abstract: This application generally relates to deformable elastomeric conductors and differential signaling transmission techniques. According to one embodiment, a deformable elastomeric conductor is configured to transmit electrical signals. It comprises: an elastomeric polymer matrix; and conductive filler material uniformly dispersed in the elastomeric polymer matrix sufficient to render the material electrically conductive. The conductive filler material may include substantially non-entangled particles having an aspect ratio sufficiently large to enable the particles to substantially remain in contact and/or in close proximity with adjacent particles so as to maintain conductive pathways in the material when the material is subjected to deformation up to and exceeding 10% strain. Thus, over a transmission distance of an electrical signal through the conductor, the transmission does not suffer greater than about 3 dB of signal attenuation when subjected to the deformation.

Abstract: Polymeric compositions suitable for use as insulation materials in electrical applications. Such polymeric compositions comprise an ethylene/?-olefin-based elastomer and a filler, where the filler consists essentially of an amorphous silica. Such polymeric compositions can optionally further comprise an ethylene-based thermoplastic polymer. Also disclosed are coated conductors comprising such polymeric compositions as insulation materials.

Abstract: A multilayer insulated wire having a polyester-based resin layer formed of a polyester-based resin containing at least a trihydric or higher hydric alcohol constituent on a conductor, and a PEEK resin layer formed of polyether ether ketone or modified polyether ether ketone, directly or by interposing an intermediate layer, on the polyester-based resin layer; a coil formed by winding processing the insulated wire, and electronic/electrical equipment having the coil.

Abstract: A reinforcement arrangement for use with the connections of cable spices of undersea power cables that transport of electrical energy is disclosed. Each power cable includes an inner conducting core of copper or aluminum with one or more concentric polymeric and metallic layers that constitute insulation, screens and covers. The reinforcement arrangement is applied to the splicing of two cables at the conducting cores of each power cable, called a conducting cores connection area. The reinforcement arrangement includes a body that is disposed radially on the conducting cores connection area and on over the adjacent area of the outside outer covering of the power cable. The body is joined to the outer part covering of the power cables through a mechanical attaching element. The invention also relates to a method used to apply the reinforcement arrangement to the junctions of two submarine cables.

Abstract: Described herein are foamable compositions and methods of making foamed compositions. The foamable composition comprises at least one polymer and a foaming agent. The foaming agent comprises a talc or a talc derivative. The polymers described herein comprise a substantially non-halogenated polymer. One or more additives are added to render the compositions flame retardant and/or smoke suppressant. Also described are Power over Ethernet (PoE) cables, having at least one electrical conduit comprising an electrically conductive core, an insulation that at least partially surrounds said electrically conductive core and a polymeric separator extending from a proximal end to a distal end and having at least one channel adapted for receiving the at least one electrical conduit. The PoE cables are capable of carrying about 1 watt to about 200 watts of power.

Abstract: An alternating current (AC) power cable includes a conductor surrounded by at least an inner semiconductive layer including a first semiconductive composition, an insulation layer including a polymer composition, an outer semiconductive layer including a second semiconductive composition, and optionally a jacketing layer including a jacketing composition, in that order. The polymer composition of the insulation layer includes an unsaturated low density polyethylene (LDPE) copolymer of ethylene with one or more polyunsaturated comonomers and a crosslinking agent. The polymer composition of the insulation layer has a dielectric loss expressed as tan ? (50 Hz) of 12.0×10?4 or less, when measured at 25 kV/mm and 130° C. according to “Test for Tan ? measurements on 10 kV cables”.

Abstract: A terminal treatment apparatus for a coaxial cable including a core member having an inner conductor covered with an insulator, an outer conductor provided around the core member and formed of a plurality of wires, and a sheath covering an outer circumference of the outer conductor, includes a widening terminal to widen the outer conductor away from the core member by compressing a terminal-near portion of the exposed outer conductor from an outer circumferential side of the coaxial cable to deform the terminal-near portion of the exposed outer conductor.

Abstract: A sealing element for sealing a housing opening in a housing, wherein the sealing element comprises at least one through-opening for the passage of an electrical cable into the housing. The sealing element is formed of a first subcomponent and a second subcomponent, the first subcomponent and the second subcomponent having a different hardness and the two subcomponents are made of silicone.

Abstract: Systems and methods for providing electrical bushings for maintaining a seal during severe incidents are provided. The bushings provide for relatively large gap formations and seal spacings by using one or more self-modulating seals. In certain configurations, the bushings provide for relatively large gap formations and seal spacings by using a wider or narrow top portion adjacent to a relatively narrower middle portion. The systems and methods can be also applied to other apparatus when deemed proper.