Abstract: A maximum length of a heat sink is set as “L” and a warp amount of the heat sink is set as “Z”; the warp amount “Z” is set as a positive value if a bonded surface of the heat sink to a metal layer is deformed to be concave or the warp amount “Z” is set as a negative value if the bonded surface is deformed to be convex; a ratio Z/L of the maximum length “L” and the warp amount “Z” measured at 25° C. is in a range not smaller than ?0.005 and not larger than 0.005, and the ratio Z/L is in the range not smaller than ?0.005 and not larger than 0.005 even when it is heated to 280° C. and then cooled to 25° C.

Abstract: A method is disclosed of fabricating a power package which includes a heat tab extending from a die pad exposed on the underside of the package, which facilitates the removal of heat from the die to the PCB or other surface on which the package is mounted. The heat tab has a bottom surface coplanar with the flat bottom surface of the die pad and bottom surface of a lead. The lead includes a horizontal foot segment, a vertical columnar segment, and a horizontal cantilever segment facing the die pad. The heat tab may also have a foot. A die containing a power device is mounted on a top surface of the die pad and may be electrically connected to the lead using a bonding wire or clip. The die may be mounted on the die pad with as electrically conductive material, and the package may also include a lead that extends from the die pad and is thus electrically tied to the bottom of the die.

Abstract: A die mounting system in which die supply device is set on component mounter and dies supplied from die supply device are mounted on circuit board by mounting head of component mounter, determines the next die transfer position is determined such that the longer of time required for die transfer preparation operation (die imaging and image processing, die pickup operation, and movement and vertical inverting operation of a supply head) of die supply device and time required for die mounting operation (movement and vertical motion at the mounting position of mounting head) of component mounter is made shorter, and the difference (which corresponds to the waiting time at the die transfer position) between the two times decreased, such that the cycle time is shortened.

Abstract: Package structures and methods of forming package structures are described. A method includes depositing and patterning a first dielectric material. The first dielectric material is deposited in first and second package component regions and in a scribe line region. The scribe line region is disposed between the first and second package component regions. The patterning the first dielectric material forms a first dielectric layer in each of the first and second package component regions and a dummy block in the scribe line region. The dummy block is separated from the first dielectric layer in each of the first and second package component regions. The method further includes forming a metallization pattern on the first dielectric layer; depositing a second dielectric material on the first dielectric layer and the metallization pattern; and patterning the second dielectric material to form a second dielectric layer.

Abstract: The present disclosure relates to semiconductor packages and methods of manufacturing the same. In an embodiment, the semiconductor package includes a substrate, a semiconductor element, at least one connecting element, and an encapsulant. The semiconductor element is mounted to the substrate. The connecting element is disposed on the substrate and adjacent to the semiconductor element. The encapsulant covers at least a portion of the semiconductor element and at least a portion of the connecting element and defines at least one first groove surrounding the connecting element.

Abstract: The invention relates to a mold for encapsulating electronic components mounted on a carrier, with at least two mold parts which are displaceable relative to each other for engaging with a mold cavity round electronic components, and at least one feed for encapsulating material recessed into the mold parts and connecting to the mold cavity. The invention also relates to a carrier with encapsulated electronic components. The invention further relates to a method for encapsulating electronic components and to the thus manufactured encapsulated separated components. The carrier is provided with a plurality of recessed through-openings located at a distance from the electronic components and an encapsulation arranged round the electronic components, wherein through-openings are recessed into the encapsulating material and wherein some of the through-openings recessed into the carrier coincide at least partially with the through-openings recessed into the encapsulating material.

Abstract: A substrate treatment apparatus is used for treating a major surface of a substrate with a chemical liquid. The substrate treatment apparatus includes: a substrate holding unit which holds the substrate; a chemical liquid supplying unit having a chemical liquid nozzle which supplies the chemical liquid onto the major surface of the substrate held by the substrate holding unit; a heater having an infrared lamp to be located in opposed relation to the major surface of the substrate held by the substrate holding unit to heat the chemical liquid supplied onto the major surface of the substrate by irradiation with infrared radiation emitted from the infrared lamp, the heater having a smaller diameter than the substrate; and a heater moving unit which moves the heater along the major surface of the substrate held by the substrate holding unit.

Abstract: A substrate cleaning device 1 includes a substrate holding unit 10 configured to hold a substrate W, a first cleaning unit 11 having a first cleaning member 11a caused to come into contact with a first surface WA of the substrate W held by the substrate holding unit 10 to clean the first surface WA, a second cleaning unit 12 having a second cleaning member 12a caused to come into contact with the first surface WA of the substrate W held by the substrate holding unit 10 to clean the first surface WA, and a controller 50 configured to control the first and second cleaning units 11, 12 so that, when any one of the first cleaning member 11a and the second cleaning member 12a cleans the first surface WA of the substrate W held by the substrate holding unit 10, the other cleaning member is at a position apart from the substrate W held by the substrate holding unit 10.

Abstract: A substrate processing apparatus configured to rotate a substrate, such as a wafer, is disclosed. The substrate processing apparatus includes: a substrate holder configured to hold and rotate a substrate; a natural frequency calculator configured to determine a natural frequency of the substrate; and a processing controller configured to control a rotational speed of the substrate based on the natural frequency of the substrate. The processing controller is configured to control the rotational speed of the substrate such that the substrate is rotated at a rotational speed that is different from a rotational speed corresponding to the natural frequency of the substrate.

Abstract: The present disclosure relates to an apparatus and a method for treating a substrate with a liquid. A substrate treating apparatus includes a substrate supporting unit having a supporting plate for supporting a substrate and a bottom liquid supply unit for supplying a liquid to a bottom of the substrate supported by the supporting plate, wherein the bottom liquid supply unit includes a body and a liquid discharge nozzle for discharging a treatment liquid to the bottom of the substrate and coupled to the body and wherein an upper surface of the body includes a drainage hole for draining a liquid remaining in the body. Accordingly a liquid remained in the body may be discharged through the drainage hole.

Abstract: A manufacturing method of a semiconductor device according to the present invention comprises cleaning a semiconductor substrate. A first chemical liquid for forming a water-repellent protection film and a second chemical liquid coating the first chemical liquid are supplied on a surface of the semiconductor substrate. Alternatively, the semiconductor substrate is immersed in the first chemical liquid coated with the second chemical liquid. The semiconductor substrate is then dried.

Abstract: A system for preventing an unsafe operation of at least one machine communicatively coupled to a computing device. The system includes the computing device which includes a processor coupled to a memory. The memory contains processor-executable instructions that, when executed, cause the computing device to perform the steps of storing, in the memory, a first state of a first machine of the at least one machine, generating a first pending output to be issued to the first machine, determining whether an unsafe condition would result if the first pending output is issued to the first machine in the first state, and issuing the first pending output upon determining that issuing the first pending output would not result in an unsafe condition and blocking the first pending output from being issued upon determining that issuing the first pending output would result in an unsafe condition.

Abstract: An improved system and method for purging a microenvironment to desired levels of relative humidity, oxygen, or particulates through the implementation of a purge gas delivery apparatus and method that provides even distribution of the purging gas within the microenvironment. A substrate container has a tower therein with a fluid flow passageway extending the length of the tower. Apertures with porous media between the aperture and fluid flow passageway regulate the volume and pressure of air discharging at each aperture. Alternatively, the tower may be formed of a porous tubular polymeric material. A sleeve may direct the discharge purge gas in the interior.

Abstract: A semiconductor device, method, and tool of manufacture includes a semiconductor manufacturing tool. The semiconductor manufacturing tool includes push pins in a chuck and an edge ring over the chuck. The push pins are configured to hold a wafer, and are operable to vary a height of the wafer with respect to the chuck. The edge ring has a first width at a base proximate the chuck, and a second width at a point distal the chuck. The first width is greater than the second width. A distance from the wafer to the edge ring varies when the push pins vary the height of the wafer with respect to the chuck.

Abstract: Packaged semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a packaged semiconductor device includes a first device and a second device coupled to the first device. The second device includes an integrated circuit die covered by a molding compound. An over-mold structure is disposed over the second device.

Abstract: A method for fabricating an integrated circuit (IC) includes etching trenches into a semiconductor surface of a substrate that has a mask thereon. Trench implanting using an angled implant then forms doped sidewalls of the trenches. Furnace annealing after trench implanting includes a ramp-up portion to a maximum peak temperature range of at least 975° C. and ramp-down portion, wherein the ramp-up portion is performed in a non-oxidizing ambient for at least a 100° C. temperature ramp portion with an O2 flow being less than 0.1 standard liter per minute (SLM). The sidewalls and a bottom of the trench are thermally oxidized to form a liner oxide after furnace annealing to form dielectric lined trenches. The dielectric lined trenches are filled with a fill material, and overburden portions of the fill material are then removed to form filled trenches.

Abstract: The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.

Abstract: A method for forming a semiconductor device includes the following steps. An IMD layer is provided on a substrate. A plurality of block patterns is formed on the IMD layer. A plurality of dummy patterns is formed on the IMD layer and the block patterns. Portions of the IMD layer uncovered by the dummy patterns and the block patterns are etched to form a plurality of trenches of the IMD layer. After the trenches of the IMD layer are formed, the dummy patterns and the block patterns are removed, and a metal material is filled into the trenches to form metal lines.

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device includes a substrate including cell and peripheral regions, a stack on the cell region, vertical channel portions vertically penetrating the stack, a contact structure penetrating the stack, an insulating structure on the peripheral region, an impurity region in the peripheral region of the substrate, and a first contact penetrating the insulating structure and connected to the impurity region. The stack includes gate electrodes sequentially stacked on the substrate, and the contact structure is spaced apart from the vertical channel portions. A top surface of the first contact is positioned at a lower level than that of the contact structure.

Abstract: When a MISFET is formed by using a gate last process and replacing dummy gate electrodes with metal gate electrodes, both of respective cap insulating films and an interlayer insulating film over a control gate electrode and the dummy gate electrodes are polished to prevent excessive polishing of the upper surface of the interlayer insulating film and the occurrence of dishing. In the gate last process, the interlayer insulating film is formed to cover the control gate electrode and the dummy gate electrodes as well as the cap insulating films located thereover. After the upper surface of the interlayer insulating is polished to expose the cap insulating films from the interlayer insulating films, etching is performed to selectively remove the cap insulating films. Subsequently, the upper surfaces of the interlayer insulating films are polished.

Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric material; plugging the at least one self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.

Abstract: A wafer having on one side a device area with devices partitioned by division lines is divided into dies. An adhesive tape for protecting the devices is attached to the one side of the wafer, and a carrier for supporting the adhesive tape is attached to the outside of the adhesive tape. The other side of the wafer is ground to adjust the wafer thickness, and a protective layer is applied to the ground side of the wafer. The side of the wafer opposite to the adhesive tape is mechanically partially cut along the division lines with a first cutting width. A remaining part of the wafer, in the thickness direction thereof in the region or regions where the partial cut or cuts had been formed, is cut with a second cutting width. The second cutting width is smaller than or equal to the first cutting width.

Abstract: A method of forming a semiconductor device includes forming an active region in a first side of a silicon carbide substrate, the silicon carbide substrate having a second side opposite the first side and forming a contact pad at the first side. The contact pad is coupled to the active region. The method further includes forming an etch stop layer over the contact pad and plasma dicing the silicon carbide substrate from the second side. The plasma dicing etches through the silicon carbide substrate and stops on the etch stop layer. The diced silicon carbide substrate is held together by the etch stop layer. The diced silicon carbide substrate is attached on a carrier. The diced silicon carbide substrate is separated into silicon carbide dies by cleaving the etch stop layer.

Abstract: The present invention has an object to perform a peeling treatment in a short time. Peeling is performed while a peeling layer is exposed to an atmosphere of an etching gas. Alternatively, peeling is performed while an etching gas for a peeling layer is blown to the peeling layer in an atmosphere of an etching gas. Specifically, an etching gas is blown to a part to be peeled while a layer to be peeled is torn off from a substrate. Alternatively, peeling is performed in an etchant for a peeling layer while supplying an etchant to the peeling layer.

Abstract: A method for fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a first fin; forming a first set of gate structures on the first fin, where the gate structures are surrounded by an interlayer dielectric; forming a first contact hole in the interlayer dielectric between two adjacent gate structures; forming a first dopant source layer on the bottom of the first contact hole, where the dopant source layer comprise dopants with a first conductivity type; and annealing the first dopant source layer to diffuse the dopants out of the first dopant source layer.

Abstract: A method for manufacturing a semiconductor device includes forming a first gate structure on a semiconductor substrate. The first gate structure includes a first gate dielectric layer and a first gate electrode layer formed thereon. The method also includes forming an insulating material layer on the semiconductor substrate, wherein the semiconductor substrate and the first gate structure are covered by the insulating material layer. The method further includes removing a portion of the insulating material layer in a high-voltage element region to form a second gate dielectric layer in the high-voltage element region on the semiconductor substrate, and forming a second gate electrode layer on the second gate dielectric layer.

Abstract: A method for forming contacts on a semiconductor device includes forming trenches by etching an etch stop layer formed on an interlayer dielectric and etching the interlayer dielectric to expose source and drain regions between gate structures and depositing conductive material in the trenches and over the etch stop layer to a height above the etch stop layer. A resist is patterned on the conductive material with shapes over selected source and drain regions. The conductive material is subtractively etched to remove the conductive material from over the etch stop layer and to recess the conductive material into the trenches without the shapes to form self-aligned contacts below the shapes and lines in the trenches.

Abstract: The present invention further provides a method for forming a semiconductor device, comprising: first, a substrate having a fin structure disposed thereon is provided, wherein the fin structure has a trench, next, a first liner in the trench is formed, a first insulating layer is formed on the first liner, afterwards, a shallow trench isolation is formed in the substrate and surrounding the fin structure, wherein a bottom surface of the shallow trench isolation is higher than a bottom surface of the first insulating layer, and a top surface of the shallow trench isolation is lower than a top surface of the first insulating layer, and a dummy gate structure is formed on the first insulating layer and disposed above the trench, wherein a bottom surface of the dummy gate structure and a top surface of the fin structure are on a same level.

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a source/drain region, forming a first spacer within troughs defined by the plurality of fins and depositing a high-k dielectric layer, a work function material layer, and a conducting layer. The method further includes etching the high-k dielectric layer, the work function material layer, and the conducting layer to form recesses between the plurality of fins, depositing a liner dielectric, and etching portions of the liner dielectric to form a plurality of second spacers having a U-shaped configuration. The method further includes forming an epitaxial layer over the plurality of fins such that a gap region is defined between the plurality of second spacers and the epitaxial layer.

Abstract: Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.

Abstract: Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method includes forming a first semiconductor fin in a first region of a substrate and a second semiconductor fin in a second region of the substrate. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a first channel region of the second semiconductor fin. A first doped region is formed on the first semiconductor fin, adjacent to the first gate. A second doped region is formed in a top portion of the first doped region and a third doped region is formed in a top portion of the second semiconductor fin. The third doped region is removed to form a recess and the recess is filled with a fourth doped region.

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Abstract: Monitoring a geometric parameter value for one or more features produced on a substrate during an etch process may involve: (a) measuring optical signals produced by optical energy interacting with features being etched on the substrate; (b) providing a subset of the measured optical signals, wherein the subset is defined by a range where optical signals were determined to correlate with target geometric parameter values for features; (c) applying the subset of optical signals to a model configured to predict the target geometric parameter values from the measured optical signals; (d) determining, from the model, a current value of the target geometric parameter of the features being etched; (e) comparing the current value of the target geometric parameter of the features being etched to an etch process endpoint value for the target geometric parameter; and (f) repeating (a)-(e) until the comparing in (e) indicates that the current value of the target geometric parameter of the features being etched has reach

Abstract: Methods and apparatus are described for creating a multi-die package from a wafer without dicing the wafer into individual dies and reassembling the dies on an interposer. One example method generally includes testing a plurality of IC dies disposed on a wafer; disposing one or more connectivity layers above the plurality of IC dies, the one or more connectivity layers comprising one or more electrical conductors configured to connect together two or more of the plurality of dies in each of one or more groups of the IC dies; dicing the wafer having the one or more connectivity layers disposed above the plurality of dies into sets, each set comprising one or more of the plurality of dies, wherein the dicing is based on the one or more groups having IC dies that passed the testing; and packaging at least a portion of the sets of dies.

Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.

Abstract: A lead bonding structure includes: a plurality of leads extending outward from a package; and a plurality of electrode pads formed on a circuit board. The plurality of leads are soldered to the electrode pads, respectively. Each of the leads includes a lower wide portion having a width dimension greater than a width dimension of each of the electrode pads. The lower wide portion of each of the leads is soldered to the corresponding electrode pad.

Abstract: An electronic component includes a core, a winding, and an electrode. A flange of the core includes a body having a first surface that faces a top side and is located on the top side of a winding core of the core and first and second electrode formation portions protruding toward the top side of the first surface. The electrode is provided on a second surface of the first electrode formation portion and is connected to the winding. Space surrounded by the first and second electrode formation portions and the first surface is formed. A predetermined section between a point where the winding is separated from the winding core and a point where the winding comes into contact with the electrode extends toward the upper right side as viewed from the front, and does not include a portion of the winding an entire line width of which overlaps the space.

Abstract: A motor drive device detects the malfunction of a flow path in a heat sink based on the temperature of the device. The motor drive device includes: a temperature detection part which detects the temperature of the motor drive device; a temperature change calculating part which calculates the degree of change of the temperature with respect to time when the rotation number of a fan is controlled to a lower rotation number than a regular rotation number; an malfunction determination part which determines whether or not the degree of the change is different from a predetermined standard; and an malfunction signal generation part which generates a signal indicating that malfunction occurs in fluid flow when it is determined that the degree of the change is different from the standard.

Abstract: A temperature control device for controlling a temperature of a semiconductor device including a first chip and a second chip. The temperature control device may be configured to generate a correction temperature based on internal temperatures of the semiconductor device.

Abstract: In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core layer and electrically coupled to at least one contact pad arranged on a first side of the dielectric core layer, and a heat dissipation layer arranged on a second side of the dielectric core layer and thermally coupled to the semiconductor die. The semiconductor die has a thickness that is substantially equal to, or greater than, or equal to the thickness of the dielectric core layer. The heat dissipation layer includes a material with a substantially isotropic thermal conductivity.

Abstract: Disclosed herein are a double-side cooling type power module and a producing method thereof. The double-side cooling type power module includes a pair of semiconductor chips disposed between an upper substrate and a lower substrate. The double-side cooling type power module includes output terminal leads configured to be disposed on a lower surface of the upper substrate and each connected to the pair of semiconductor chips, respectively; a plus terminal lead configured to be disposed at one side of an upper surface of the lower substrate to be connected to any one semiconductor chip selected from the pair of semiconductor chips; and a minus terminal lead configured to be disposed at the other side of the upper surface of the lower substrate to be connected to the other semiconductor chip of the pair of semiconductor chips.

Abstract: A thermally conductive and electrically insulating layer is provided over a semiconductor structure.

Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

Abstract: Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a semiconductor package structure includes a substrate including a surface, a semiconductor die including a first interface surface connected to the surface of the substrate and a second interface surface opposing the first interface surface, a mold compound applied to the substrate surrounding the semiconductor die. The second interface surface of the semiconductor die is exposed from the mold compound. The semiconductor package structure includes a heat dissipation cover attached to the second interface surface of the semiconductor die and the mold compound.

Abstract: A system includes a front plate, a manifold cover, and bridge heat sinks. The manifold cover is secured to the front plate to define a fluid distribution chamber along a front side of the front plate. The manifold cover defines a port opening through which a cooling fluid is received from outside of the manifold cover. The bridge heat sinks extend rearward from a back side of the front plate. The bridge heat sinks define fluid channels that are fluidly connected with the fluid distribution chamber through corresponding slots in the front plate. The fluid distribution chamber is configured to distribute the cooling fluid received from outside of the manifold cover through the fluid channels of the bridge heat sinks in order to cool one or more electronics packages disposed along the bridge heat sinks without the cooling fluid engaging the one or more electronics packages.

Abstract: A power electronics assembly includes a semiconductor device stack having a wide bandgap semiconductor device, a semiconductor cooling chip thermally coupled to the wide bandgap semiconductor device, and a first electrode electrically coupled to the wide bandgap semiconductor device and positioned between the wide bandgap semiconductor device and the semiconductor cooling chip. The semiconductor cooling chip is positioned between a substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet port and the substrate outlet port and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more cooling chip fluid channels extending into the semiconductor cooling chip.

Abstract: A semiconductor package includes a substrate, an integrated circuit disposed on the substrate, a memory support disposed on the integrated circuit, stacked memory disposed on the memory support and in communication with the integrated circuit, and a lid connected to the substrate. The integrated circuit has a low power region and a high power region. The memory support is disposed on the low power region of the integrated circuit and is configured to allow a flow of fluid therethrough to conduct heat away from the low power region of the integrated circuit. The lid defines a first port, a second port, and a lid volume fluidly connecting the first port and the second port. The lid volume is configured to house the integrated circuit, the memory support, and the stacked memory, while directing the flow of fluid to flow over the integrated circuit, the memory support, and the stacked memory.

Abstract: A microelectronic package includes an interposer with through-silicon vias that is formed from a semiconductor substrate and one or more semiconductor dies coupled to the interposer. A first signal redistribution layer formed on the first side of the interposer electrically couples the one or more semiconductor dies to the through-silicon vias. A second redistribution layer is formed on a second side of the interposer, and is electrically coupled to the through-silicon vias. In some embodiments, a mold compound is connected to an edge surface of the interposer and is configured to stiffen the microelectronic package.

Abstract: An electronic component package may include: a redistribution layer including a first insulating layer, a first conductive pattern disposed on the first insulating layer, and a first via connected to the first conductive pattern while penetrating through the first insulating layer; an electronic component disposed on the redistribution layer; and an encapsulant encapsulating the electronic component. The first via has a horizontal cross-sectional shape in which a distance between first and second edge points of the first via in a first direction passing through the center of the first via and the first and second edge points thereof is shorter than that between third and fourth edge points of the first via in a second direction perpendicular to the first direction and passing through the center of the first via and the third and fourth points thereof.