Patents Issued in August 14, 2018
  • Patent number: 10049008
    Abstract: A method includes determining whether at least a portion of a data object requires rebuilding, wherein the data object is stored in accordance with a RAID format. The method further includes, when the at least a portion of the data object requires rebuilding, reconstructing stripes from sets of data blocks and parity blocks. The method further includes dividing the recovered data object into data segments. The method further includes dispersed storage error encoding the data segments in accordance with dispersed storage error encoding parameters to produce sets of encoded data slices, wherein a data segment is recoverable from a threshold number of encoded data slices. The method further includes issuing sets of write requests to write the sets of encoded data slices into storage units of a dispersed storage network (DSN).
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 10049009
    Abstract: Methods, systems and devices for remediation of a malfunctioning IHS (Information Handling Systems) using a peer IHS. Upon detecting a failure condition that prevents booting a primary operating system, the malfunctioning IHS initiates a remediation service as a BIOS/UEFI runtime process. The remediation service specifies remediation resources via an embedded web server. The web server provides a web interface that provides a peer IHS with resource links that provide access to remediation resources stored on the malfunctioning IHS. The web interface may also provide links that trigger the transfer of diagnostic information from the malfunctioning IHS to the peer IHS, which can be further relayed to a remote diagnostic service that may provide the peer IHS with updated remediation resources. The remediation resource may utilize pre-boot diagnostic processes to identify resources that are targeted to specific failures detected on the malfunctioning IHS.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: August 14, 2018
    Assignee: Dell Products, L.P.
    Inventors: Anantha Boyapalle, Yuan-Chang Lo, Marc Hammons, Philip Seibert, Todd Swierk
  • Patent number: 10049010
    Abstract: A method, a computer, and an apparatus for migrating memory data, where after receiving a first trigger instruction, a processor may exit an operating system and execute a memory data migration instruction of a basic input/output system, where the memory data migration instruction of the basic input/output system enables the processor to determine a source memory card of to-be-migrated memory data, determine a backup memory card for the source memory card, and instruct a memory controller of the source memory card to migrate the memory data in order to enable the memory controller of the source memory card to read the memory data of the source memory card and write the read memory data of the source memory card into the backup memory card according to an instruction of the processor.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: August 14, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Liping Yang, Teng Lv, Hongwei Sun
  • Patent number: 10049011
    Abstract: A processor-implemented method, for continuing operation of a quorum based system is provided. The method detects a loss of quorum. A plurality of speculative configurations is created, whereby each speculative configuration is isolated from other speculative configurations in the quorum based system. Each speculative configuration continues to order requests during the creation of speculative configurations. The method selects and starts one of the plurality of speculative configurations as a new operational configuration. Ordered requests continue to the new operational configuration. The original configuration of the quorum based system is restarted in response to the plurality of speculative configurations not being isolated.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Vita Bortnikov, Zvi Cahana, Shlomit I. Shachor, Ilya Shnayderman
  • Patent number: 10049012
    Abstract: In one example method, a group of directories is backed, and then a failure of an emitter is experienced. A respective saveset is created for each of several dynamic parallel save streams, where each saveset is associated with one or more emitters. Next, a path checkpoint ‘P’ is created using the smallest emitter, and a time checkpoint ‘S’ is created using an earliest savetime of all of the savesets. A retry is started using the time checkpoint ‘S’ and the path checkpoint ‘P’. One or more items are identified for backup and then sent to a director to be backed up. Next, savesets are generated for the backed up items. Finally, the generated savesets are combined with the savesets of the dynamic parallel save streams to form a global image for all save streams.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: August 14, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventor: Mu Chai
  • Patent number: 10049013
    Abstract: A system for applying a recovery mechanism to a network of medical diagnostics instruments is provided herein. The system includes the following: a plurality of medical diagnostics instruments, each associated with a network connected component; a plurality of communication modules, each associated with a corresponding one of the plurality of network connected components, wherein each one of the plurality of communication modules is arranged to report on malfunctioning components that are network connected with the corresponding component, and a recovery module, configured to: (i) obtain reports from the communication modules; (ii) re-establish the malfunctioning components; and (iii) notify all communication modules of the re-establishment of the malfunctioning components, wherein the communication modules are further configured to re-establish connection between the corresponding components and the re-established components.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: August 14, 2018
    Assignee: Bio-Rad Laboratories, Inc.
    Inventors: Shlomo Gabel, Eliran Tamir
  • Patent number: 10049014
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for receiving a first source file, the first source file including one or more first computer-aided design models; converting the first source file into a first plurality of files; generating a first snapshot, the first snapshot including the first source file, the first plurality of files, and a first version; receiving a second source file, the second source file having the first format that is readable by the first application, the second source file including one or more second models, the second source file being an updated version of the first source file; converting the second source file into a second plurality of files; generating a second snapshot; and associating the second snapshot with the first snapshot, where the second snapshot being a more recent version than the first snapshot.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: August 14, 2018
    Assignee: Autodesk, Inc.
    Inventors: James Awe, Johannes Leon Marais, Jianfeng Guo, Nathan James Pahucki
  • Patent number: 10049016
    Abstract: In the dedupe storage network priority to data replication needs to be given over the garbage collection (GC) activity. For this purpose GC running on any site should not impose any locking on its peer sites for replication. For replication activity GC activity must be completely transparent. In the dedupe storage network, the retention policy of a replicated image is controlled by the site where the image was originated. Distributed GC running on the originating site can only inform the replication sites the list of expired replicated images and cleanup of replicated garbage chunks from its remote FS database for corresponding replication sites. But it cannot cleanup garbage chunks from replication sites. Garbage chunks can only be cleaned by the local GC running on that site.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: August 14, 2018
    Inventors: Ashish Govind Khurange, Sachin Baban Durge, Kulangara Kuriakose George, Kuldeep Sureshrao Nagarkar, Ravender Goyal
  • Patent number: 10049017
    Abstract: A method for byzantine fault-tolerant replication of data on a plurality of n servers by a client, wherein the n servers include one primary node (PN) and n?1 replica nodes (REPN), wherein f servers may arbitrarily fail, and wherein all n servers include a trusted computing entity (TCE), includes: performing a request procedure, performing a prepare procedure, performing a commit procedure, and performing a reply procedure. The request procedure includes providing a request message for requesting a certain operation, and transmitting the request message to all n servers. The prepare procedure includes computing a prepare message including at least part of the content of the request message and a unique identifier (UI), the UI being computed by the TCE, the UI being based on a cryptographic signature of the request message and a unique, monotonic, sequential counter (UMSC), and providing the prepare message to the REPN.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 14, 2018
    Assignee: NEC Corporation
    Inventors: Ghassan Karame, Wenting Li, Jian Liu, Nadarajah Asokan, Andrew Paverd
  • Patent number: 10049018
    Abstract: An information processing apparatus, backup method, and program product that enable efficient differential backup. In one embodiment, an information processing apparatus for files stored in a storage device includes: a metadata management unit for managing metadata of files stored in the storage device; a map generation unit for generating a map which indicates whether metadata associated with an identification value uniquely identifying a file in the storage device is present or absent; and a backup management unit for scanning the metadata to detect files that have been created, modified, or deleted since the last backup, and storing at least a data block and the metadata for a detected file in a backup storage device as backup information in association with the identification value.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Norie Iwasaki, Sosuke Matsui, Tsuyoshi Miyamura, Terue Watanabe, Noriko Yamamoto
  • Patent number: 10049019
    Abstract: An information processing apparatus, backup method, and program product that enable efficient differential backup. In one embodiment, an information processing apparatus for files stored in a storage device includes: a metadata management unit for managing metadata of files stored in the storage device; a map generation unit for generating a map which indicates whether metadata associated with an identification value uniquely identifying a file in the storage device is present or absent; and a backup management unit for scanning the metadata to detect files that have been created, modified, or deleted since the last backup, and storing at least a data block and the metadata for a detected file in a backup storage device as backup information in association with the identification value.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Norie Iwasaki, Sosuke Matsui, Tsuyoshi Miyamura, Terue Watanabe, Noriko Yamamoto
  • Patent number: 10049020
    Abstract: Disclosed herein are system, method, and computer program product embodiments for providing point in time recovery on a database. An embodiment operates by determining that one or more values were written to one of a plurality of database nodes of a database as part of a write transaction. The one or more data pages to which the one or more values were written are copied to a storage location of a backup corresponding to the write transaction. The storage location of the one or more data pages in the backup are written to a location in a transaction log corresponding to the write transaction.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 14, 2018
    Assignee: SYBASE, INC.
    Inventors: Blaine French, Nandan Marathe, Fang-Ying Yen
  • Patent number: 10049021
    Abstract: A redundant system includes a primary system including a first node and a second node, and a secondary system including a third node and a fourth node. When the secondary system in place of the primary system operates, the fourth node executes first takeover processing or second takeover processing, the first takeover processing taking over the primary system on the basis of data update information acquired from either a second inter-system transfer path or a second intra-system transfer path, and the second takeover processing taking over the primary system on the basis of both the data update information acquired from the second inter-system transfer path and the data update information acquired from the second intra-system transfer path.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: August 14, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Motoyuki Mashima, Tomoaki Mizoo, Toshirou Ono
  • Patent number: 10049022
    Abstract: A method, system, and computer program for high-availability database systems. The method commences by replicating (e.g., from a first server to a second server) a data structure having entries describing resource locks and client states. The replication can be performed to any number of servers. Upon detecting a failure of a connection between the first server and a client to which the first server is connected, the system establishes a new connection between the second server and the client by updating the replicated data structure to describe new connection between the second server and the client and updating the entries of the replicated data structure to reflect the new connection and the then current aspects of the resource locks and client states. The client can be a database instance, and the act of replicating can be accomplished using a broadcast channel. The servers can be organized in a computing cluster.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: August 14, 2018
    Assignee: Oracle International Corporation
    Inventors: Rajiv Gamani Wickremesinghe, Harish Nandyala, Prasad V. Bagal, Richard Lawrence Long, Shie-rei Huang, Dungara Ram Choudhary
  • Patent number: 10049023
    Abstract: Various systems, methods, and processes to perform recovery operations in a cluster based on exponential backoff models are disclosed. A node failure is detected. The node is one of multiple nodes in a cluster. In response to the node failure, an application executing on the node is failed over to another node in the cluster. In response to the detecting the node failure, recovery operations are automatically performed to determine whether the node is recovered. A subsequent recovery operation is performed after a prior recovery operation. The subsequent recovery operation is performed periodically based on a frequency that decreases exponentially after performing the prior recovery operation.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 14, 2018
    Assignee: Veritas Technologies LLC
    Inventor: Anand J. Bhalerao
  • Patent number: 10049024
    Abstract: A data processing method, a device, and a system for a storage unit in order to avoid performing repeated data read operations on the storage unit where the method includes recording, by a first server for at least one storage unit used to store data, information about a storage unit in which a repairable fault occurs but repairing fails, querying, by the first server each time a request for reading data is received, whether the storage unit corresponding to the recorded information about the storage unit stores a part or all of the data, and when the storage unit corresponding to the recorded information stores the data, returning, to a requesting party that sends the request, a message indicating that reading the data fails, or otherwise, reading the data from a storage unit that stores the data, and feeding back the data to the requesting party that sends the request.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: August 14, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Zhongping Chen
  • Patent number: 10049025
    Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 14, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shrey Bhatia, Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch
  • Patent number: 10049026
    Abstract: Embodiments of bus interface systems and methods of operating the same are disclosed. In one embodiment, a bus interface system includes a master bus controller and multiple slave bus controllers that are each coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. Each of the slave bus controllers decodes the first set of data pulses along the bus line representing the payload segment and performs an error check. Each slave bus controller is then configured to generate an acknowledgement pulse along the bus line to indicate that the slave bus controller's particular error check was passed. In this manner, the bus interface system can perform a group write bus function and the master bus controller can determine that the multiple slave bus controllers each received an accurate copy of the payload segment.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 14, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Christopher Truong Ngo, Alexander Wayne Hietala
  • Patent number: 10049027
    Abstract: Creating additional trace entries by dynamically processing recently captured output data, working data, and input data to diagnose a software error. Integrating additional trace entries in chronological order with conventional trace entries into a single trace dataset for analysis.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stephen J. Burghard, Samuel J. Smith, Mark A. Woolley, Andrew Wright
  • Patent number: 10049028
    Abstract: Systems and methods are disclosed for debug session management. For example, methods may include receiving a request from a client device and, in response, identifying a set of instructions to be executed, wherein the set of instructions is associated with at least one breakpoint. The methods may include initiating execution of the set of instructions. The methods may include determining, based on a marker, that pausing execution of the set of instructions using a data structure is permitted, and responsive to this determination: pausing execution of the set of instructions before executing an instruction associated with a breakpoint, and updating the marker to indicate that execution of the set of instructions has paused using the data structure.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: August 14, 2018
    Assignee: ServiceNow, Inc.
    Inventors: Christopher Tucker, Qian Zhang, Carl David Solis, Jr.
  • Patent number: 10049029
    Abstract: A debugger is provided that is capable of connecting internally or externally to a host device using one or more of multiple host interfaces. The debugger can also connect, over a network, to a remote communication device executing a debugging application. Through the debugger, the debugging application receives messages from the host device regarding the status of a firmware on the host device, and sends debugging commands to the host device for performing operations such as updating the firmware on the host device.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: August 14, 2018
    Assignee: American Megatrends, Inc.
    Inventor: Hoang Ngoc Minh Vu
  • Patent number: 10049030
    Abstract: A method and a system for test output evaluation of a JAVA component. The java component and reference classes are received and non-private members of the Java component are identified using JAVA reflection API and the reference classes. An API structure comprising public members is extracted from the non-private members. Behavior checking expressions are received and selected corresponding to the public members. A Java source code comprising wrapper methods wherein the wrapper method corresponds to the one or more public members and a test output evaluation method comprising the behavior checking expressions is generated. The test output evaluation of the JAVA component is performed using the test output evaluation method over the generated Java source code.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: August 14, 2018
    Assignee: Infosys Limited
    Inventors: Rakesh Shukla, Shruti Bansal
  • Patent number: 10049031
    Abstract: Embodiments of the invention provide for the correlation of violating change sets during regression testing of a computer program. A method of the invention includes annotating a test case with a reference to logical operations of different programmatic objects of a computer program. Thereafter, change sets are applied to the program and the test case is executed by a development environment such as a debugger to a point of failure. It is then determined from the annotations change sets related to the logical operations and different ones of the determined change sets are sequentially replaced and the test case repeatedly re-executed. As such, the ones of the replaced change sets resulting in failure from re-execution of the test case are determined to be violating change sets.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Corville O. Allen, Albert A. Chung, Andrew R. Freed, Richard A. Salmon, Eric Woods
  • Patent number: 10049032
    Abstract: The present invention provides a method and system for generating negative test input data. A set of attributes and a set of attribute properties can be extracted from a requirement specification. A constraint representation syntax can be framed from the extracted set of attribute properties. A structured diagram is modeled from the framed constraint representation syntax and a set of use cases, a set of path predicates can be constructed from the structured diagram. One or more attribute classes can be determined from the set of path predicates based on an attribute constraint and an attribute dependency. The negative test input data shall be generated from the one or more attribute classes using genetic algorithm.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: August 14, 2018
    Assignee: Infosys Limited
    Inventors: Anjaneyulu Pasala, Nihar Sharma, Saurav Singh
  • Patent number: 10049033
    Abstract: The present disclosure involves systems, software, and computer-implemented methods for certifying applications for execution in cloud computing systems. An example method includes identifying an application for execution in a cloud computing system; determining a set of application characteristics associated with the application based at least in part on an automatic analysis of the application; determining whether the application is suitable to be executed in the cloud computing system based at least in part on the determined set of application characteristics; and in response to determining that the application is suitable for use in the cloud computing system, storing the application and at least a portion of the determined set of application characteristics in an application repository.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: August 14, 2018
    Assignee: SAP SE
    Inventor: Oliver Daute
  • Patent number: 10049034
    Abstract: Performing data processing for data sets stored in each of a plurality of storage devices includes collecting access data indicating details of accesses to each of the plurality of storage devices and computing predicted changes in access frequency for each of the storage devices on the basis of the access data for each of the plurality of storage devices in response to a request to reserve a storage area for storing a new data set. A storage device in which the storage area for storing the new data set is to be reserved is selected from among the plurality of storage devices on the basis of the predicted changes for each storage device.
    Type: Grant
    Filed: December 17, 2017
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mayumi Goto, Noriaki Takatsu, Atsushi Yokoi
  • Patent number: 10049035
    Abstract: A disclosed stream memory management circuit includes a first memory controller circuit for accessing a first memory of a first type. A second memory controller circuit is provided for accessing a second memory of a second type different from the first type. An access circuit is coupled to the first and second memory controller circuits for inputting and outputting streaming data. An allocation circuit is coupled to the access circuit, the allocation circuit configured and arranged to select either the first memory or the second memory for allocation of storage for the streaming data in response to attributes associated with the streaming data. A de-allocation circuit is coupled to the access circuit for de-allocating storage assigned to the streaming data from the first and second memories.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 14, 2018
    Assignee: Reniac, Inc.
    Inventors: Chidamber Kulkarni, Prasanna Sundararajan
  • Patent number: 10049036
    Abstract: Methods and apparatus for reliable distributed messaging are described. A computer system includes a system memory coupled to one or more processors. The system memory comprises at least a non-volatile portion. A particular location within the non-volatile portion is designated as a target location to which a sender module participating in a communication protocol is granted write permission. A receiver module participating in the communication protocol, subsequent to a failure event that results in a loss of data stored in a volatile portion of the system memory, reads a data item written by the sender program at the target location prior to the failure event. The receiver module performs an operation based on contents of the data item.
    Type: Grant
    Filed: August 20, 2017
    Date of Patent: August 14, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Samuel James McKelvie, Anurag Windlass Gupta
  • Patent number: 10049037
    Abstract: A storage system, and a method of data management in the storage system, with non-volatile memory device characteristics determined during an inspection of non-volatile memory devices before a runtime operation of a storage device in the storage system including: a controller in the storage system: a drive-level control unit configured for an update of operational capabilities based on the non-volatile memory device characteristics during the runtime operation of the storage device and for a group of the non-volatile memory devices based on the operational capabilities; and a memory control unit, coupled to the drive-level control unit, the memory control unit configured to receive the operational capabilities for control of the non-volatile memory devices.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: August 14, 2018
    Assignee: SanDisk Enterprise IP LLC
    Inventors: John Scaramuzzo, Bernardo Rub, Robert W. Ellis, James Fitzpatrick
  • Patent number: 10049038
    Abstract: A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: August 14, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Luca De Santis, Pasquale Conenna
  • Patent number: 10049039
    Abstract: A memory system may include: a memory device including a plurality of pages each having a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host, and a plurality of memory blocks each having the pages; and a controller suitable for grouping the pages included in the memory blocks so as to divide each of the memory blocks into a plurality of page zones, and storing data corresponding to a write command into pages of a second memory block of the memory blocks and storing program update information on a first page zone of a first memory block of the memory blocks into a list, when receiving the write command for data stored in a first page of the first page zone in the first memory block.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: August 14, 2018
    Assignee: SK Hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10049040
    Abstract: The disclosure is related to systems and methods of managing a memory. In a particular embodiment, a memory is disclosed that includes multiple garbage collection units. The memory also includes a controller that determines whether to select a garbage collection unit of the multiple garbage collection units for garbage collection based on a variable threshold number of the multiple garbage collection units to garbage collect.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: August 14, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: David S. Ebsen, Ryan J. Goss
  • Patent number: 10049041
    Abstract: A system and method for Java object storage and retrieval in a non-volatile all flash memory database. Bean annotations define the attributes of objects and object classes that are created using a Java compiler in an all flash Java runtime environment. Object indexes are created based upon these attributes, and a Java object query language using the indexes is employed to locate objects in the all flash memory database. A new transactional model is provided for managing objects and memory in the all flash memory database, and a new garbage collector deletes objects and reclaims memory.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 14, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Jeroen M. van Rotterdam, Michael Mohen, Ravi Ranjan Jha, Sreecharan Shroff
  • Patent number: 10049042
    Abstract: The present invention improves an access performance in an SSD device in which a nonvolatile semiconductor, such as a NAND flash memory, is mounted, or in a storage subsystem having the SSD device built therein, and achieves longer operating life. For this purpose, a plurality of units (logical-physical sizes) for associating a logical address with a physical address is provided in the SSD device or the storage subsystem, and an appropriate logical-physical size is selected in accordance with an I/O size or I/O pattern accessed from a superior device.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: August 14, 2018
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Tsuruya, Atsushi Kawamura, Akifumi Suzuki, Hideyuki Koseki
  • Patent number: 10049043
    Abstract: A data processing apparatus 2 performs multi-threaded processing using the processing pipeline 6, 8, 10, 12, 14, 16, 18. Flush control circuitry 30 is responsive to multiple different types of flush trigger. Different types of flush trigger result in different sets of state being flushed for the thread which resulted in the flush trigger with state for other thread not being flushed. For example, a relatively low latency stall may result in flushing back to a first flush point whereas a longer latency stall results in flushing back to a second flush point and the loss of more state data. The data flushed back to the first flushed point may be a subset of the data flushed back to the second flush point.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: August 14, 2018
    Assignee: ARM Limited
    Inventor: Peter Richard Greenhalgh
  • Patent number: 10049044
    Abstract: Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: August 14, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Boyer, Gabriel Loh, Nuwan Jayasena
  • Patent number: 10049045
    Abstract: Techniques described herein generally include methods and systems related to cooperatively caching data in a chip multiprocessor. Cooperatively caching of data in the chip multiprocessor is managed based on an eviction rate of data blocks from private caches associated with each individual processor core in the chip multiprocessor. The eviction rate of data blocks from each private cache in the cooperative caching system is monitored and used to determine an aggregate eviction rate for all private caches. When the aggregate eviction rate exceeds a predetermined value, for example the threshold beyond which network flooding can occur, the cooperative caching system for the chip multiprocessor is disabled, thereby avoiding network flooding of the chip multiprocessor.
    Type: Grant
    Filed: March 5, 2017
    Date of Patent: August 14, 2018
    Assignee: Empire Technology Development LLC
    Inventor: Ezekiel Kruglick
  • Patent number: 10049046
    Abstract: Methods and apparatus for providing region zero-fill on demand for tiered memory including a first region in a first memory tier having a page cache in physical memory, where virtual memory includes a mmap of the first region. An input can be controlled between zeroes and the first region to the page cache.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: August 14, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Adrian Michaud, Roy E. Clark, Kenneth J. Taylor
  • Patent number: 10049047
    Abstract: A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. The SSD further includes one or more volatile memory devices communicatively coupled to the memory controller, where at least one of the one or more volatile memory devices has a read cache area. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC write cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: August 14, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Narasimhulu Dharani Kotte, Senthil Thamgaraj, Robert Reed, Hitoshi Kondo
  • Patent number: 10049048
    Abstract: A processor cache is logically partitioned into a main partition, located in the cache itself, and an enclave partition, located within an enclave, that is, a hardware-enforced protected region of an address space of a memory. This extends the secure address space usable by and for an application such as a software cryptoprocessor that is to execute only in secure regions of cache or memory.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: August 14, 2018
    Assignee: Facebook, Inc.
    Inventors: Oded Horovitz, Stephen A. Weis, Sahil Rihan, Carl A. Waldspurger
  • Patent number: 10049049
    Abstract: A disclosed information processing method is executed in a distributed processing system that processes data by plural information processing apparatuses. And the information processing method includes: obtaining, by a first information processing apparatus of the plural information processing apparatuses and from a second information processing apparatus that manages relations among data, identification information of first data that has a predetermined relation with second data and identification information of an information processing apparatus that manages the first data, upon detecting access to the second data managed by the first information processing apparatus; reading out, by the first information processing apparatus, the first data, upon determining that the information processing apparatus that manages the first data corresponds to the first information processing apparatus; and loading, by the first information processing apparatus, the first data into a cache.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: August 14, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Yasuo Koike, Kazuhisa Fujita, Toshiyuki Maeda, Tadahiro Miyaji, Tomonori Furuta, Fumiaki Itou
  • Patent number: 10049050
    Abstract: Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen L. Blinick, Charles S. Cardinell, Roger G. Hathorn, Bernhard Laubli, Miguel A. Montoya, Timothy J. Van Patten
  • Patent number: 10049051
    Abstract: Systems and methods are described to reserve cache space of points of presence (“POPs”) within a content delivery network (“CDN”). A provider may submit a request to the CDN to reserve cache space on one or more POPs for data objects designated by that provider. Thereafter, the CDN may mark those designated data objects within its cache as protected from eviction. When the CDN implements a cache eviction policy on the cache, the protected objects may be ignored for purposes of eviction, or may be evicted only after non-protected data objects.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 14, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Matthew Graham Baldwin
  • Patent number: 10049052
    Abstract: A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. The mirror unit is arranged for providing at least two buffer mirrors at respective different buffer mirror address ranges in the main address range by adapting the memory addressing. Due to the virtual mirrors data on a respective address in any of the respective different buffer mirror address ranges is the data of the buffer memory at a corresponding address in the buffer address range. The device enables processing of a subsequent set of data in the buffer memory via the cache memory without invalidating the cache by switching to a different buffer mirror.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: August 14, 2018
    Assignee: NXP USA, Inc.
    Inventors: Ray Charles Marshall, Joachim Fader, Stephan Herrmann
  • Patent number: 10049053
    Abstract: An external storage resource pool associated with federated tiered storage is associated with at least one performance tier based on evaluated performance of the external storage resource pool. Performance of the external pool may be evaluated in terms of service level expectations or service level objectives. Workload pattern analysis or performance probability curves may be used to classify the external storage resource pool. Workload distribution may be determined by a margin analysis algorithm that matches workloads and storage resource pool performance characteristics.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: August 14, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Malak Alshawabkeh, Owen Martin, Xiaomei Liu, Sean Dolan, Hui Wang
  • Patent number: 10049054
    Abstract: The present disclosure is related to a virtual register file. Source code can be compiled to include references to a virtual register file for data subject to a logical operation. The references can be dereferenced at runtime to obtain physical addresses of memory device elements according to the virtual register file. The logical operation can be performed in the memory device on data stored in the memory device elements.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 14, 2018
    Assignee: Micron Technology, Inc.
    Inventors: John D. Leidel, Geoffrey C. Rogers
  • Patent number: 10049055
    Abstract: Some implementations provide a method for managing data in a storage system that includes a persistent storage device and a non-volatile random access memory (NVRAM) cache device. The method includes: accessing a direct mapping between a logical address associated with data stored on the persistent storage device and a physical address on the NVRAM cache device; receiving, from a host computing device coupled to the storage system, a request to access a particular unit of data stored on the persistent storage device; using the direct mapping as a basis between the logical address associated with the data stored on the persistent storage device and the physical address on the NVRAM cache device to determine whether the particular unit of data being requested is present on the NVRAM cache device.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 14, 2018
    Assignee: VIRIDIENT SYSTEMS, INC
    Inventors: Shibabrata Mondal, Vijay Karamcheti, Ankur Arora, Ajit Yagaty
  • Patent number: 10049056
    Abstract: Data operations, requiring a lock, are batched into a set of operations to be performed on a per-core basis. A global lock for the set of operations is periodically acquired, the set of operations is performed, and the global lock is freed so as to avoid excessive duty cycling of lock and unlock operations in the computing storage environment.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: August 14, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Lokesh M. Gupta, David B. Whitworth
  • Patent number: 10049057
    Abstract: A processor includes a front end to receive an encrypted instruction sequence. The processor also includes a decoder including logic to identify a encrypted command from a packet in the encrypted instruction sequence, logic to identify a key index from the packet, logic to determine an encrypted opcode lookup table with the key index, logic to look up a decoded opcode from the encrypted opcode lookup table based upon the key index, and logic to forward the decoded opcode for execution.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Imran Desai, Elmoustapha Ould-Ahmed-Vall
  • Patent number: 10049058
    Abstract: A method for method for resolving a cable mismatch by a target device is provided. The method includes determining that all PHYs in a receptacle are currently inactive, a PHY in the receptacle became active, and determining if there is a mismatch between a cable type and a stored cable configuration. If there is a mismatch between the cable type and the stored cable configuration, the method further includes disabling all other PHY groups in the receptacle that do not include the PHY that became active and notifying a user that a cable mismatch corresponding to the receptacle has occurred. If there is not a mismatch between the cable type and the stored cable configuration, then the method includes re-enabling PHYs in the receptacle, if any PHYs are disabled, and notifying a user that a cable mismatch corresponding to the receptacle has been corrected.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: August 14, 2018
    Assignee: Seagate Technology LLC
    Inventor: Phillip Raymond Colline