Abstract: A SIMD processor may be configured to determine one or more active threads from a plurality of threads, select one active thread from the one or more active threads, and perform a divergent operation on the selected active thread. The divergent operation may be a serial operation.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for computing a multivalue reduction using a parallel processing device. One of the methods includes performing a parallel M-value reduction by parallel processing units of a parallel processing device. A plurality of initial reductions are performed in serial, each initial reduction operating on data in a different respective register space of at least M register spaces. Data is moved from the M register spaces so that all results from the plurality of initial reductions are in a same first register space. One or more subsequent reductions are performed in parallel to compute M final values, each subsequent reduction operating only on data in the first register space.

Abstract: A system-on-a-chip includes a plurality of instruction processors and a hardware block such as a system management unit. The hardware block accesses values of performance counters associated with the plurality of instruction processors and modifies one or more operating points of one or more of the plurality of instruction processors based on comparisons of the instruction arrival rates and the instruction service rates to achieve optimized system metrics.

Abstract: A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memory of the first operand, generating a hash value using a 512 bit secure hash technique and at least one seed value of a parameter block of the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number.

Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

Abstract: A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data elements stored in a storage location indicated by a first source operand. The instruction schedule/dispatch unit is to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand. The processor further includes multiple processing elements coupled to the instruction schedule/dispatch unit to process the data elements of the SIMD instruction in a vector manner, and a power management unit coupled to the instruction schedule/dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.

Abstract: Embodiments are provided for an asynchronous processor with heterogeneous processors. In an embodiment, the apparatus for an asynchronous processor comprises a memory configured to cache instructions, and a first unit (XU) configured to processing a first instruction of the instructions. The apparatus also comprises a second XU having less restricted access than the first XU to a resource of the asynchronous processor and configured to process a second instruction of the instructions. The second instruction requires access to the resource. The apparatus further comprises a feedback engine configured to decode the first instruction and the second instruction, and issue the first instruction to the first XU, and a scheduler configured to send the second instruction to the second XU.

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include system memory, coupled an out-of-order processor via a memory bus.

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.

Abstract: An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.

Abstract: A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.

Abstract: There is provided an electronic device including a manipulation unit configured to acquire manipulation by a user, and a control unit configured to selectively execute one of a plurality of controls of the electronic device which are associated with a duration of the manipulation and to perform switching of at least one of the plurality of controls according to information indicating a state of the electronic device.

Abstract: The present disclosure describes several embodiments, e.g., a method, a baseboard management controller (BMC) system, a computer-readable non-transitory medium, for managing boot images for a computer system. These embodiments may include obtaining, by a BMC of the BMC system, a first boot image for the processor-based system, storing, by the BMC of the BMC system, the first boot image at a first location in a memory element of BMC system, and informing, by the BMC of the BMC system to a bus-to-memory bridge, first location information indicating a first location at which the first boot image is stored. The present disclosure also describes the bus-to-memory bridge which interfaces between a bus of the processor-based system and the memory element of the BMC system to allow one or more processors of the processor-based system to access the memory element of the BMC system to obtain boot image(s).

Abstract: Provided is an information processing apparatus including a decision unit configured to decide an operation mode defining an operation of a target apparatus on the basis of tag information acquired from a tag capable of communicating with an external device, the target apparatus being an apparatus corresponding to the tag information.

Abstract: The present invention relates to a method, system, or computer application that allows to define a product configuration and using this configuration, manage entirely user experience related to this product, and in particular a method in where a rules engine containing directives, logic and constraints controls without the need of human intervention; the content, form and behavior of the user interface on a computational device. All elements and logic contained in the interface can be controlled directly by individual or multiple sets of rules in the rules engine. Rules can be added, edited and operated on by human or machine agents. Any change in the state of the rules is propagated to the user interface automatically and in real time.

Abstract: Provided are a computer program product, system, and method for generating component pages to render in a configuration page in a graphical user interface (GUI) to configure a computing resource. A plurality of component pages are generated to render in the configuration page. Each component page includes user configuration setting controls to enable the user to set configuration parameters for component resources to configure the computer resource. The configuration page is generated to: render a main panel in the GUI program; render graphical component page selection controls in the GUI program associated with the component pages; receive user selection of a selected one of the graphical component page selection controls associated with one of the component pages; and render the component page associated with the selected graphical component page selection control.

Abstract: In various example embodiments, a system and method for transforming instructions for collaborative updates are described herein. A group of instructions for an update of an element depicted in a client device version of a user interface are generated. The group of instructions is executed and the group or a subset of instructions are transmitted to a server. The server accepts or rejects the instructions. The server may execute the instructions to update a server version of the element. The server sends accepted instructions to the other or all client devices.

Abstract: A system for presenting help information relating to a user of a computer program based on context of the computer program is provided. The system receives an indication of a generic request and identifies the context of the computer program at the time of the request. The context may include information that is currently being displayed by the computer program and metadata relating to the user and the computer program. The system selects help information based on the context such that the selected help information varies based on information that is currently being displayed and the metadata. The system then presents the help information to the user.

Abstract: Processes, machines, and manufactures involving adaptable containers that can be built and torn down more efficiently than VMs, may support various processes, and may be maintained without the presence of an active process. These adaptable containers may also be configured to support a process type and may support various processes at the same time as well. Other features and aspects are provided and taught.

Abstract: Approaches are described for collecting and/or utilizing network traffic information, such as network flow data, within a virtualized computing environment. The network traffic information can be collected on one or more host computing devices that host virtual machines. The collected network traffic information can include virtualized computing environment specific information, such as a user account identifier (ID), virtual machine identifier (ID), session termination information and the like. The collected network traffic information can also be presented to the user of the virtualized computing environment.

Abstract: A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may be generated and one or more graph transformations may be applied to the dataflow graph to generate a revised dataflow graph that includes one or more of the deferred parallel data objects and deferred, combined parallel data operations. The deferred, combined parallel operations may be executed to produce materialized parallel data objects corresponding to the deferred parallel data objects.

Abstract: Migrating servers from client networks to virtual machines (VMs) on a provider network. A migration appliance is installed or booted on the client network, and a migration initiator is instantiated on the provider network. A VM and associated volumes are instantiated on the provider network. The initiator sends a request for a boot sector to the appliance; the appliance reads the blocks from a volume on the client network, converts the blocks to a format used by the VM, and sends the blocks to the initiator. The initiator boots the VM using the boot sector and the VM begins execution. The initiator then retrieves all data blocks for the VM from volumes on the client network via the appliance, stores the data to the volumes on the provider network, and fulfills requests from the VM from either local volumes or the remote volumes via the appliance.

Abstract: Techniques and mechanisms provide a flexible mapping for physical functions and virtual functions in an environment including virtual machines.

Abstract: Apparatuses, methods, and program products are disclosed for producing a task reminder on a device. One method includes detecting, by use of a processor, a task to be completed via a user account in an environment that does not enable the task to be completed. The method also includes tagging the task as an incomplete task. The method includes directing information to be stored. The information associates the incomplete task with the user account, and the information is used to produce a reminder to complete the incomplete task.

Abstract: A system and method can support application interoperation in a transactional middleware environment. A first transaction server operates to initiate a global transaction, wherein the first transaction server that is associated with a first format identifier (ID), and wherein the global transaction includes a plurality of branches and each said branch is associated with an individual branch qualifier. Furthermore, the first transaction server can direct at least one branch of the global transaction from the first transaction server to a second transactional server, wherein each said transactional server is associated with a second format identifier (ID), and configure a plurality of branches in the global transaction to share a common format identifier (ID).

Abstract: Technologies for scheduling workload submissions for a graphics processing unit (GPU) in a virtualization environment include a GPU scheduler embodied in a computing device. The virtualization environment includes a number of different virtual machines that are configured with a native graphics driver. The GPU scheduler receives GPU commands from the different virtual machines, dynamically selects a scheduling policy, and schedules the GPU commands for processing by the GPU.

Abstract: An apparatus includes a processor and a guest operating system. In response to receiving a request to create a task, the guest operating system requests a hypervisor to create a virtual processor to execute the requested task. The virtual processor is schedulable on the processor.

Abstract: Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.

Abstract: Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.

Abstract: System and techniques for memory management are described herein. A request for an adjusted process-value for a process may be received. Here, the adjusted process-value may be used to compare resident processes to determine which resident process will be terminated in certain circumstances. In response to the request for the adjusted process-value, a launch-time weight for the process may be obtained. The launch-time weight may be combined with a process-value to create an adjusted process-value. The adjusted process-value may then be returned to the requestor.

Abstract: An adaptive contention-aware thread scheduler may place software threads for pairs of applications on the same socket of a multi-socket machine for execution in parallel. Initial placements may be based on profile data that characterizes the machine and its behavior when multiple applications execute on the same socket. The profile data may be collected during execution of other applications. It may identify performance counters within the cores of the processor sockets whose values are suitable for predicting whether the performance of a pair of applications will suffer when executed together on the same socket (e.g., values indicative of their demands for particular shared resources). During execution, the scheduler may examine the performance counters (or performance metrics derived therefrom) and determine different placement decisions (e.g., placing an application with high demand for resources of one type together with an application with low demand for those resources).

Abstract: A system for verifying resource transfers in real-time typically includes a classical computer apparatus and a quantum optimizer in communication with the classical computer apparatus. The quantum optimizer is configured to analyze resource transfer information related to previous resource transfers to generate a model for verifying resource transfers. Subsequently, when the classical computer apparatus receives a resource transfer request, the classical computer apparatus source transfer request information to the quantum optimizer. The quantum optimizer analyzes the resource transfer request information using the model to determine whether the resource transfer is verified. Based on receiving an indication from the quantum optimizer of whether the resource transfer is verified, the classical computer apparatus processes the resource transfer request.

Abstract: In response to a selection of a program, a board image display control section sets program related information associated with the selected program in a displayable state. An execution start managing section starts the program in response to reception of a request to start the program, the program related information associated with the program being set in the displayable state. A stop and end managing section ends an already started program when a given condition is satisfied at a time of starting the program by the execution start managing section. A setting of program related information associated with the ended program is maintained in a displayable state even after the program is ended by the stop and end managing section.

Abstract: The estimation of a computing capacity of a machine. The computing capacity is estimated by iteratively adding and removing calibrated computer processes on the machine, and performing a sum of computing loads of processes that execute on the machine. In order to characterize the ability of a machine to run in parallel a number of processes having a defined computing load, the processes are associated to a condition of success.

Abstract: An application scaling management method and apparatus are disclosed, so as to perform, in a case in which an application requires capacity expansion and remaining resources of a data center in which the application runs are insufficient, capacity expansion of the application by utilizing remaining resources of another data center, thereby improving resource utilization and capacity expansion efficiency.

Abstract: A method for migrating network entities to a cloud computing infrastructure includes receiving an indication of at least one node of a plurality of nodes to migrate from an enterprise network to a cloud computing infrastructure, identifying one or more related nodes of the plurality of nodes that have direct and indirect communication relationships with the indicated node, and adding the indicated node and at least one node of the related nodes for the indicated node to a migration group.

Abstract: A cloud services brokerage platform system includes a virtual data center (VDC) and an architecture management interface. The virtual data center (VDC) includes a plurality of resource groups. Each one of the resource groups includes one or more VDC resources. Each one of the VDC resources is associated with a respective set of resource group specification parameters. The architecture management interface enables an architectural layout of the one or more VDC resources to be displayed. The architectural layout includes a visual depiction of the one or more VDC resources of each one of the resource groups. An arrangement of the visual depiction is dependent upon the respective set of resource group specification parameters.

Abstract: A method includes creating a file directory entry in a directory file of a secure hierarchical file directory system for a file. The file directory entry includes a path name, an encryption access control list, and a source name. The file is encrypted with a key and the key is encrypted with each public key of user devices authorized to access the file. The encryption access control list includes identities of the set of user devices and the set of object content keys. The method further includes encrypting the directory file using a second key. The method further includes generating second object content keys based on the second key and public keys of second user devices authorized to access the directory file. The method further includes creating a next level directory file entry in a next higher directory file of the secure hierarchical file directory system for the directory file.

Abstract: A temperature-aware task scheduling method, system, and computer program product, includes the GPU, receiving a request to execute the task, collecting task information including an intensiveness factor of a computation by an arithmetic logic unit (ALU) and a memory usage of a dynamic random-access memory (DRAM) for the task, obtaining a temperature of the ALU and a temperature of the DRAM, and accepting the task to the GPU based on the intensiveness factor, the ALU temperature, and the DRAM temperature.

Abstract: A system and method for communicating data between a first software and a second software located on first and second devices, respectively, has a hardware driver and memory associated with each device. Each communication of data from the first software to the second software allocates memory to manage data to be communicated from the first software to the second software, provides memory allocation information to the hardware driver associated with the first software, and transmits the data from the first hardware driver to the second hardware driver for delivery to the second software via the memory associated with the second software.

Abstract: Devices and systems supporting more than one Virtual Assistant (VA) are able to initiate and collaborate with multiple virtual assistants within the same session and at the same time. This system allows application specific virtual assistants to register and listen for intents from a general purpose virtual assistant. When the general purpose virtual assistant raises an intent, control can be passed to an interested application specific virtual assistant for handling. The system of registering new intents increases the knowledge of the general purpose virtual assistant, or overloads the handling of an existing intent.

Abstract: A digital assistant includes an extensibility client that interfaces with application extensions that are built by third-party developers so that various aspects of application user experiences, content, or features may be integrated into the digital assistant and rendered as native digital assistant experiences. Application extensions can use a variety of services provided from cloud-based and/or local sources such as language/vocabulary, user preferences, and context services that add intelligence and contextual relevance while enabling the extensions to plug in and operate seamlessly within the digital assistant context. Application extensions may also access and utilize general digital assistant functions, data structures, and libraries exposed by the services and implement application domain-specific context and behaviors using the programming features captured in the extension.

Abstract: Operational event loggings and operational alarm productions within a running multiserver data processing system are automatically and repeatedly sampled and co-associated with one another so as to build annotated logs that can be used by post-process analytics for filling in mappings thereof into an anomalies versus parameters mapping space and for keeping track of unusual changes in the mappings or their rates where the unusual changes can be indicative of emerging new problems of significance within the system.

Abstract: Serving resources. A method includes receiving from a client, a request for one or more operations to be performed. The method further includes attempting to perform the one or more operations. The method further includes determining that the one or more operations are not complete at a present time. As a result, the method further includes sending a message to the client indicating that the client should attempt to obtain status information for the one or more operations at a predetermined later time. The method further includes receiving a request from the client for status information about the one or more operations. The method further includes repeating sending a message to the client and receiving a request from the client for status information.

Abstract: There is provided a distributed object storage system that includes several performance optimizations with respect to efficiently storing data objects when coping with a desired concurrent failure tolerance of concurrent failures of storage elements which is greater than two and with respect to optimizing encoding/decoding overhead and the number of input and output operations at the level of the storage elements.

Abstract: Examples include a system comprising a non-volatile memory, a cluster management interface, and a multi-node cluster. In some examples, the cluster management interface may monitor a system critical alert to determine if the system critical alert has been triggered. Based on the determination that it has been triggered, the cluster management interface may multicast a system failure notification. The multi-node cluster of the system has multiple nodes, each node connected to the non-volatile memory and having a processor and a processor cache. Each node of the multi-node cluster may determine if the system failure notification has been received and based on the determination that it has been received, each node may freeze execution of all processes on the process and flush the processor cache to the non-volatile memory.

Abstract: Various embodiments for retaining diagnostic information for data in a computing storage environment. In one such embodiment, a diagnostic component, apart from a volume table of contents (VTOC), associated with an integrated catalog facility (ICF) catalog and with a base data set from data sets via a catalog association record, is initialized. The diagnostic component is configured to retain base data set-specific diagnostic information retrievable by the computing storage environment to assist in error diagnosis. The base data set-specific diagnostic information is stored pursuant to at least one detected event associated with the base data set.

Abstract: Systems for self-configuring health monitoring instrumentation for clustered storage platforms. Master and slave health modules implement a health monitoring system in a clustered virtualization environment comprising a plurality of nodes of the cluster with an installed health module instance running on the nodes. The health module system may gather and analyze data on a node level and at a cluster level to manage the cluster. The cluster health module system observes I/O commands issued to, and I/O command responses returned from, a common storage pool. Health data is stored in the storage pool.

Abstract: A processor includes physical storage locations, and a register rename unit that includes a plurality of register rename storage structures. At a given time, each of a complete group of physical storage location identifiers is to be stored in one, but only one, of the plurality of register rename storage structures, unless there is an error. Each of the complete group of physical storage location identifiers is to identify a different one of the physical storage locations. The register rename unit is to detect an error when a first value, which is to be equal to an operation on the complete group of the physical storage location identifiers with no errors, is inconsistent with a second value. The second value is to represent the operation on all physical storage location identifiers that are to be stored in the plurality of register rename storage structures at the given time.

Abstract: Disclosed are data gathering and analysis systems, methods, and computer-readable storage media to facilitate an investigation process. The method includes accessing a data object representing an investigative issue. The method further includes causing presentation, on a display of a device, of a user interface configured to receive user search queries and present search results for each received search query. The method further includes tracking user activity including one or more user actions performed as part of an investigation of the investigatory issue, the one or more user actions including user interactions with the user interface. The method further includes creating a record of the user activity involving the investigatory issue, and linking the record of the user activity with the data object representing the investigative issue.