Patents Issued in November 20, 2018
  • Patent number: 10133622
    Abstract: Disclosed herein are systems, methods, and software for enhancing error detection in data synchronization operations. In an implementation, log data reported by a device is received and incorporated into an event database indicating interleaved events related to data synchronization threads on the device. The event database is queried to extract a listing of events in the event database, the listing of events comprising events potentially associated with at least one error condition in the data synchronization threads. The listing of events is processed to identify one or more patterns from among the interleaved events that indicate the at least one error condition in the data synchronization threads. Responsive to identifying the one or more patterns, an indication of the at least one error condition in the data synchronization threads is communicated.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: November 20, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jack Allen Nichols, Ryan Gordon Zacher, György Keresztély Schadt, Rayyan Jaber, Erik Hampton Soderberg
  • Patent number: 10133623
    Abstract: Systems (100) and methods are provided for obtaining process model which comprises of process maps, wherein process maps comprises of process levels and sub levels, which are configured with key metrics and corresponding time stamp to monitor health of process model. During execution of process model and therein the process levels, configured key metrics are monitored and compared with the pre-defined threshold value. Any increase in the key metrics beyond threshold limit, one or more events are determined, which are analyzed and based on the time stamp of the events, process levels and sub levels are identified and rectified. In one of the embodiment, system (100) enables replay process to replay process model for problem determination purpose. In the replay process, system (100) enables viewing of obtained process model wherein process definition and data with time stamp is in XML format for every step which is recorded in the past.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: November 20, 2018
    Assignee: Tata Consultancy Services Limited
    Inventors: Soumya Chatterjee, Sanjib Palchaudhuri, Indranil Mutsuddi, Debabrata Mondal
  • Patent number: 10133624
    Abstract: Disclosed are a fault-localization and error-correction method for a self-checking binary signed-digit adder and a digital logic circuit for performing the method. More specifically, a fault-localization and error-correction method for a self-checking binary signed-digit adder in which a stuck-at fault of the self-checking binary signed-digit adder may be detected at low cost and with low complexity and in which an error may be autonomously corrected using the self-dual concept, and a digital logic circuit for performing the method are disclosed.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: November 20, 2018
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION CHOSUN UNIVERSITY
    Inventors: Jeong A Lee, Hossein Moradian
  • Patent number: 10133625
    Abstract: A storage device may include a primary storage array comprising a plurality of memory devices, one or more parity memory devices, and a controller configured to store a block of data. The controller may be configured to store the block of data by at least: writing the block of data to the primary storage array, determining parity data for the block of data, and writing at least a portion of the determined parity data to the one or more parity memory devices.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: November 20, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zvonimir Z. Bandic, Robert E. Mateescu, Seung-Hwan Song
  • Patent number: 10133626
    Abstract: A method is proposed for storing bits in memory cells of a memory, wherein in two successive write operations first and second wits are written to identical memory cells at an identical address, without the memory cells being erased after the first write operation, wherein first check bits are stored in further first memory cells and second check bits are stored in further second memory cells. A corresponding device is furthermore specified.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Michael Goessel
  • Patent number: 10133627
    Abstract: A controller includes a command generation unit suitable for generating a first read command for at least one page selected from said plurality of pages, an error correction block suitable for performing a first error correction operation to one or more code words stored in said at least one selected page in response to the first read command, and a command mirroring unit suitable for generating a mirrored command by mirroring the first read command.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: November 20, 2018
    Assignee: SK Hynix Inc.
    Inventors: Young Dong Roh, Se Chun Park
  • Patent number: 10133628
    Abstract: The present disclosure relates to apparatuses and method for encoding using error protection codes. An example apparatus comprises circuitry, for instance, including an encoder configured to compute parity data based, at least in part, on program data and on predetermined coefficient data. The predetermined coefficient data is determined independent of the program data.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: November 20, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Stephen P. Van Aken
  • Patent number: 10133629
    Abstract: The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: November 20, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Ashwin Narasimha, Kenneth Alan Okin
  • Patent number: 10133630
    Abstract: A method for recovering a failed storage drive in a redundant array of independent disks (RAID) includes storing, on a first distributed spare of the RAID, a first parity subset for a first set of drives in the RAID. The method further stores, on a second distributed spare of the RAID, a second parity subset for a second set of drives in the RAID. In the event a storage drive in the RAID fails, the method determines whether the storage drive belongs to the first set or second set. In the event the failed storage drive belongs to the first set, the method uses the first parity subset on the first set of drives in the RAID to recover the failed storage drive. In the event the failed storage drive belongs to the second set, the method uses the second parity subset on the second set of drives in the RAID to recover the failed storage drive. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: John P. Agombar, Ian Boden, Alastair Cooper, Gordon D. Hutchison
  • Patent number: 10133631
    Abstract: A method includes identifying an encoded slice for rebuilding. The method further includes determining whether the set of encoded slices is stored in an encrypted section of a vault or within an unencrypted section of the vault. The method further includes, when the set of encoded slices is stored in the unencrypted section of the vault, determining whether the set of storage units have viewing rights. The method further includes, when the set of storage units does not have the viewing rights, enabling a restricted rebuilding process to rebuild the encoded slice. The method further includes, when the set or storage units does have the viewing rights, enable an unrestricted rebuilding process to rebuild the encoded slice.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Greg R. Dhuse, Wesley B. Leggette, Jason K. Resch, Trevor J. Vossberg
  • Patent number: 10133632
    Abstract: A method for determining completion of a data migration that results from a distributed agreement protocol (DAP) change within a distributed storage network (DSN). The method begins by transferring, in accordance with the DAP change, encoded data slices to one or more other storage units within the DSN. The method continues by maintaining a storage unit migration tracking repository that tracks migration of the encoded data slices. The method continues by maintaining a storage pool migration tracking repository based on the storage unit migration tracking repositories of the plurality of storage units. The method continues by maintaining a DSN migration tracking repository based on the storage pool migration tracking repositories of the plurality of storage pools. The method continues by indicating completion of the data migration as a result of the DAP change based on information within the DSN tracking repository.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Wesley B. Leggette, Manish Motwani, Jason K. Resch
  • Patent number: 10133633
    Abstract: A data storage method is used to improve storage consistency of a distributed storage system. The method includes: a primary storage node performs EC coding on a to-be-stored data segment to obtain a target EC stripe; determines in a storage node group to which the primary storage node belongs, m+k target storage nodes used to store m+k target EC blocks of the target EC stripe; sends a preparation message to the target storage nodes; receives a response message sent by a target storage node; and sends an execution message to the target storage nodes to instruct the target storage nodes to write target EC blocks that are in preparation logs.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: November 20, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Daohui Wang, Feng Zhang, Wei Fan, Zhile Zhang, Yongqiang Zeng
  • Patent number: 10133634
    Abstract: A method begins by processing modules in a dispersed storage network (DSN) identifying a memory device having a legacy slice storage format (SSF) to a second SSF and that includes a first encoded data slice (EDS) of a set of EDSs. When at least a predetermined threshold number of EDSs of the set of EDSs are included within one or storage units (SUs) excluding the first EDS the method continues by transitioning the first SSF of the memory device to the second SSF, and performing a rebuilding process using the at least the decode threshold number of EDSs of the set of EDSs to generate a rebuilt first EDS. The method continues by storing the rebuilt first EDS within the memory device to replace the first EDS that was deleted during the transitioning.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Manish Motwani
  • Patent number: 10133635
    Abstract: A method includes storing a first set of data slices in a standard-width vault using a first group of DS units of a distributed storage network (DSN). The first set of data slices corresponds to a first representation of a data object, and includes a first write-threshold number of data slices encoded using a first set of dispersal parameters specifying first write and read widths associated with the standard-width vault. A second set of data slices, corresponding to a second representation of the data object, is stored in a low-width vault using a second group of DS units. The second set of data slices includes at least a second write-threshold number of data slices encoded using a second set of dispersal parameters specifying second write and read widths associated with the low-width vault. The low-width vault has a lower width read and/or write width than the standard-width vault.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ahmad Alnafoosi, Andrew D. Baptist, Wesley B. Leggette, Jason K. Resch
  • Patent number: 10133636
    Abstract: Through use of a mediator, one can translate and efficiently store data. The meditator may link one or more hosts to one or more storage devices. Optionally, the meditator may convert data and decode data. Through the use of meditator, one can realize certain economies because fewer units within recording media will be used. Additionally, in some embodiments, the mediator will also allow increased protection against unauthorized access and additionally or alternatively allow for efficient backing-up of data.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 20, 2018
    Assignee: FORMULUS BLACK CORPORATION
    Inventor: Brian Ignomirello
  • Patent number: 10133637
    Abstract: A management controller may be configured to control connectivity among a host system processor, a primary ROM, and a recovery ROM in accordance with a plurality of modes of operation including at least a normal mode that occurs in response to absence of a corruption of the ROM code in which the management controller causes the host system processor to be communicatively coupled to the primary ROM and communicatively decoupled from the recovery ROM, such that the host system processor loads and executes the ROM code during boot of the host system, and a primary ROM recovery mode that occurs in response to presence of the corruption of the ROM code in which the management controller causes the host system processor to be coupled to the primary ROM and the recovery ROM, such that the host system processor loads and executes the recovery code during boot of the host system.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: November 20, 2018
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Johan Rahardjo, Mukund P. Khatri
  • Patent number: 10133638
    Abstract: Recovery of an in-memory state in a log-structured filesystem using fuzzy checkpoints is disclosed, including: determining a portion of a data structure to checkpoint to a storage unit, wherein the structure is associated with a set of references to locations in persistent storage at which metadata is stored, wherein the portion of the data structure is dynamically determined based at least in part on a size of the data structure and a predetermined number of storage units to be associated with a checkpoint window, wherein the number of storage units to be associated with the checkpoint window is fewer than a total number of storage units associated with the persistent storage; and checkpointing the portion of the data structure to the storage unit.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: November 20, 2018
    Assignee: Tintri Inc.
    Inventors: Sumedh V. Sakdeo, Brandon W. Salmon, Olivier F. Lecomte, Marco J. Zagha
  • Patent number: 10133639
    Abstract: Backing up electronic data files excluding confidential data. An electronic trigger event for initiating a data backup operation is detected. Data files are identified for backup. One or more files, or parts of a file, are designated for exclusion from the backup process. The backup process initiates a backup operation of one or more files, excluding the designated files.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Muhtar B. Akbulut, Mario A. Maldari, David D. Taieb
  • Patent number: 10133640
    Abstract: A storage apparatus includes a first storage device and a processor. The first storage device is configured to store therein first information blocks used to recover second information blocks stored in a second storage device. The processor is configured to read the first information blocks from the first storage device in an order of addresses of storage areas of the first storage device. The processor is configured to output part of the first information blocks which have been read from the first storage device to respective recovery destinations of the second information blocks to recover the second information blocks step by step.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: November 20, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Kensuke Shiozawa
  • Patent number: 10133641
    Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
  • Patent number: 10133642
    Abstract: Techniques for operating a computing system to facilitate visualization of a backup environment are disclosed. In one particular embodiment, the techniques may be realized as a method of operating a computing system to facilitate visualization of a backup environment. The method may comprise performing a backup service for an organization and rendering a graphical user interface that presents a plurality of views of the backup environment for the organization on a sub-organizational basis.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: November 20, 2018
    Assignee: Cobalt Iron, Inc.
    Inventors: Richard R. Spurlock, Robert M. Marett, J. Mitchell Haile
  • Patent number: 10133643
    Abstract: Provided are a computer program product, system, and method for performing a failover between a first storage system and a second storage system. Data is synchronized between the first storage system and the second storage system. A failover is performed from the first storage system to the second storage system in response to a failover event at the first storage system while synchronizing the data. A determination is made that a first storage unit of the first storage system is inoperable and that that a second storage unit of the first storage system is operable in response to the failover event. In response to determining that the second storage unit is operable, a resynchronization is initiated to copy updates to a second storage unit of the second storage system mirroring the second storage unit of the first storage system to the second storage unit of the first storage system.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Brandner, Michael Frankenberg, Alan G. McClure, David B. Petersen, Daniel Roman, Gail A. Spear, John G. Thompson
  • Patent number: 10133644
    Abstract: A method and system permit a backup entity of a redundant apparatus of a communication system that shares control of hardware resources or other network resources with an active entity to indirectly determine a status of the active entity based upon behavior and reaction to actions it takes in connection with resources it shares control of with the active entity. Such a method and system permit the backup entity to deduce the state of the active entity without having any a hardware connection or other communication connection with the active entity.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: November 20, 2018
    Assignee: Unify GmbH & Co. KG
    Inventors: Rodrigo Biermayr, Evandro Hauenstein, David Wiebe, Thomas Nagel
  • Patent number: 10133645
    Abstract: Data is programmed in a respective block of non-volatile three dimensional memory. The block contains a plurality of rows of subblocks, each row having S subblocks. Programming data in the respective block includes successively programming data in individual rows of the respective block. Programming data in each row is completed prior to programming data in a next row. Programming data in a row includes successively programming data in individual subblocks of the row, in a predefined order. The programming of data in each subblock is completed prior to programming data in a next subblock. While programming data in each individual subblock, a number of XOR signatures, sufficient in number to enable recovery from a short circuit that disables two or three word lines, are generated in volatile memory, and then copied to non-volatile memory prior to programming data in a next subblock in the respective block.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: November 20, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Ofer Shapira, Idan Alrod, Eran Sharon
  • Patent number: 10133646
    Abstract: A method for providing fault tolerance in a distributed file system of a service provider may include launching at least one data storage node on at least a first virtual machine instance (VMI) running on one or more servers of the service provider and storing file data. At least one data management node may be launched on at least a second VMI running on the one or more servers of the service provider. The at least second VMI may be associated with a dedicated IP address and the at least one data management node may store metadata information associated with the file data in a network storage attached to the at least second VMI. Upon detecting a failure of the at least second VMI, the at least one data management node may be re-launched on at least a third VMI running on the one or more servers.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: November 20, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Rejith George Joseph, Tin-Yu Lee, Bandish N. Chheda, Scott Michael Le Grand, Saurabh Dileep Baji
  • Patent number: 10133647
    Abstract: A method of operating a computer system in an operating system test mode. The computer system comprises a processor system, a physical memory system, and a secondary storage memory system. In response to a request to access a memory address, it is determined if the memory page associated with the memory address is available in the physical memory system, and if the memory page associated with the memory address is not pinned in the virtual memory area. In response to the memory page being available in the physical memory system but not pinned in the virtual memory area, an interrupt is generated.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventor: Jose Pina Coelho
  • Patent number: 10133648
    Abstract: A power allocation system includes a manager provided on a network controller. An agent is provided on a line module coupled to the network controller. The agent is operable to detect a connection of a powered device to a port on the line module and communicate that to the manager. The manager then classifies the powered device and provides a first power to the powered device through the port from a global power budget according to the classification. At least one of the manager and agent then monitor the power consumption of the powered device subsequent to providing the first power, and a second power is provided to the powered device through the port from the global power budget according to the monitoring, wherein the second power is different from the first power.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: November 20, 2018
    Assignee: Dell Products L.P.
    Inventors: Rabah S. Hamdi, Saikrishna M. Kotha
  • Patent number: 10133649
    Abstract: Systems and methods for software verification. In some embodiments, an application architecture model is generated for a software application, wherein: the application architecture model is generated based on source code of the software application and a framework model representing a software framework using which the software application is developed; and the application architecture model comprises a plurality of component models. One or more component models may be selected, based on a property to be checked, from the plurality of component models. The one or more component models may be analyzed to determine if the property is satisfied.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 20, 2018
    Assignee: Synopsys, Inc.
    Inventors: Guodong Li, John Steven
  • Patent number: 10133650
    Abstract: A method for automated application programming interface (API) validation includes extracting API information from an API repository. The API information is used to generate a test case for the automated API validation. The API information may include a parameter placeholder, parameter information related to a parameter of an API endpoint, an API endpoint of the API, an endpoint description, a description of the API, a description of the parameter, response information, an authentication requirement information, and an API name. The method includes resolving the parameter of the API endpoint. The method includes communicating to a native API system a request using the sample parameter value for the parameter. The method includes comparing a response from the native API system with the response information to validate the API. The method includes verifying integrity of a software application implementing the API endpoint for use with a native software application.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: November 20, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Junhee Park, Mehdi Bahrami, Wei-Peng Chen
  • Patent number: 10133651
    Abstract: A software defect detection tool determines a modification in a software code at a first time and analyzes an execution of the software code to detect a performance issue at a second time. The software defect detection tool detects a defect in the software code by a comparison of the first time and a second time. A software defect analysis tool generates a cause/category combination for a software code defect. The software defect analysis tool determines whether the cause/category combination is an approved combination and whether the software code defect is a false positive. The software defect analysis tool generates a corrective action plan indicating measures to implement to reduce software defects.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: November 20, 2018
    Assignee: Bank of America Corporation
    Inventors: Samson Paulraj, Chandrashekhar Radhakrishnan, Jyothi Lloyd Leslie, Mudit Chawla, Mahendran Vella Pandian
  • Patent number: 10133652
    Abstract: Embodiments of the present invention provide a method, computer program product, and system for debugging optimized code. The system includes a FAT binary, wherein the FAT binary comprises a non-optimized native code and an internal representation of a program's source code. An optimus program is configured to transform the internal representation of the program's source code into a fully optimized native code. The system also includes an enhanced loader, wherein the enhanced loader is configured to communicate with a debugger to determine a type of code to load.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Moniz, Ali I. Sheikh, Diana P. Sutandie, Srivatsan Vijayakumar, Ying Di Zhang
  • Patent number: 10133653
    Abstract: Recording and playback of trace log data and video log data for programs is described. In one aspect, a method for viewing log data recorded during execution of a program includes causing a display of recorded images depicting prior visual user interaction with the program during a particular time period. The method also includes causing a display of messages tracing and describing prior execution of the program during the particular time period. The display of the messages and the display of the recorded images are synchronized.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: November 20, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, David Varghese
  • Patent number: 10133654
    Abstract: A method for firmware debug trace capture includes creating a hand-off block (“HOB”), capturing first debug trace statements during a boot sequence of a computer and writing the first debug trace statements to the HOB. A trace memory buffer can be created and the first debug trace statements can be copied from the HOB to the trace memory buffer. Second debug trace statements are captured during the boot sequence and appended to the trace memory buffer. In some configurations, the first debug trace statements can be written to the HOB during the pre-Extensible Firmware Interface initialization (“PEI”) phase of the boot sequence and the second debug trace statements can be written to the trace memory buffer during the driver execution (“DXE”) phase of the boot sequence.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: November 20, 2018
    Assignee: American Megatrends, Inc.
    Inventors: Michael Harry Deiderich, III, Matthew Hoffmann, Thomas Gilreath
  • Patent number: 10133655
    Abstract: An emulator handles problematic target code blocks by evaluating target system code for problematic target code blocks and bypassing translation of such blocks, in some cases selecting alternative host code for a problematic block. Non-problematic portions of the target system code are translated into corresponding portions of host system code, which are inserted into an execution stream. Alternative host system code may also be inserted into the execution stream.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: November 20, 2018
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Geoffrey Piers Robert Norton, Jacob P. Stine, Takayuki Kazama, Dmitri Tolstov
  • Patent number: 10133656
    Abstract: This disclosure relates to systems and methods for generating covering arrays. By processing parameters and corresponding values pertaining to an application under test (AUT), the system generates a first set of arrays, wherein elements in the first set are unique from each other. A second set of arrays is generated by identifying two or more arrays from the first set. Each array in the second set may include pairwise interacting elements that are unique to each other. A third set of arrays is formed by interchanging pairwise interacting elements across the second set of arrays. Unique pairwise interacting elements are interchanged across set of arrays to eliminate from duplicating pairwise interacting elements. Combining two or more arrays from the third set of arrays results in an optimized covering array, which is then used for generating optimized test designs for at least one AUT.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: November 20, 2018
    Assignee: Tata Consultancy Services Limited
    Inventor: Sukumar Sundaram
  • Patent number: 10133657
    Abstract: According to an aspect of an embodiment, a method may include identifying a fault at a fault location in a software program using a test suite. The method may also include determining multiple textual similarity scores by determining a textual similarity score with respect to each of multiple repair candidates for the fault. In addition, the method may include sorting the repair candidates based on the textual similarity scores. The method may also include selecting a particular repair candidate from the repair candidates based on the sorting. Moreover, the method may include implementing the particular repair candidate at the fault location based on the selection of the particular repair candidate.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: November 20, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Hiroaki Yoshida, Ripon Kumar Saha, Mukul R. Prasad
  • Patent number: 10133658
    Abstract: Methods, systems, apparatus, including computer programs encoded on computer storage media, for reclaiming storage space in a storage environment. In one aspect, the method includes actions of aggregating data that is indicative of access to one or more data objects, determining a future storage cost associated with each of a plurality of data objects, determining an access window for each of the plurality of data objects, identifying a data object based on (i) the future storage cost that satisfies a predetermined threshold and (ii) a data object access window, providing a notification to a user device that requests feedback from a user indicating whether the data object can be deleted, and in response to receiving data that indicates that the data object can be deleted, generating an instruction to cause deletion of the data object upon the expiration of the access window.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: November 20, 2018
    Assignee: Google LLC
    Inventors: Konstantinos Nikoloudakis, Sven Koehler, Danyao Wang, Sahand Saba, Long Fei, Simon Tyler Wise, David Halladay Schneider
  • Patent number: 10133659
    Abstract: Technologies are described for performing proactive memory allocation (e.g., pre-allocation). Proactive memory allocation (e.g., proactive memory page allocation) can be provided for applications, such as database applications. For example, an application can be associated with a free memory pool (e.g., a free memory pool containing free memory pages). A dedicated thread of the application can monitor the free memory pool and perform proactive memory allocation when needed (e.g., when the amount of memory in the pool is low). For example, the dedicated thread can obtain new free memory from the operating system and add it to the pool.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: November 20, 2018
    Assignee: SAP SE
    Inventors: Hyeong Seog Kim, Jaeyun Noh, Yong Sik Kwon, Sang Kyun Cha
  • Patent number: 10133660
    Abstract: Dynamically allocated thread storage in a computing device is disclosed. The dynamically allocated thread storage is configured to work with a process including two or more threads. Each thread includes a statically allocated thread-local slot configured to store a table. Each table is configured to include a table slot corresponding with a dynamically allocated thread-local value. A dynamically allocated thread-local instance corresponds with the table slot.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: November 20, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Igor Ostrovsky, Joseph E. Hoag, Stephen H. Toub, Mike Liddell
  • Patent number: 10133661
    Abstract: Disclosed herein are system, method, and computer program product embodiments for adaptively self-tuning a bucket memory manager. An embodiment operates by receiving requests for memory blocks of varying memory sizes from a client. Determining a workload for the client based on the requests. Analyzing buckets in the bucket memory manager based on the workload. Adjusting parameters associated with the bucket memory manager based on the analyzing to accommodate the requests.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 20, 2018
    Assignee: SAP SE
    Inventor: Tony Imbierski
  • Patent number: 10133662
    Abstract: A storage controller is configured to implement an atomic storage operation comprising a plurality of separate storage operations on a non-volatile storage medium. The storage controller may store persistent indicators to identify data that pertains to the atomic storage operation. An invalid shutdown may occur before the atomic storage operation is complete. A restart and recovery operation comprises a first scan of the non-volatile storage medium to identify data of the failed atomic storage operation. A physical trim note is stored on the non-volatile storage medium to identify the data of the failed atomic storage operation. The data may be identified by media address. Storage metadata is reconstructed in a second scan, which excludes the data and/or operations of the failed atomic storage operation.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: November 20, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James G. Peterson, Ashish Batwara, Nisha Talagala, Michael Zappe
  • Patent number: 10133663
    Abstract: Data is stored on a non-volatile storage media in a sequential, log-based format. The formatted data defines an ordered sequence of storage operations performed on the non-volatile storage media. A storage layer maintains volatile metadata, which may include a forward index associating logical identifiers with respective physical storage units on the non-volatile storage media. The volatile metadata may be reconstructed from the ordered sequence of storage operations. Persistent notes may be used to maintain consistency between the volatile metadata and the contents of the non-volatile storage media. Persistent notes may identify data that does not need to be retained on the non-volatile storage media and/or is no longer valid.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: November 20, 2018
    Assignee: Longitude Enterprise Flash S.A.R.L.
    Inventors: David Atkisson, David Nellans, David Flynn, Jens Axboe, Michael Zappe
  • Patent number: 10133664
    Abstract: A method for accessing a flash memory module is provide. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of the flash memory chips; and allocating a buffer memory space to store a plurality of temporary parities generated when data is written into the at least one first super block.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: November 20, 2018
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 10133665
    Abstract: A method of operating a data storage device includes programming non-fully programmed memory blocks at a point in time when a reference time elapses from a point in time when each of the memory blocks is physically erased, acquiring a first interval and a second interval, calculating a disturb index based on the first interval and the second interval, selecting a victim block for garbage collection based on the disturb index, and copying valid page data of the victim block into a free block. The first interval is defined by a point in time when each of the memory blocks is physically erased and a point in time when each of the memory blocks is fully programmed. The second interval is an interval during which a fully programmed state is maintained after a point in time when each of the memory blocks is fully programmed.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangkwon Moon, Seung-Yeon Lee, Heewon Lee, In Hwan Doh, NamWook Kang
  • Patent number: 10133666
    Abstract: A file storage method includes: splitting each of multiple files into one or more file block objects with different sizes; and writing the file block objects obtained from file splitting into corresponding large object storage files, wherein a preset number of large object storage files are pre-created in a storage apparatus, and storage spaces occupied by the preset number of large object storage files in the storage apparatus are continuous.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: November 20, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mingchang Wei, Wei Zhang
  • Patent number: 10133667
    Abstract: Techniques related to efficient data storage and retrieval using a heterogeneous main memory are disclosed. A database includes a set of persistent format (PF) data that is stored on persistent storage in a persistent format. The database is maintained on the persistent storage and is accessible to a database server. The database server converts the set of PF data to sets of mirror format (MF) data and stores the MF data in a hierarchy of random-access memories (RAMs). Each RAM in the hierarchy has an associated latency that is different from a latency associated with any other RAM in the hierarchy. Storing the sets of MF data in the hierarchy of RAMs includes (1) selecting, based on one or more criteria, a respective RAM in the hierarchy to store each set of MF data and (2) storing said each set of MF data in the respective RAM.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: November 20, 2018
    Assignee: Orcle International Corporation
    Inventors: Niloy Mukherjee, Tirthankar Lahiri, Juan R. Loaiza, Jesse Kamp, Prashant Gaharwar, Hariharan Lakshmanan, Dhruvil Shah
  • Patent number: 10133668
    Abstract: Technologies for providing cross data storage device communication include a compute device to transmit, with a processor, a move request to a first data storage device. The first data storage device is to transmit, in response to the move request, a completion notification to the processor. Additionally, the compute device is to read, with the first data storage device, after transmitting the completion notification, a block of data from a first non-volatile memory of the first data storage device to a volatile memory of the compute device. The first data storage device is to transmit to the second data storage device a second move request to move the block of data. The second data storage device is to write the block of data from the volatile memory to a second non-volatile memory of the second data storage device.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventor: Anand S. Ramalingam
  • Patent number: 10133669
    Abstract: An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache and store a first data set at a first location in the cache and receive a first request from an application to write a second data set to the cache. The predictor circuit may be coupled to the processor and determine that a second location where the second data set is to be written to in the cache is nonconsecutive to the first location, where the processor is to perform a request-for-ownership (RFO) operation for the second data set and write the second data set to the cache.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Pavel I. Kryukov, Stanislav Shwartsman, Joseph Nuzman, Alexandr Titov
  • Patent number: 10133670
    Abstract: In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Ramadass Nagarajan, Jose S. Niell, Michael T. Klinglesmith, Derek T. Bachand, Ganesh Kumar
  • Patent number: 10133671
    Abstract: A system and method are disclosed that include a bridge that translates non-coherent transactions, which are received from a non-coherent subsystem, into one or more coherent transactions to be issued to a coherent subsystem. The bridge also buffers data coherently in an internal cache, also known as a proxy cache, based on certain attributes of the non-coherent transaction. The invention may be applied to any cache, which receives read and write transactions that become coherent transactions.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: November 20, 2018
    Assignee: ARTERIS, Inc.
    Inventors: David A Kruckemyer, Craig Stephen Forrest