Abstract: Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage system is provided that includes a first processor configured to establish a network connection with an external system, and receive first storage operations transferred by the external system over the network connection, the first storage operations related to storage and retrieval of data on at least one storage drive. The first processor is configured to transfer information describing the network connection for delivery to at least a second processor. The second processor is configured to identify when the first processor has failed, responsively establish the network connection with the external system based at least on the information describing the network connection, and receive second storage operations transferred by the external system over the network connection.

Abstract: Systems and methods for monitoring hardware observation points within a System on a Chip (SoC) are disclosed. In one embodiment, a monitoring system includes observers electrically coupled to corresponding hardware observation points. For each observation time period, the observer receives events from a corresponding hardware observation point and outputs observation data indicative of the number of events received. Each observer operates in the same clock and power domain as the corresponding hardware observation point. The hardware monitoring system includes collectors; each collector receives the observation data from a corresponding observer for the observation time period(s). Each collector updates a value of a live-counter based on the observation data and outputs the value of the live-counter. By counting the number of events at the hardware observation points, the monitoring system can enable detailed runtime monitoring, which can be used, e.g.

Abstract: The present disclosure involves systems, software, and computer implemented methods for monitoring processes running on a platform as a service architecture. One example method includes storing a received sample of monitored attributes of a computer process in a sample memory buffer that includes other stored samples. A determination is made that the sample memory buffer is full. The sample memory buffer is compressed. A starting position in a compressed sample file store at which to store the compressed sample memory buffer is determined. The compressed sample memory buffer is stored at the determined starting position in the compressed sample file store. The starting position of the stored compressed sample memory buffer is stored at a particular location in a file position index. A collection timestamp for the sample in a timestamp index is stored at a timestamp index location that matches the particular location in the file position index.

Abstract: An evaluation system includes a process execution module that executes an operation in accordance with a safety program, a setting module that receives an evaluation condition, a first determination module that changes the value of the input signal to be evaluated, from a first input value which is an initial value to a second input value, and determines whether a first output value of the output signal to be evaluated which is determined by the process execution module is identical to the expected output value, a second determination module that restores the value of the input signal to be evaluated, from the second input value to the first input value, and determines whether a second output value of the output signal to be evaluated which is determined by the process execution module is identical to the first output value, and an output module that outputs a determination result.

Abstract: A developer analytic module executing on an integrated development environment provides location tracing of a software development toolkit and automatic updated of the SDK. The developer analytic module further provides data container transfer functionality to ensure that analytic logic has access to necessary data containers to perform symbolication and/or error detection.

Abstract: Techniques for identifying a stack frame responsible for resource usage are described. For instance, techniques described herein enable a particular process and a particular stack frame and/or set of stack frames of the process that are high resource consumers to be identified. According to various implementations, resource usage of a process is observed and recorded over a period of time. A data structure is generated that characterizes the resource usage of the process over the sampling period. The data structure be evaluated to identify a stack frame that is responsible for excess resource consumption. In at least some implementations, a remedial procedure can be performed to attempt to reduce the process's resource usage.

Abstract: Mechanisms are provided for propagating source identification information from an application front-end system in an application layer to a data layer inspection system associated with a back-end system. An incoming user request is received, at the data layer inspection system, from a gateway system associated with the application front-end system. One or more outgoing statements targeting a back-end system are received at the data layer inspection system. The data layer inspection system accesses a mapping data structure based on the one or more outgoing statements to thereby correlate the one or more outgoing statements with the incoming user request. The data layer inspection system retrieves source identification information associated with the incoming user request based on the correlation of the one or more outgoing statements with the incoming user request. The data layer inspection system performs a data layer inspection operation based on the source identification information.

Abstract: A system and method of debugging a multi-threaded process with at least one running thread and at least one suspended thread is disclosed. Embodiments utilize a blocking function to block the thread of a process while other threads are allowed to run. The blocking function may be executed in a suspended thread by a debugger under control of a thread blocking controller. The other threads may implement interprocess communication channels for enabling communication between the process and another application. A simulated user interface (UI) of a debugger enables interaction with users while a hardware simulation thread is blocked, where blocking of the hardware simulation thread may be implemented by a thread blocking component implemented externally to the debugger. Where a thread blocking controller is implemented within the debugger, a debugger UI may interact with a user while the hardware simulation thread is blocked and interprocess communication threads are running.

Abstract: According to an aspect of an embodiment, a method may include identifying a fault location of a fault in a software program using a test suite. The method may further include implementing, in the software program, a repair candidate for the fault. In addition, the method may include augmenting the test suite with a plurality of test oracles that are based on observed behavior of the software program and that correspond to the fault location. Moreover, the method may include running the augmented test suite with respect to the software program with the implemented repair candidate. The method may also include prioritizing the repair candidate as a repair of the software program based on a failure rate of the plurality of test oracles with respect to running the augmented test suite.

Abstract: A test device includes a memory and a processor coupled to the memory. The processor is configured to execute a test on a first virtual machine among a plurality of virtual machines included in a network in operation. The processor is configured to generate a first snapshot of the first virtual machine before the test is executed. The processor is configured to generate a first substitute machine from the first snapshot. The first substitute machine is a substitute for the first virtual machine. The processor is configured to determine whether the test results in success. The processor is configured to replace the first virtual machine with the first substitute machine depending on a result of the determination.

Abstract: A device and a method are provided to automatically generate test case for embedded software. This invention is in software test field, including symbolic execution kernel module, path selection module, solver, debugger, concrete execution kernel module and debugger agent module. The tested software and test cases are uploaded from the host system to the embedded system through debugger and debugger agent. The concrete execution kernel module starts the tested software. The symbolic execution kernel module captures the run-time information of the tested software through the debugger. When the tested software operates on the symbol source, the symbolic execution kernel module marks the symbol source, tracks the symbol propagation, generates path condition and sends the path condition to path selection module. This invention can automatically generate test cases for embedded software, which doesn't need the source code of the tested software and can be conveniently used for commercial software.

Abstract: An example method of generating one or more scripts specific to an application programming interface (API) type and language and in accordance with user-selected events includes receiving an API type and a language in which to implement a script. Events selected by a user via a graphical user interface in response to receiving a request to record the events may be recorded. Additionally, the user-selected events may be mapped to a set of commands specific to the API type and the language. Additionally, a script including a first command to import a set of modules specific to the API type and language, a second command to create a computing session, and the set of commands is generated.

Abstract: Aspects of the present disclosure disclose systems and methods for managing space in storage devices. In various aspects, the disclosure is directed to providing more efficient method for managing free space in the storage system, and related apparatus and methods. In particular, the system provides for freeing blocks of memory that are no longer being used based on the information stored in a file system. More specifically, the system allows for reclaiming of large segments of free blocks at one time by providing information on aggregated blocks that were being freed to the storage devices.

Abstract: Garbage collection processing is facilitated. Based on execution of a load instruction and determining that an address of an object pointer to be loaded is located in a pointer storage area and the object pointer indicates a location within a selected portion of memory undergoing garbage collection, processing control is obtained by a handler executing within a processor of the computing environment. The handler obtains the object pointer from the pointer storage area, and determines whether the object pointer is to be modified. If the object pointer is to be modified, the handler modifies the object pointer. The handler may then store the modified object pointer in a selected location.

Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.

Abstract: Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.

Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit for a multi-level cache system. The access patterns that are matched to the access maps may include prefetches for different cache levels. Centralizing the generation of prefetches into one prefetch circuit may provide better observability and controllability of prefetching at various levels of the cache hierarchy, in an embodiment. Prefetches at different levels may be controlled individually based on the accuracy of those prefetches, in an embodiment. Additionally, in an embodiment, access patterns that are longer that a given threshold may have the granularity of the prefetches change so that more data is prefetched and the prefetches occur farther in advance, in some embodiments.

Abstract: A system and method for using high bandwidth memory as cache memory. A high bandwidth memory may include a logic die, and, stacked on the logic die, a plurality of dynamic read-only memory dies. The logic die may include a cache manager, that may interface to external systems through an external interface conforming to the JESD235A standard, and that may include an address translator, a command translator, and a tag comparator. The address translator may translate each physical address received through the external interface into a tag value, a tag address in the stack of memory dies, and a data address in the stack of memory dies. The tag comparator may determine whether a cache hit or cache miss has occurred, according to whether the tag value generated by the address translator matches the tag value stored at the tag address.

Abstract: A processor includes an arithmetic processing circuit, a cache memory including a plurality of ways, a usage information register storing usage information indicating whether to use each of the plurality of ways, a purge control circuit performing purge processing on a basis of rewriting of the usage information within the usage information register according to an instruction executed by the arithmetic processing circuit, the purge processing including processing of deleting, from the cache memory, target data retained in a target way to be stopped and processing of writing back part of the target data, the part of the target data being data rewritten in the cache memory, to a main memory at a lower level than the cache memory, and an access control circuit controlling accessing the cache memory on a basis of a memory access request received from the arithmetic processing circuit and status of the purge processing.

Abstract: Aspects include computing devices, systems, and methods for implementing a cache maintenance or status operation for a component cache of a system cache. A computing device may generate a component cache configuration table, assign at least one component cache indicator of a component cache to a master of the component cache, and map at least one control register to the component cache indicator by a centralized control entity. The computing device may store the component cache indicator such that the component cache indicator is accessible by the master of the component cache for discovering a virtualized view of the system cache and issuing a cache maintenance or status command for the component cache bypassing the centralized control entity. The computing device may receive the cache maintenance or status command by a control register associated with a cache maintenance or status command and the component cache bypassing the centralized control entity.

Abstract: A marking capability is used to provide an indication of whether a block of memory is being used by a guest control program to back an address translation structure. The marking capability includes setting an indicator in one or more locations associated with the block of memory. In a further aspect, the marking capability includes resetting the one or more indicators to indicate that the block of memory is no longer being used by the guest control program to back the address translation structure.

Abstract: A marking capability is used to provide an indication of whether a block of memory is being used by a guest control program to back an address translation structure. The marking capability includes setting an indicator in one or more locations associated with the block of memory. In a further aspect, the marking capability includes resetting the one or more indicators to indicate that the block of memory is no longer being used by the guest control program to back the address translation structure.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: A computer system, such as a data storage system, implements techniques for segregating and controlling access to data stored in multiple regions. In some embodiments, redundancy coded shards generated from the data and stored in durable storage of a data storage system is allocated across multiple regions, but in a fashion that prevents actors with access to regions outside that of a “home” region from recovering a sufficient number of unique shards to regenerate the data represented thereby. In some embodiments, encryption is used to segregate the data by encrypting the generated shards, then storing the cryptographic information on or otherwise controlling access on hosts or other devices of only the home region.

Abstract: An apparatus includes an arbiter circuit and a translation circuit. The arbiter circuit may be configured to generate a first address signal in a virtual memory space by arbitrating among a plurality of clients to access a physical memory space. The clients may be classified as either privileged clients or non-privileged clients. The physical memory space may comprise at least one secure space. The translation circuit may be configured to generate a second address signal by translating a page in the virtual memory space into the physical memory space based on the first address signal. The page may corresponds to a particular one of the clients that won the arbitration. The page may be translated (a) into the secure space if the particular client is one of the privileged clients and (b) outside the secure space otherwise.

Abstract: In one aspect, a system for controlling domain name service (DNS) caching is disclosed, the system includes a processor; a memory; and one or more modules stored in the memory and executable by a processor to perform various operations. The various operations include maintain a hard cache on a local disk that includes a file of DNS entries that persists and available for access by an application after a reboot of a Java Virtual Machine (JVM) system running the application; populate a runtime positive soft cache with the entries from the hard cache, wherein the positive soft cache represents DNS entries assumed to be successful for resolving DNS client calls from the application that persists until the reboot of the JVM system running the application; and load entries into the runtime positive soft cache populated from the hard cache in response to an application making DNS client calls.

Abstract: A method and an apparatus for accessing physical resources, is used to restrict access to physical resources of other light system kernel Light OSs by a first Light OS in a multi-kernel operating system and ensure security of accessing physical resources among the Light OSs. A method, executed by secure firmware, includes: receiving a physical address corresponding to a physical resource to be accessed by the first Light OS; determining whether the physical address corresponding to the physical resource is out of bounds; and if the physical address corresponding to the physical resource is within bounds, sending an access continuity signal to the first Light OS; or if the physical address corresponding to the physical resource is out of bounds, sending an access error signal to the first Light OS.

Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.

Abstract: An interface unit for data exchange between a first processor of a computer system and a peripheral environment. The interface unit has a number of input data channels for receiving input data from the peripheral environment and a first access management unit. The access management unit is configured to receive a request for providing the input data, stored in the number of input data channels, from a first interface processor stored in the interface unit and from a second interface processor stored in the interface unit and to provide or not to provide the input data, stored in the number of input data channels, to the first interface processor and the second interface processor. A first priority and a second priority can be stored in the first access management unit.

Abstract: The present invention provides a mobile wireless communication system, network, and method for managing the use of one or more peripherals with a mobile wireless communication device in connection with an upcoming event. The method includes associating one or more peripherals with one or more users, where the one or more peripherals have an extended capability for use with a mobile wireless communication device, and maintaining a list of the peripheral associations and the respective extended capabilities. Upcoming events and any need for corresponding event supporting capabilities are monitored. Any unmet need for event supporting capabilities is compared with the extended capability of peripherals associated with at least some of the one or more users that will be attending the upcoming event.

Abstract: A bus controller is configured to transmit a broadcast read request on at least one bus. The broadcast read request includes an address. A first logic module determines that the broadcast read request is targeting the first logic module. The first logic module reads a first value from a first register included in the first logic module. The first register is specified by the address included in the broadcast read request. The first value is transmitted onto the at least one bus. A second logic module determines that the broadcast read request is targeting the second logic module. The second logic module reads a second value from a second register included in the second logic module. The second register is specified by the address included in the broadcast read request. The second value is transmitted onto the at least one bus.

Abstract: Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The receiver may be configured to receive first data signals having a first voltage swing and having a first slew rate. The transmitter may be configured to provide second data signals having a second voltage swing and having a second slew rate, wherein the first and second voltage swings are different, and wherein the first and second slew rates are different.

Abstract: Embodiments relate to non-interfering transactions. An aspect includes receiving, by a first transaction, a conflicting remote access request from a requester, the remote access request being directed to a memory area that is owned as part of at least one of a transactional read set and transactional write set by the first transaction. Another aspect includes determining whether the requester is a second transaction that is indicated as a non-interfering transaction with respect to the first transaction. Another aspect includes, based on determining that the requester is indicated as a non-interfering transaction with the first transaction, handling the remote access request. Yet another aspect includes continuing execution of the first transaction and the second transaction after handling the remote access request.

Abstract: Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller.

Abstract: A connecting device able to allocate master and slave roles between two intelligent devices having On-The-Go functions, depending on the intelligent device connects at a first point in time to one of two connectors, the connecting device also includes a control circuit connected between the two connectors. The control circuit between the connectors maintains and controls the master-slave relationship between the two intelligent devices.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes communicatively coupling graphics processing units (GPUs) over a Peripheral Component Interconnect Express (PCIe) fabric. The method also includes establishing a peer-to-peer arrangement between the GPUs over the PCIe fabric by at least providing an isolation function in the PCIe fabric configured to isolate a device PCIe address domain associated with the GPUs from at least a local PCIe address domain associated with a host processor that initiates the peer-to-peer arrangement between the GPUs.

Abstract: An integrated circuit (IC) having multiple cores controls write access to its input/output (I/O) pins. The IC includes a pin-control circuit, a memory, and a set of I/O pins. The pin-control circuit allows a core to independently control individual ones of the I/O pins. A set of pin-control values are defined that correspond to the set of I/O pins to indicate a type of core that can access an I/O pin. The pin-control circuit receives the pin-control values, a source ID, and write data generated by a core, and updates a pin data bit stored in the memory with a corresponding bit of the write data when the core is allowed to access the I/O pin. The pin-control circuit does not change the pin data bit when the core is denied write access to the I/O pin.

Abstract: A system includes multiple servers, each server including a host bus adapter (HBA) and multiple data storage devices. The system further includes a controller including a switch, wherein the switch has first ports and second ports, each first port being coupled to a HBA of one server, and each second port being coupled to one of the data storage devices, and wherein communications between any of the HBAs and any of the data storage devices are directed through the switch. A method is also provided including coupling multiple host bus adapters to first ports of a controller, wherein multiple servers each include one of the HBAs, coupling multiple data storage devices in each of the servers to second ports of the controller, and directing communications between any of the HBAs and any of the data storage devices through the controller.

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

Abstract: Heterogeneous hardware accelerator architectures for processing sparse matrix data having skewed non-zero distributions are described. An accelerator includes sparse tiles to access data from a first memory over a high bandwidth interface and very/hyper sparse tiles to randomly access data from a second memory over a low-latency interface. The accelerator determines that one or more computational tasks involving a matrix are to be performed, partitions the matrix into a first plurality of blocks that includes one or more sparse sections of the matrix, and a second plurality of blocks that includes sections of the matrix that are very- or hyper-sparse. The accelerator causes the sparse tile(s) to perform one or more matrix operations for the computational task(s) using the first plurality of blocks and further causes the very/hyper sparse tile(s) to perform the one or more matrix operations for the computational task(s) using the second plurality of blocks.

Abstract: Systems and methods are disclosed for key phrase clustering of documents. In accordance with one implementation, a method is provided for key phrase clustering of documents. The method includes obtaining a first plurality of documents based at least on a user input, obtaining a statistical model based at least on the user input, and obtaining, from content of the first plurality of documents, a plurality of segments. The method also includes identifying a plurality of clusters of segments from the plurality of segments, determining statistical significance of the plurality of clusters based at least on the statistical model and the content, and providing for display a representative cluster from the plurality of tokens, the representative cluster being determined based at least on the statistical significance. The method further includes determining a label for the representative cluster based at least on the plurality of clusters and the statistical significance.

Abstract: Systems and methods of the present invention provide for one or more server computers communicatively coupled to a network and configured to: monitor a character stream; identify characters comprising a domain name request; identify a token in a language character map comprising the characters and associated with a language; generate, using a software translation engine, a translation of the first token into a second language; generate candidate domain names comprising: a domain name comprising the token; and a second domain name comprising the second token; modify, in real time, a user interface control to display the list of candidate domain names.

Abstract: Embodiments of the current invention may include methods, systems, and products designed to utilize a template processor to determine particular data types and/or data instances that are matched to each of a number of different templates. An input file containing at least a data type/instances portion may be processed along with another input that includes templates with code for processing one or more of the data types/instances. Some of the data types/instances may have a unique identifier added to the definition and/or instantiation. Similarly, some of the templates may have code added that may cause the template processor to create an output for each data type/instance that is processed using the template. The output of the processor may then be used to indicate which of the data types/instances may be processed by each template for which the additional code was added.

Abstract: Systems and methods are provided for creating tables using auto-generated templates. Reports including lines of text to be extracted into tables are received. An auto define input is received to auto-generate the tables corresponding to the reports. Groups of lines are identified from among the lines of text in the reports. A detail group and relevant groups are selected and identified from among the groups of lines. A final detail group is created by merging the detail group with at least a portion of the relevant groups. Append groups are identified from among the groups of lines not included in the final detail group. Templates corresponding to the final detail group and the append groups are generated. Text is extracted from the reports based on the templates. Tables are generated using the text extracted from the reports, by assigning the text from the text fragments to entries in the tables.

Abstract: Methods, systems and computer program products are provided for visually indicating relationships among cells in a spreadsheet. Each of a first graphical linking element extending between cells in a first branch of a dependency tree of a root cell and a second graphical linking element extending between cells in a second branch of the dependency tree of the root cell is independently displayed and hidden.

Abstract: Systems and methods are provided for automatically translating one or more electronic spreadsheets into scripts. One or more electronic spreadsheets containing data arrays and formula arrays may be accessed. The electronic spreadsheet(s) may implement various logic using the data arrays and the formula arrays. The range(s) of the formula arrays may be determined. The range(s) of the data arrays may be determined based on the range(s) of the formula arrays. Conversion ranges may be determined based on the range(s) of formula arrays and the range(s) of data arrays. One or more dependencies between the conversion ranges may be determined and used to generate source code modeling the logic implemented by the electronic spreadsheet(s).

Abstract: A system for identifying language(s) for content items is disclosed. The system can identify different languages for content item words segments by identifying segment languages that maximize a probability across the segments. The probability can be a combination of: an author's likelihood for the language identified for the first word; a combination of transition frequencies for selected languages identified for words, the transition frequencies indicating likelihoods that a transition occurred to the selected language from the previous word's language; and a combination of observation probabilities indicating, for a given word in the content item, a likelihood the given word is in the identified language. For an in-vocabulary word, the observation probabilities can be based on learned probability for that word. For an out-of-vocabulary word, the probability can be computed by breaking the word into overlapping n-grams and computing combined learned probabilities that each n-gram is in the given language.

Abstract: A mechanism is provided for representing information, such as binary sequence, in a manner that is easier to read and less likely to generate errors when interacted with by human. A dictionary is seeded with two or more set of words, the words being selected from distinct categories. Symbols may be created by combining words from the distinct categories. A mapping of symbols to corresponding values may then be generated. The generated mapping may be used to translate bit values to symbols and symbols to bit values.

Abstract: Methods, computer program products, and systems are presented. The methods include, for instance: monitoring one or more message of the conversation between multiple users for an entity reference; detecting the entity reference in a message in the conversation. An entity reference list stores previously established alternate name referring to a user in the conversation. By analyzing the message and following messages in the conversation for relevance of and sentiment to the entity reference, the entity reference is evaluated and if acceptable, the entity reference list is updated with the entity reference as a new alternate name to identify the user in subsequent messages.

Abstract: A method of decision definition using a rules vocabulary includes: receiving free form input; identifying terms contained within the free form input; searching the rules vocabulary objects for terms; responsive to the term being found, obtaining input from a user as to whether to use the found term; responsive to the term not being found; searching the rules vocabulary attributes for terms having attributes corresponding to the term; responsive to the term being found, obtaining input from a user as to whether to use the found term; and refactoring the free form input with the found term accepted by the user. The method also includes updating the rules vocabulary with the term identified in the free form input as a synonym for the term found in said rules vocabulary. One embodiment further provides a method of determining semantic equivalence between a plurality of rules using a rules database having preferred terms.