Patents Issued in June 18, 2019
  • Patent number: 10324712
    Abstract: A method of maintaining or improving functionality of legacy code for operation in a new machine system is disclosed. Reference code and documentation are leveraged to provide functionality of the machine system. The sections may be identified and presented as user defined representations (for example, pseudocode, diagrams, descriptive text, or encapsulations) so that the reference code may be migrated to a newer machine system and the sections may be re-written as necessary to make the sections of reference compatible with the new machine system.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: June 18, 2019
    Inventor: Thomas A. Nolan
  • Patent number: 10324713
    Abstract: Embodiments of the present invention address deficiencies of the art in respect to server-side processing and provide a novel and non-obvious method, system and computer program product for performing server-side translation for custom application support in client-side scripts. In an embodiment of the invention, a method for supporting custom applications in client-side scripts can be provided. The method can include retrieving a client-side script, for execution in a client-environment and detecting an incompatibility of the retrieved client-side script resulting from a dependency of the client-side script upon an expected occurrence of an event in the client-environment. Thereafter, the retrieved script can be rewritten to manually invoke the expected event in the client-environment. Finally, the rewritten script can be compiled and cached, and the compiled and cached rewritten script can be delivered to the client-environment for execution therein.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventor: Joel B. Allen
  • Patent number: 10324714
    Abstract: Apparatus and method are described for trimming parameters of analog circuits. The apparatus includes trim result registers for storing trim results for adjusting parameters of analog circuits, respectively; a memory device configured to store sets of operands; and a trim calculation unit configured to generate the set of trim results by performing a set of arithmetic operations on the sets of operands based on a set of commands, respectively. The trim calculation unit receives a set of commands; transfers sets of operands from the memory device to a programmable ALU array based on the set of commands, respectively; generates trim results by performing arithmetic operations on the sets of operands based on the set of commands, respectively; and sends the trim results to the trim result registers based on the set of commands, respectively.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Michael Anderson, Gunjan Upadhyay
  • Patent number: 10324715
    Abstract: Setting or updating of floating point controls is managed. Floating point controls include controls used for floating point operations, such as rounding mode and/or other controls. Further, floating point controls include status associated with floating point operations, such as floating point exceptions and/or others. The management of the floating point controls includes efficiently updating the controls, while reducing costs associated therewith.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10324716
    Abstract: An instruction defined to be a looping instruction is obtained and processed. A determination is made as to whether an obtained selected character is an expected selected character. Based on the obtained selected character being the expected selected character, an execution process is used that includes a sequence of operations to perform an operation, the sequence of operations replacing a loop and providing a non-looping sequence to perform the operation on up to a defined number of units of data. The sequence of operations is configured to repeat one or more times and to terminate based on the obtained selected character. Based on the obtained selected character being different than the expected selected character, an alternate execution process is chosen.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10324717
    Abstract: An instruction defined to be a looping instruction is obtained and processed. A determination is made as to whether an obtained selected character is an expected selected character. Based on the obtained selected character being the expected selected character, an execution process is used that includes a sequence of operations to perform an operation, the sequence of operations replacing a loop and providing a non-looping sequence to perform the operation on up to a defined number of units of data. The sequence of operations is configured to repeat one or more times and to terminate based on the obtained selected character. Based on the obtained selected character being different than the expected selected character, an alternate execution process is chosen.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael K. Gschwind
  • Patent number: 10324718
    Abstract: A method of an aspect includes receiving a masked packed rotate instruction. The instruction indicates a first source packed data including a plurality of packed data elements, a packed data operation mask having a plurality of mask elements, at least one rotation amount, and a destination storage location. A result packed data is stored in the destination storage location in response to the instruction. The result packed data includes result data elements that each correspond to a different one of the mask elements in a corresponding relative position. Result data elements that are not masked out by the corresponding mask element include one of the data elements of the first source packed data in a corresponding position that has been rotated. Result data elements that are masked out by the corresponding mask element include a masked out value. Other methods, apparatus, systems, and instructions are disclosed.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal San Andrian, Suleyman Sair, Bret L. Toll, Zeev Sperber, Amit Gradstein, Asaf Rubinstein
  • Patent number: 10324719
    Abstract: Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael F. Cowlishaw, Shawn D. Lundvall, Ronald M. Smith, Sr., Phil C. Yeh
  • Patent number: 10324720
    Abstract: A system and method tests computer software using tracking bits in branch instructions to track portions of the software that have been tested. The tracking bits are bits of a branch programming instruction and may be repurposed hint bits used in the prior art to control pre-fetch of instructions. A branch tracking unit sets bits in a branch instruction of an application or program being tested. The branch tracing unit sets a first bit if a branch is taken and sets a second tracking bit if the branch is not taken. The modified program instructions can be analyzed after running the test inputs to determine if any branches in the software have not been exercised by the test inputs.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gaurav Batra, Demetrice Browder, Douglas J. Griffith, Sreenivas Makineedi
  • Patent number: 10324721
    Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Anupama A. Thaploo, Bhushan M. Borole, Bee Ngo, Iqbal R. Rajwani, Altug Koker, Abhishek R. Appu, Kamal Sinha, Wenyin Fu
  • Patent number: 10324722
    Abstract: Example implementations relate to global capabilities transferrable across node boundaries. For example, in an implementation, a switch that routes traffic between a node and global memory may receive an instruction from the node. The switch may recognize that data referenced by the instruction is a global capability, and the switch may process that global capability accordingly.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: June 18, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Dejan S Milojicic, Paolo Faraboschi, Chris I Dalton
  • Patent number: 10324723
    Abstract: Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: June 18, 2019
    Assignee: NXP USA, Inc.
    Inventors: Peter J Wilson, Brian C Kahne, Jeffrey W Scott
  • Patent number: 10324724
    Abstract: Methods and apparatuses relating to a fusion manager to fuse instructions are described. In one embodiment, a hardware processor includes a hardware binary translator to translate an instruction stream into a translated instruction stream, a hardware fusion manager to fuse multiple instructions of the translated instruction stream into a single fused instruction, a hardware decode unit to decode the single fused instruction into a decoded, single fused instruction, and a hardware execution unit to execute the decoded, single fused instruction.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Patrick P. Lai, Tyler N. Sondag, Sebastian Winkel, Polychronis Xekalakis, Ethan Schuchman, Jayesh Iyer
  • Patent number: 10324725
    Abstract: The disclosure provides a method and a system for identifying and replacing code translations that generate spurious fault events. In one embodiment the method includes executing a first set and a second set of native instructions, performing a third translation of a target instruction to form a third set of native instructions in response to a determination that a fault occurrence is attributed to a first translation, wherein the third set of native instructions is not the same as the second set of native instructions, and the third set of native instructions is not the same as the first set of native instructions, and executing the third set of native instructions.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: June 18, 2019
    Assignee: Nvidia Corporation
    Inventors: Nathan Tuck, David Dunn, Ross Segelken, Madhu Swarna
  • Patent number: 10324726
    Abstract: Techniques are disclosed relating to scheduling graphics instructions for execution on different types of execution units based on characteristics of decoded and cached graphics instruction. In some embodiments, a graphics unit includes multiple different types of execution units that are configured to execute different types of instructions (e.g., different units for datapath, sample, load/store, etc.). In some embodiments, the graphics unit stores decoded instructions in an instruction cache in at least one cache level, along with information specifying characteristics of the instructions. The characteristics may be stored at clause granularity and may indicate the type of instructions in each clause (e.g., corresponding to which type of execution unit is configured to execute the instructions).
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: June 18, 2019
    Assignee: Apple Inc.
    Inventors: Michael A. Geary, Brian K. Reynolds, Terence M. Potter
  • Patent number: 10324727
    Abstract: A data processing apparatus executes a stream of instructions. Memory access circuitry accesses a memory in response to control signals associated with a memory access instruction that is executed in the stream of instructions. Branch prediction circuitry predicts the outcome of branch instructions in the stream of instructions based on a branch prediction table. Processing circuitry performs a determination of whether out-of-order execution of memory access instructions is to be performed based on memory prediction data, and selectively enables out-of-order execution of the memory access instructions in dependence on the determination. The memory prediction data is stored in the branch prediction table.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: June 18, 2019
    Assignee: ARM Limited
    Inventors: Curtis Glenn Dunham, Mitchell Bryan Hayenga
  • Patent number: 10324728
    Abstract: Embodiments relate to lightweight interrupts for condition checking. An aspect includes determining, by a condition checker in a computer system, that a condition occurs for an application executing on the computer system. Another aspect includes, based on determining that the condition occurs for the application, determining whether lightweight interrupts are enabled. Yet another aspect includes based on determining that lightweight interrupts are enabled, issuing a lightweight interrupt to the application and handling the instruction by the application.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giles R. Frazier, Michael Karl Gschwind, Christian Jacobi, Chung-Lung K. Shum, Joran S. C. Siu, Timothy J. Slegel, Zhong L. Wang
  • Patent number: 10324729
    Abstract: Methods and systems enabling rapid application development, verification, and deployment requiring only knowledge of high level languages. Two aspects of the disclosed methods and systems are called Machine Intelligence and Learning for Graphic chip Accessibility (MILeGrA) and Machine Intelligence and Learning for Graphic chip Execution (MILeGrE). Using MILeGrA and MILeGrE, high-level language programmers do not need to learn complex coprocessor programming languages, but can still use coprocessors (e.g., GPU processors) to benefit from results-in-seconds big data capabilities through the translation of coprocessor-unaware code to coprocessor-aware code. Execution of such coprocessor-unaware code on coprocessors includes parsing the coprocessor-unaware code to generate intermediate code, analyzing the intermediate code to determine a model for coprocessor-aware code generation, and generating coprocessor-aware code based on the model using machine learning techniques.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: June 18, 2019
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Nilay K. Roy, Rami S. Mangoubi
  • Patent number: 10324730
    Abstract: A computing device performs parallel computations using a set of thread processing units and a memory shuffle engine. The memory shuffle engine includes a register array to store an array of data elements retrieved from a memory buffer, and an array of input selectors. According to a first control signal, each input selector transfers at least a first data element from a corresponding subset of the register array, which is coupled to the input selector via input lines, to one or more corresponding thread processing units. According to a second control signal, each input selector transfers at least a second data element from another subset of the register array, which is coupled to another input selector via other input lines, to the one or more corresponding thread processing units.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: June 18, 2019
    Assignee: MediaTek, Inc.
    Inventors: Shou-Jen Lai, Pei-Kuei Tsung, Po-Chun Fan, Sung-Fang Tsai
  • Patent number: 10324731
    Abstract: The present invention provides a multimode startup method for intelligent device and the system thereof, through predefining a plurality of startup modes, and based on a plurality of application scenarios according to the application and service programs installed in the intelligent device, assigning the said application programs and service programs into different startup modes, then receiving a control instruction sent from the user, identifying the startup mode according to the said control instruction, before loading the application and service programs list assigned to the specific startup mode according to the identified startup mode.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: June 18, 2019
    Assignee: SHENZHEN SKYWORTH-RGB ELECTRONIC CO., LTD
    Inventor: Jinpeng Liu
  • Patent number: 10324732
    Abstract: Described is a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and ASSP initializing block may be embedded in a processor, such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), or other chipset. This controller and initializing block may be a configurable, while maintaining specialization, hardware block. This block may be implemented as a complex programmable logic device or as a simple cascaded programmable logic array block, such as being the equivalent of a few hundred logic gates, for example. Described also is a method of performing power sequencing and boot strapping for internal and external blocks on a chipset. The method includes powering a system power controller and initializing block and saving a power-up sequencing in a nonvolatile wake-up table.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 18, 2019
    Assignee: ATI TECHNOLOGIES ULC.
    Inventors: Behrooz Karimian-Kakolaki, Darlington C. Opara
  • Patent number: 10324733
    Abstract: Shutdown notification techniques are described in which notifications associated with various applications and functionality of a device are presented in conjunction with a shutdown sequence. In one or more implementations, a shutdown of the device may be initiated automatically in response to low power conditions, device/application errors, restarts, or explicitly by a user. A notification system of a device may be configured to enable designation of particular notifications to show upon shutdown. Notifications to output at shutdown may be selected based upon various criteria including but not limited to selection based on a perceived importance, notification type, particular application(s), and/or particular user contacts. When a shutdown is initiated, a check is performed to determine whether any designated notifications are available.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: June 18, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sung Joon Won, Jiwon Choi
  • Patent number: 10324734
    Abstract: In some examples, a method includes receiving, by a supervisor component executing at a computing device, a request to execute an application, and determining, by the supervisor component, whether any application container is currently allocated for the application. The method may also include, responsive to determining that an application container is currently allocated for the application: activating, by the supervisory, the application container currently allocated for the application, and executing, by the application container for the application, the application, and, responsive to terminating execution of the application, deactivating, by the supervisor component, the application container for the application.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: June 18, 2019
    Assignee: Google LLC
    Inventor: Ficus Kirkpatrick
  • Patent number: 10324735
    Abstract: A mechanism is disclosed that enables the invocation of methods of object instances that have persistent data and a mutable key. A mutable key capability is advantageous in a variety of applications, such as monitoring a set of users and their login status on a plurality of media servers (e.g., an email server, an instant messaging server, a voice mail server, a video server, an audio-conferencing server, etc.). The methods that can be invoked include get methods, set methods, unset methods, finder methods, destructors, and business methods. Implementations based on the Enterprise JavaBean specification are disclosed for three illustrative embodiments of the present invention. The illustrative embodiments of the present invention can also be implemented in accordance with object persistence mechanisms other than Enterprise JavaBeans.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: June 18, 2019
    Assignee: Avaya Inc.
    Inventor: Reinhard Peter Klemm
  • Patent number: 10324736
    Abstract: Systems and methods for displaying a stereoscopic three-dimensional (3D) webpage overlay. In some embodiments user input may be received from a user input device and in response to determining that the user input device is substantially concurrently interacting with the 3D content, at least one of a plurality of render properties associated with of the 3D content may be modified. In some embodiments, the at least one render property may be incrementally modified over a specified period of time, thereby animating modification of the at least one render property.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: June 18, 2019
    Assignee: zSpace, Inc.
    Inventors: Jonathan J. Hosenpud, Clifford S. Champion
  • Patent number: 10324737
    Abstract: Rendering of a portal page that is displayable on a client system includes receiving a request for a portal page by a web portal engine, monitoring server-side aggregation and rendering performance by the web portal engine, and comparing a measured performance parameter value of the server-side aggregation and rendering against a pre-defined threshold value. The server-side aggregation and rendering is interrupted, based upon the comparison, once the threshold value is exceeded. Further, an intermediate result of the portal page is prepared based on the server-side aggregation and rendering for sending, such that a client-side processing completes the interrupted aggregation and rendering of the portal page.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Matthias Falkenberg
  • Patent number: 10324738
    Abstract: Disclosed aspects relate to window management in a stream computing environment. A set of computing resources may be detected with respect to the stream computing environment. Based on the set of computing resources, a set of window configurations in the stream computing environment may be determined. In response to determining the set of window configurations in the stream computing environment, the set of window configurations may be established in the stream computing environment.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric L. Barsness, Daniel E. Beuch, Michael J. Branson, John M. Santosuosso
  • Patent number: 10324739
    Abstract: In a computing device for simulating the application of cosmetic effects, a user interface with a plurality of cosmetic templates is displayed to a user, where each cosmetic template comprises a predefined sequence for applying cosmetic effects. A selection of one of the cosmetic templates is obtained from the user, and a digital representation of the user is captured. The computing device tracks facial features of the user in the digital representation of the user and generates a virtual mirror for the user to view. The virtual mirror displays progressive application of each of the sequence of cosmetic effects of the selected cosmetic template to corresponding facial features in the digital representation. A digital representation of the simulated application of all of the sequence of cosmetic effects is then stored.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: June 18, 2019
    Assignee: PERFECT CORP.
    Inventors: Chen-Wei Chou, Ching-Hsuan Ma
  • Patent number: 10324740
    Abstract: A control-circuit of an emulation system may include one or more serial link inputs communicatively coupled to a serial bus, a serial link input receiving an input control bit from the serial bus. A configurable logic circuit may be configured to receive multiple control bits from the one or more serial link inputs, execute one or more operations on the plurality of input control bits according to programmable logic, and transmit an output control bit to a serial output link.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: June 18, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell G. Poplack, Yuhei Hayashi
  • Patent number: 10324741
    Abstract: According to one technique, a virtual machine stores type profiling data for program code, the type profiling data indicating observed types for profiled values within the program code at specific profile points during previous executions of the program code. The virtual machine determines to optimize a particular code segment of the program code. The virtual machine generates a program representation describing a flow of data through different variables within the code segment. The virtual machine assigns speculative types to certain variables in the particular code segment by: assigning speculative types of first variables to respective observed types recorded in the type profiling data; calculating speculative types of second variables, based on propagating the speculative types of the first variables through the program representation.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: June 18, 2019
    Assignee: Oracle International Corporation
    Inventors: Roland Westrelin, John Robert Rose
  • Patent number: 10324742
    Abstract: A method. A JavaScript (JS) object is instantiated. The instantiated JS object processes application programming interface (API) requests received from mobile devices. The instantiation of the JS object is based on a JS model including (1) a JS file that stores a description of a behavior of the JS object and (2) a JS object notation (JSON) file that stores a description of properties of the JS object. The JSON file includes at least one validation rule to reject a data tuple unless the data tuple meets a required constraint specified in the validation rule. A data abstracter is an interface between the JS object and a set of data storages from which the JS object retrieves data while processing at least two of the API requests. The data abstractor is connected with the set of data storages by implementing a data exchange logic for the set of data storages.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Issac Jacob Roth, Albert K. Tsang, Zhaohui Feng, Ritchie Tyler Martori, Miroslav Bajtos
  • Patent number: 10324743
    Abstract: Systems and methods for announcing virtual machine migration. An example method may comprise: receiving, by a first hypervisor running on a first computer system, a migration announcement from a virtual machine that is undergoing live migration from the first computer system to a second computer system; and transmitting a message comprising the migration announcement to a second hypervisor running on the second computer system.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: June 18, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 10324744
    Abstract: Described herein are systems, methods, and software to provide virtualized computing sessions with attachable volumes to requesting users. In one implementation, a virtual computing service identifies a service login for an end user to initiate a virtual computing session. In response to the service login, the virtual computing service identifies a virtual machine to allocate to the virtual computing service, and initiates a user login process to log the end user into the virtual machine. The virtual computing service further initiates, prior to completing the user login process, a volume attach process to attach at least one storage volume to the virtual machine based on credentials associated with the service login.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: June 18, 2019
    Assignee: VMware, Inc.
    Inventors: Jeffrey Ulatoski, Steven Lawson, Matthew Conover
  • Patent number: 10324745
    Abstract: Systems herein include thin clients that operate with managed profile-based virtual machines. This can allow users to utilize personal user devices in an enterprise environment without subjecting sensitive enterprise credentials to the user device. A management server can determine a profile associated with the user device. Based on the profile, a virtual machine can be instantiated at a thin server, remotely from the thin client. The profile-specific virtual machine can include a particular guest operating system, guest applications, security features, or functionality. The instance of the virtual machine can communicate graphics information from a guest application to the thin client, and the thin client can communicate user interface events to the instance for controlling the guest application.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: June 18, 2019
    Assignee: AirWatch, LLC
    Inventors: Kar Fai Tse, Ketan Bhardwaj, Erich Stuntebeck
  • Patent number: 10324746
    Abstract: Some embodiments provide a novel method for authorizing network requests for a machine in a network. In some embodiments, the method is performed by security agents that execute on virtual machines operating on a host machine. In some embodiments, the method captures a network request (e.g., network control packets, socket connection request, etc.) from a primary application executing on the machine. The method identifies an extended context for the network request and determines whether the network request is authorized based on the extended context. The method then processes the network request according to the determination. The extended context of some embodiments includes identifications for primary and secondary applications associated with the network request. Alternatively, or conjunctively, some embodiments include identifications for primary and secondary users associated with the network request.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: June 18, 2019
    Assignee: NICIRA, INC.
    Inventors: Vasantha Kumar, Prasad Sharad Dabak, Azeem Feroz, Amit Vasant Patil
  • Patent number: 10324747
    Abstract: In one embodiment, for each of the nodes forming a cluster that share a cluster shared volume (CSV), a remote connection is established with an operating system (OS) management interface of an operating system of the node to query and to obtain OS configuration information concerning a VMM hosting one or more virtual machine (VMs) within the node. A remote connection is established with a VMM interface of the VMM of the node to query and to obtain VM information concerning each of the VMs hosted by the VMM in the node. An analysis is performed on the OS configuration information and the VM information in view of a set of management rules. A report is generated based on the analysis, the report including information indicating which of the management rules has been violated.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: June 18, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Anupam Chakraborty, Tushar Dethe, Subhashish Mallik
  • Patent number: 10324748
    Abstract: Apparatuses, methods and storage medium associated with live migration of virtual machines (VMs) from/to host computers with graphics virtualization are disclosed herein. In embodiments, an apparatus may include a virtual machine monitor (VMM) having a memory manager to manage accesses of system memory of the apparatus, including tracking of modified memory pages of the system memory. Additionally, the VMM may include a graphics command parser to analyze graphics commands issued to a graphics processor (GPU) of the apparatus to detect writes to the system memory caused by the graphics commands, and augment the tracking of modified memory pages. Further, the VMM may include a live migration function to live migrate a VM to another apparatus, including provision of current memory content of the VM, utilizing modified memory pages tracked by the memory manager, as augmented by the graphics command parser.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Yao Zu Dong, Zhiyuan Lv
  • Patent number: 10324749
    Abstract: A method, system and computer program product for optimizing runtime performance of an application workload. Network input/output (I/O) operations between virtual machines of a pattern of virtual machines servicing the application workload in a private cloud are measured over a period of time and depicted in a histogram. A score is generated for each virtual machine or group of virtual machines in the pattern of virtual machines based on which range in the ranges of I/O operations per seconds (IOPS) depicted in the histogram has the largest sample size and the number of virtual machines in the same pattern that are allowed to be in the public cloud. In this manner, the runtime performance of the application workload is improved by minimizing the network input/output communications between the two cloud environments by migrating those virtual machine(s) or group(s) of virtual machines with a score that exceeds a threshold value.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Rahul Ghosh, Giribabu V. Paramkusham, Aaron J. Quirk, Upendra Sharma
  • Patent number: 10324750
    Abstract: A computer system includes a node including a plurality of processes, an instruction unit that designates a key range of data processed by the process, and a distribution unit. When a first key range is processed by a first process and a third key range, which is a portion of the first key range, is processed by a second process that processes a second key range, the instruction unit transmits a first updated key range to the first process, transmits a second updated key range to the second process, and transmits third range update information including first and second new ranges to the distribution unit. When receiving the third range update information, the distribution unit changes the distribution of the data to be processed. The first process performs data processing in the first updated key range and the second process performs data processing in the second updated key range.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: June 18, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Yutaro Kato, Toshiyuki Hasegawa, Nobuyuki Yamamoto
  • Patent number: 10324751
    Abstract: An information processing apparatus includes: a memory configured to store an information processing program; and a plurality of processor cores configured to acquire and execute a task from a storage region which is provided for each of the processor cores and including a first processor core configured to execute the information processing program, wherein the first processor core: performs, in work steal in which a task stored in a storage region of the first processor core is acquired by a second processor core, a writing process for an abort region, which is provided corresponding to the task, for detecting access contention by the first processor core and the second processor core using a transactional memory function; and performs a reading process for the abort region when the task is to be acquired from the storage region.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: June 18, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Yuto Tamura
  • Patent number: 10324752
    Abstract: Systems and methods for improving response times in based on application states. In some embodiments, an Information Handling System (IHS) may include a Central Processing Unit (CPU) and a hardware memory storage device coupled to the CPU, the hardware memory storage device having program instructions stored thereon that, upon execution by the CPU, configure the IHS to: identify a first state of an application being executed by the CPU at runtime; identify a trigger event configured to cause the IHS to change from the first state to a second state; in response to the trigger event, switch from the first state to a second state, wherein the first state is associated with first hardware configuration and the second state is associated with a second hardware configuration; and in response to the trigger event, switch the first hardware configuration to the second hardware configuration.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: June 18, 2019
    Assignee: Dell Products, L.P.
    Inventors: Farzad Khosrowpour, Mitchell Anthony Markow
  • Patent number: 10324753
    Abstract: A replication factor tuner can use historical data about previous runs of compute jobs to predict execution time periods for jobs scheduled to run in a distributed system, which implements a software framework that utilizes data locality for parallelization of jobs or tasks of the jobs. The replication factor tuner also determines input data sets that are common across the jobs scheduled to run in the distributed system. Based on the predicted execution time periods on commonality of input data sets, the replication factor tuner determines predicted concurrent access of the input data sets by the scheduled compute jobs. The tuner can change replication factors of input data sets that are predicted to be concurrently accessed by a threshold number of the scheduled compute jobs.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: June 18, 2019
    Assignee: CA, Inc.
    Inventors: Mukul Jain, Hiren Mansukhlal Mandalia
  • Patent number: 10324754
    Abstract: Managing virtual machine patterns, including: identifying resource utilization of each virtual machine within a first virtual machine pattern having a first group of resources; determining resource requirements of one or more applications executing on one or more virtual machines within the first virtual machine pattern; based on the resource utilization and the determined resource requirements, identifying a second virtual machine pattern having a second group of resources; and deploying at least one of the one or more applications executing on the one or more virtual machines within the first virtual machine pattern onto one or more virtual machines of the second virtual machine pattern.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bin Cao, Jessica R. Eidem, Brian R. Muras
  • Patent number: 10324755
    Abstract: Mechanisms are provided for distributing work requests to worker devices. The mechanisms generate a cycle table data structure which segments a set of work request allocations into a plurality of cycles in which, for each cycle, a subset of worker devices, from a set of worker devices, are eligible to receive allocations of work requests. The mechanisms receive a work request from a computing device and select a worker device to receive the work request, from a first subset of worker devices that are eligible to receive allocations of work requests for a current cycle in the cycle table data structure, based on both of entries in the cycle table data structure corresponding to a current cycle, and execution of weighted round robin scheduling logic. The mechanisms distribute the work request to the selected worker device which performs an operation on the work request.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventor: Philip D. Hirsch
  • Patent number: 10324756
    Abstract: Techniques are described for eliminating backpressure in a distributed system by changing the rate data flows through a processing element. Backpressure occurs when data throughput in a processing element begins to decrease, for example, if new processing elements are added to the operating chart or if the distributed system is required to process more data. Indicators of backpressure (current or future) may be monitored. Once current backpressure or potential backpressure is identified, the operator graph or data rates may be altered to alleviate the backpressure. For example, a processing element may reduce the data rates it sends to processing elements that are downstream in the operator graph, or processing elements and/or data paths may be eliminated. In one embodiment, processing elements and associate data paths may be prioritized so that more important execution paths are maintained.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Branson, Ryan K. Cradick, John M. Santosuosso
  • Patent number: 10324757
    Abstract: A method and computer system for scheduling, for periodic execution, a program requiring a computer hardware resource for execution. A processor of the computer system receives a request to schedule the program for execution on a day at a specified time and periodically thereafter at the specified time, and in response, the processor determines if there was historical availability of the resource exceeding a predetermined availability threshold on the day at approximately the specified time to execute the program, and if so, schedule the program for execution on the day at the specified time and periodically thereafter, and if not, not schedule the program for execution on the day at the specified time periodically. In response to a determination of no historical availability of the resource at approximately the specified time, the processor automatically determines another time on the day during which there was historical availability of the resource.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joseph M. Picinich, Loren W. Pusey, Jiyu C. Lin
  • Patent number: 10324758
    Abstract: A system for throttling includes an interface and a processor. The interface is configured to receive a read task. The processor is configured to determine a read engine of a set of read engines for the read task, submit the read task to the read engine for execution, determine whether the read task execution time exceeds a resubmit threshold time, and in the event that the read task execution time exceeds the resubmit threshold time, resubmit the read task, wherein resubmitting the read task includes determining a new read engine for the read task.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 18, 2019
    Assignee: Workday, Inc.
    Inventors: Shivender Devarakonda, Lawrence Lam
  • Patent number: 10324759
    Abstract: Techniques for secure and efficient interfacing with a cloud computing service are described. In an embodiment, a cloud computing management service is programmed or configured to communicate with a cloud computing service. The cloud computing management service can be accessed by software engineers that are looking to deploy a software instance to a computing device of the cloud computing service. Thus, the cloud computing management service acts as an intermediary layer in front of the cloud computing service. In an embodiment, the cloud computing management service may store one or more frequently-used system parameters for deployment of software instances. The parameters conform to company's security protocols, compliance protocols, and/or other standards.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: June 18, 2019
    Assignee: Palantir Technologies Inc.
    Inventors: Daniel Paquette, Huw Pryce, Alexander Feldman, Ryan Zheng, Daniel Walker, Cody Moore, Patricio Velez, Gustav Brodman, Jakub Kozlowski, Eric Wong, Steven Capetta, Charles Post, Rick White
  • Patent number: 10324760
    Abstract: The described embodiments include a computing device that has two or more levels of memory, each level of memory having different performance characteristics. During operation, the computing device receives a request to lease an available block of memory in a specified level of memory for storing an object. When a block of memory is available for leasing in the specified level of memory, the computing device stores the object in the block of memory in the specified level of memory. The computing device also commences the lease for the block of memory by setting an indicator for the block of memory to indicate that the block of memory is leased. During the lease (i.e., until the lease is terminated), the object is kept in the block of memory.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: June 18, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Mitesh Meswani
  • Patent number: 10324761
    Abstract: Techniques are described for providing clients with access to functionality for creating, configuring and executing defined workflows that manipulate source data in defined manners, such as under the control of a configurable workflow service that is available to multiple remote clients over one or more public networks. A defined workflow for a client may, for example, include multiple interconnected workflow components that are specified by the client and that each are configured to perform one or more types of data manipulation operations on a specified type of input data. The configurable workflow service may further execute the defined workflow at one or more times and in one or more manners, such as in some situations by provisioning multiple computing nodes provided by the configurable workflow service to each implement at least one of the workflow components for the defined workflow.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: June 18, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: James P. Bartlett, Richard J. Cole, Adam D. Gray, Peter Sirota