Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.

Abstract: A method and apparatus for multi-level data protection in a storage system. The storage system comprises a first storage device, a second storage device, and a third storage device, the method comprising: establishing a synchronous replication session between the first storage device and the second storage device so as to synchronously replicate data in the first storage device to the second storage device; establishing an asynchronous replication session between the first storage device and the third storage device so as to asynchronously replicate the data in the first storage device to the third storage device; and recovering the asynchronous replication by establishing an asynchronous replication session between the second storage device and the third storage device in response to a failure of the first storage device.

Abstract: Techniques for faster reconstruction of segments using a dedicated spare memory unit are described. Zone segments in memory units are associated with a dedicated spare memory unit. The zone segments are reconstructed in the dedicated spare memory unit in response to a failed memory unit except for an identified failed zone segment of the failed memory unit. The identified failed zone segment of the failed memory unit is retained in the dedicated spare unit. Other embodiments are described and claimed.

Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.

Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.

Abstract: A computer-implemented method executed by one or more processors, the method includes monitoring execution of program code executed by a first processor component; and monitoring execution of program code executed by a second processor component. A computing system stores data identifying hardware events in a memory buffer. The stored events occur across processor units that include at least the first and second processor components. The hardware events each include an event time stamp and metadata characterizing the event. The system generates a data structure identifying the hardware events. The data structure arranges the events in a time ordered sequence and associates events with at least the first or second processor components. The system stores the data structure in a memory bank of a host device and uses the data structure to analyze performance of the program code executed by the first or second processor components.

Abstract: Techniques for generating and rendering analytics data from system management data collected for multiple service domains are disclosed herein. In some embodiments, performance data are collected from multiple service domains that are each configured to determine performance metrics for one or more target system entities. The performance data for a first of the service domains is monitoring including, displaying metric objects representing variations in performance metrics for the first service domain and detecting a performance event for the first service domain, wherein the performance event is associated with a target system entity and a performance metric value. In response to said detecting the performance event, a metric object is displayed that indicates an association between an entity identifier (ID) of the target system entity and the performance metric value.

Abstract: Operations include diagnosing performance hotspots with minimal performance impact. A system selectively extracts a subset of in-memory application data, for failure analysis, based on application metadata associated with an application. The selective data extraction may be used to generate succinct reports that are customized to explore the specific vulnerabilities of each particular application. Application metadata identifies application data attributes for value extraction. The application metadata may identify, for example, a client attribute which indicates the client which requested the execution of a failed operation (or execution of an operation with a failed sub-function). The application metadata may identify a particular function, associated with an operation, that is to be analyzed in case of operation failure. The application metadata may identify a thread-local variable of a thread, executing an operation, that is to be analyzed in case of operation failure.

Abstract: Providing specialization for a static program analysis procedure by executing an automated agent to monitor a code authoring process for a program under examination that includes a plurality of respective lexical scopes. The agent monitors a corresponding amount of coding time, or a corresponding number of edits, for each of the plurality of respective lexical scopes. A mapping associates each of the plurality of respective lexical scopes with a first quantitative measure of the corresponding amount of time, or a second quantitative measure of the corresponding number of edits, that were used to code each of the plurality of respective lexical scopes. The static analysis procedure is specialized by applying a more refined, detailed, precise, or granular analysis to a first lexical scope that is mapped to a greater amount of time or a greater number of edits than a second lexical scope.

Abstract: A system and method for facilitating characterizing customized computing objects of a software application, such as a networked enterprise application. An example method includes identifying one or more custom computing objects of one or more software applications of a computing environment; determining one or more grouping criteria for grouping identified custom objects; grouping information pertaining to the one or more custom objects based on the one or more grouping criteria, resulting in one or more custom object groupings; and using the one or more custom object groupings, with reference to data characterizing one or more changes slated to be made to the software application, to generate one or more user interface display screens. In a more specific embodiment, the data characterizing one or more changes includes metadata characterizing core software application maintenance events, upgrades, and/or other modifications.

Abstract: Embodiments describe methods, apparatuses, and systems for performing data analytics on one or more features of software under development. In one exemplary embodiment, a data mining module receives a first set of data including an expected timeline of a plurality of features of program code being developed. The data mining module further retrieves a second set of data from a program testing system based on the first set of data. The second set of data includes defect information and a testing result for each of the plurality of features indicated in the first set of data. Moreover, a data analysis module executed performs an analysis on the first and second sets of data. Based on the analysis, a report generator generates an analysis report that includes an expected defect level and an actual defect level of each of the plurality of features.

Abstract: A debugging and diagnostics system allows users to take lightweight process snapshots of running debuggee processes so the users may analyze those snapshots at a later time. The snapshot mechanism allows debugging tools to compare an original process or one or more process snapshots or to compare any of a series of snapshots to each other. The snapshot mechanism further allows users to inspect a snapshot of process memory while allowing the original process to continue running with minimal impact. A user may do historical debugging using process snapshots of a debuggee process taken over time. This allows the user to view the state of the debuggee process as it existed when the snapshot was taken. The lightweight process snapshot is less invasive because it does not require a full copy of the memory and allows the original process to run un-interrupted while specific collections and inspections are completed.

Abstract: In an embodiment, a system is configured to replay and/or reconstruct execution events and system states in real time or substantially in real time starting from the point when execution of a target program has stopped to the point when the user desires to step through the target program's execution in order to debug the software. In an embodiment, a system is configured to efficiently collect trace data that is sufficient to reconstruct the state of a computer system at any point of time from the start of execution to the time execution was stopped. Efficient and effective debugging of the software can be performed using embodiments of the disclosed methods, systems, and devices.

Abstract: A source code processing application may process source code and realize the results of the code in a map configuration. In one example, the map may be displayed with a number of stations and pathways between the stations to illustrate associations with classes of the source code. An example method of operation may include one or more of retrieving source code comprising a class from memory, processing the source code to identify an error associated with the class, creating a map with a station linked to the error, and displaying the map on a device.

Abstract: Novel tools and techniques might provide for implementing application programming interface (“API”) use compliance, and, in some cases, by implementing application auditing for API use compliance within virtual environments in which target APIs are executed. In some embodiments, a method might comprise identifying misuse of an application programming interface (“API”) that is used in a developer channel, by intercepting data streams between the API and one or more computing systems, parsing the intercepted data streams, and determining whether the API is use non-compliant, based at least in part on identifying use non-compliant characteristics in the parsed data streams.

Abstract: The present disclosure relates to a method and device for automatically generating test data for testing software applications. In one embodiment, a plurality of test cases associated with test scenarios is determined by analyzing requirements of the software applications. The plurality of test cases is then processed to generate a plurality of test data scripts that are further executed on a first data source to obtain the test data. If it is determined that the execution of the plurality of test cases fail, then the plurality of test data scripts is executed on a second data source to obtain the test data. The first data source is then updated with the test data obtained for future test data requirements. Thus, the technology enables automatic generation of test data obtained from external data sources and thereby improving the testing efficiency and quality of the applications being tested.

Abstract: Techniques are described herein for generating annotated documentation of a web application based on scripts that simulate tasks performed within the web application. While running each script, an automated testing utility captures individual screens within the web application based on a first set of criteria. The first set of criteria includes capturing a screen after a page loads, before clicking on a DOM element, and before validating the occurrence of an element or event within the web application. An annotation engine then annotates each screen based on a second set of criteria. The second set of criteria includes highlighting each given screen based on the type event and location of the element that triggered the screen capture. The annotation utility additionally visualizes contextual metadata that provides the viewer with a reference of what they are looking at.

Abstract: Application testing is disclosed in the present disclosure. An interface structure may be extracted from source code of an application under test (AUT), and the interface structure may be separated into subsections. Then a primary test may be performed for the AUT by using test code to execute the subsections. An assertion strategy in the test code may be evaluated based on a predefined assertion requirement to obtain a first measurement result of the AUT, in which the assertion strategy may be to assert an execution result of the test code executing the subsections.

Abstract: Embodiments are directed to reducing the number of unit tests performed within a system. In one scenario, a computer system accesses a specified version of an application and evaluates that version of the application to identify connections between software features in the application, and to further identify defects in the software features. The computer system also determines a risk level for the software features, which indicates a likelihood of that software feature causing a software malfunction according to the identified connections or defects. The computer system further generates a feature list that includes, for at least some of the features, a corresponding ongoing risk indicator that indicates the determined likelihood of that feature causing the defect or software malfunction, and performs unit tests against the software application for those features that were indicated as sufficiently likely to cause a defect or software malfunction upon installation or upgrade of the application.

Abstract: Described are techniques for testing software. The techniques may include identifying, at a first point in time, first code that has been modified, identifying, using first mapping information, a testing set of one or more test cases wherein the first mapping information identifies each test case of the testing set as a test case used to test the first code, running the testing set, generating coverage information in accordance with executing; analyzing the coverage information, generating second mapping information in accordance with said analyzing, and updating the first mapping information in accordance with the second mapping information.

Abstract: Embodiments include a multi-stream storage device, a system including a multi-stream storage device, and a method, comprising: receiving an access to a logical address associated with a multi-stream storage device; converting the logical address into a stream identifier; and accessing the multi-stream storage device using the logical address and the stream identifier.

Abstract: A memory control device includes a host interface, a memory interface, and a controller configured to control the memory interface to output data to a non-volatile semiconductor memory for writing therein. The data include first data that the host interface received from a host, second data read out from the non-volatile semiconductor memory for memory refresh, and third data read out form the non-volatile semiconductor memory for garbage collection. When the memory refresh is not carried out, the controller adjusts a ratio of the first data with respect to the third data to be a first value. When the memory refresh is carried out, the controller calculates a second value based on the first value, and adjusts a ratio of the first data with respect to a total of the second data and the third data to be the second value.

Abstract: A method of operating a storage device managing a multi-namespace includes storing first mapping information including a mapping between a first logical address space and a first physical address space to a mapping table, in response to a request to create a first namespace, the first logical address space being allocated to the first namespace, and storing second mapping information including a mapping between a second logical address space and a second physical address space to the mapping table, in response to a request to create a second namespace, the second logical address space being allocated to the second namespace and being contiguous to the first logical address space.

Abstract: A data storage device includes a first nonvolatile memory device including first LSB, CSB and MSB pages; a second nonvolatile memory device including second LSB, CSB and MSB pages; a data cache memory is configured to store data write-requested from a host device; and a control unit suitable for configuring the first and second LSB pages as an LSB super page, configuring the first and second CSB pages as a CSB super page, and configuring the first and second MSB pages as an MSB super page, wherein the control unit is configured to one-shot programs the data stored in the data cache memory in the first LSB, CSB and MSB pages when determination is made as a data stability mode, and is configured to one-shot programs data stored in the data cache memory in the LSB, CSB and MSB super pages in a performance-improving mode.

Abstract: Garbage collection methods include adding a data object to one of multiple queues owned by a first garbage collection thread. The queues include a public queue and multiple private queues. A task is popped from one of the plurality of queues to perform garbage collection. The public queue is swapped with one of the private plurality of private queues if there are no tasks in the public queue.

Abstract: A computer-implemented method and system are provided for reducing garbage collection overhead. The method includes specifying, by a hardware processor from a set of nodes of a Directed Acyclic Graph representing an application program, wherein each of the nodes represents a respective one of a plurality of computation tasks, any of the nodes which store a respective computation result for at least a threshold period of time as cache nodes. The method further includes allocating, by the hardware processor, the respective computation result of each of the cache nodes into a tenure area of a memory.

Abstract: Systems, methods, and computer program products to manage an address translation in a virtually segmented memory system, with included processes comprising a process scoped segment table (STAB) consisting of segment table entries (STEs) that contain effective address segment number (ESID) to system wide unique virtual segment identifier (VSID) mappings, and creating a global kernel segment table (STAB) that itself is translated using a pinned page table entry (PTE). A switch to the global kernel STAB is initiated in response to a page fault interrupt on a process STAB PTE and a PTE reload handler invoked to reload that process STAB PTE. A switch to an original STAB is initiated in order to resume the address translation and resolve the page fault or the interrupt by an operating system executing on the processor.

Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.

Abstract: A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in groups, each group including at least one memory device, while the data buffer control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits, a respective buffer circuit corresponding to a respective group of memory devices. The plurality of buffer circuits are distributed across a surface of the memory module such that each data buffer control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits include clock regeneration circuits to regenerate a clock signal received from the module control device and to provide regenerated clock signals to respective groups of memory devices.

Abstract: A microprocessor comprises a plurality of queues containing transient transaction state information about cache-accessing transactions; a plurality of detectors coupled to the plurality of queues and monitoring the plurality of queues for one or more likely starvation, livelock, or deadlock conditions; and a plurality of recovery logic modules operable to implement one or more recovery routines when the detectors identify one or more likely starvation, livelock, or deadlock conditions.

Abstract: A method, computer program product, and computing system for receiving an indication of an intent to restore at least a portion of a data array based upon a historical record of the data array. One or more changes made to the content of that data array after the generation of the historical record may be identified, thus generating a differential record. One or more data entries within a cache memory system associated with the at least a portion of a data array may be invalidated based, at least in part, upon the differential record.

Abstract: Techniques are disclosed relating to memory consistency in a memory hierarchy with relaxed ordering. In some embodiments, an apparatus includes a first level cache that is shared by a plurality of shader processing elements and a second level cache that is shared by the shader processing elements and at least a texture processing unit. In some embodiments, the apparatus is configured to execute operations specified by graphics instructions that include (1) an attribute of the operation that specifies a type of memory consistency to be imposed for the operation and (2) scope information for the attribute that specifies whether the memory consistency specified by the attribute should be enforced at the first level cache or the second level cache. In some embodiments, the apparatus is configured to determine whether to sequence memory accesses at the first level cache and the second level cache based on the attribute and the scope.

Abstract: Techniques are provided for automatic placement of cache operations in a dataflow. An exemplary method obtains a graph representation of a dataflow of operations; determines a number of executions and a computational cost of the operations, and a computational cost of a caching operation to cache a dataset generated by an operation; establishes a dataflow state structure recording values for properties of the dataflow operations for a number of variations of caching various dataflow operations; determines a cache gain factor for dataflow operations as an estimated reduction in the accumulated cost of the dataflow by caching an output dataset of a given operation; determines changes in the dataflow state structure by caching an output dataset of a different operation in the dataflow; and searches the dataflow state structures to determine the output datasets to cache based on a total dataflow execution cost.

Abstract: A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.

Abstract: A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.

Abstract: A mechanism is described for facilitating independent and separate entity-based graphics cache at computing devices. A method of embodiments, as described herein, includes facilitate hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).

Abstract: Provided are techniques for a headless resilient backup and restore software ecosystem. At a first backup server of a plurality of backup servers, a connection request is received. At the first backup server, a second backup server is identified by: determining a backup server score for each of the plurality of backup servers based on identification factors comprising historical client latency, scheduled backup server workload, and whether the metadata is already cached on any of the plurality of backup servers and identifying the second backup server as having a lowest backup server score. The identification of the second backup server is returned.

Abstract: A cache system is configurable to trade power consumption for cache access latency. When it is desired for a system with a cache to conserve dynamic power, the lookup of accesses (e.g., snoops) to cache tag ways is serialized to perform one (or less than all) tag way access per clock (or even slower). Thus, for an N-way set associative cache, instead of performing a lookup/comparison on the N tag ways in parallel, the lookups are performed one tag way at a time. This take N times more cycles thereby reducing the access/snoop bandwidth by a factor of N. However, the power consumption of the serialized access when compared to ‘all parallel’ accesses/snoops is reduced.

Abstract: Facilitating recording a trace of code execution using way-locking in a set-associative processor cache. A computing device reserves cache line(s) in set(s) of cache lines of a set-associative cache for caching only locations in the system memory that are allocated to a particular executable entity. During a traced execution of the particular executable entity, the computing device detects that a cache miss has occurred on a location in the system memory that is allocated to a particular executable entity, and that a value at the location of system memory is being cached into one of the reserved cache lines. Based on the value at the location of system memory being cached into a reserved cache line, the computing device logs into a trace data stream at least a portion of the value at the location of system memory being cached into the reserved cache line.

Abstract: One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.

Abstract: The present invention provides a cache method and a cache system. The cache method includes the following steps. An instruction issuing is scheduled based on a program flow information stored in a cache system. The program flow information includes an instruction sequence information and an instruction distance information. A time point for the instruction issuing is determined based on the instruction sequence information and the instruction distance information.

Abstract: An information processing apparatus includes a storage device configured to have a first storage area disposed on a first memory, a second storage area disposed on a second memory being slower in speed than the first memory to be cached by using a capacity of a cache area exclusive of the first storage area on the first memory, and a third storage area disposed on the second memory without being cached, and a processor configured to increase a capacity of the third storage area while decreasing a capacity of the second storage area corresponding to the capacity of the cache area upon an increase of the capacity of the first storage area and a decrease of the capacity of the cache area.

Abstract: A method begins by a storage unit of a dispersed storage network (DSN) receiving access requests which include a logical DSN address and a storage function. The method continues with a first processing module of the storage unit performing logical to physical address conversions of logical DSN addresses of the access requests to physical addresses of a plurality of main memories. For a first access request of the access requests, the method continues with the first processing module identifying a first main memory based on the physical address resulting from the physical address conversion. The method continues with the first processing module identifying a first processing thread of a plurality of processing threads based on allocation of the plurality of processing threads to the plurality of main memories. The method continues with the first processing thread executing tasks of the first access request to fulfill the first access request.

Abstract: Technical solutions are described for executing one or more out-of-order instructions by a processing unit. An example method includes executing, by a load-store unit (LSU), instructions from an out-of-order (OoO) window. The OoO execution includes determining an effective address being used by a load instruction from the OoO window. Further, the execution includes determining presence of the effective address in an effective address directory (EAD) by identifying an EAD entry in the EAD, the EAD entry maps the effective address with an index of a corresponding effective-real table (ERT) entry from an effective-real table (ERT). In response to the effective address being present in the EAD, the execution includes accessing the corresponding ERT entry of the effective address of the load instruction, the corresponding ERT entry including a real address for the effective address, and issuing the load instruction using the real address from the corresponding ERT entry.

Abstract: A processing device including a linear address transformation circuit to determine that a metadata value stored in a portion of a linear address falls within a pre-defined metadata range. The metadata value corresponds to a plurality of metadata bits. The linear address transformation circuit to replace each of the plurality of the metadata bits with a constant value.

Abstract: Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.

Abstract: Certain apparatuses, systems, methods, and computer program products are used for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

Abstract: According to embodiments described herein, the hierarchical complexity for coherence protocols associated with clustered cache architectures can be encapsulated in a simple function, i.e., that of determining when a data block is shared entirely within a cluster (i.e., a sub-tree of the hierarchy) and is private from the outside. This allows embodiments to eliminate complex recursive coherence operations that span the hierarchy and instead employ simple coherence mechanisms such as self-invalidation and write-through but which are restricted to operate where a data block is shared. Thus embodiments recognize that, in the context of clustered cache hierarchies, data can be shared entirely within one cluster but can be private (unshared) to this cluster when viewed from the perspective of other clusters. This characteristic of the data can be determined and then used to locally simplify coherence protocols.

Abstract: Implementations of the disclosure provide for supporting oversubscription of guest enclave memory pages. In one implementation, a processing device comprising a memory controller unit to access a secure enclave and a processor core, operatively coupled to the memory controller unit. The processing device is to identify a target memory page in memory. The target memory page is associated with a secure enclave of a virtual machine (VM). A data structure comprising context information corresponding to the target memory page is received. A state of the target memory page is determined based on the received data structure. The state indicating whether the target memory page is associated with at least one of: a child memory page or a parent memory page of the VM. Thereupon, an instruction to evict the target memory page from the secure enclave is generated based on the determined state.