Patents Issued in June 18, 2019
  • Patent number: 10324863
    Abstract: Generally, this disclosure provides systems, methods and computer readable media for a protected memory view in a virtual machine (VM) environment enabling nested page table access by trusted guest software outside of VMX root mode. The system may include an editor module configured to provide access to a nested page table structure, by operating system (OS) kernel components and by user space applications within a guest of the VM, wherein the nested page table structure is associated with one of the protected memory views. The system may also include a page handling processor configured to secure that access by maintaining security information in the nested page table structure.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Michael Lemay, David M. Durham, Ravi L. Sahita, Andrew V. Anderson
  • Patent number: 10324864
    Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegyu Lee, Jisoo Kim, Young-Jin Park, Bo-Ram Shin
  • Patent number: 10324865
    Abstract: Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric are disclosed. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge allows writes to pass reads for a given source, but prevents reads from passing writes. The bridge forwards a write transaction out of the bridge when the write transaction is available for forwarding. The bridge forwards a read transaction from a given source out of the bridge when there are no outstanding write transactions for the given source that are older than the read transaction. The bridge prevents forwarding the read transaction from the given source out of the bridge when there are outstanding write transactions that are older than the read transaction for the given source.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: June 18, 2019
    Assignee: Apple Inc.
    Inventor: Deniz Balkan
  • Patent number: 10324866
    Abstract: An information processing apparatus includes a first, second, and third chips connected in series. The second chip includes a receiving unit, a register, a determination unit, an address translation unit, a controller unit, and a transmission unit. The receiving unit receives data and address information from the first chip. The determination unit determines whether the received address information corresponds to an address translation area based on address translation information set to the register. The address translation unit outputs translated address information to an internal bus. The controller unit controls to store data to which address information corresponding to an address area set for the second chip is attached. The transmission unit transmits to the third chip data to which address information is attached. The address translation unit translates address information corresponding to an address area set for the second chip into an address destination in the second chip.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: June 18, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akira Ichimura, Takeshi Kuga
  • Patent number: 10324867
    Abstract: Devices, systems, and methods for implementing a scalable extended basic input/output system (BIOS) region that increases the BIOS footprint of a system, are provided and described. In addition to a traditional BIOS region located in the memory mapped input/output (MMIO) low region, an extended BIOS region is initialized in a MMIO area of the system address map, where both regions are accessed by MMIO access requests.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Sivakumar Radhakrishnan, Mahesh S. Natu, Zhenyu Zhu, Malay Trivedi, Randall L. Albion, Chris Ruffin
  • Patent number: 10324868
    Abstract: The invention relates to a counting unit (100) configured to count an amount of traffic events of a data packet traffic. The counting unit comprises a counting element (131) configured to store a value representing the amount of traffic events.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: June 18, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Gabor Sandor Enyedi, László Molnár, Gergely Pongrácz
  • Patent number: 10324869
    Abstract: A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Ju Lee, Youngkwang Yoo, Youngjin Cho
  • Patent number: 10324870
    Abstract: A memory circuit having: a memory array including one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 18, 2019
    Assignee: UPMEM
    Inventors: Fabrice Devaux, Jean-François Roy
  • Patent number: 10324871
    Abstract: A first device of a Multimedia Over Coax Alliance (MoCA) network may communicate with a second device of the MoCA network to control power-save operation of the second MoCA device. The first device may control the power-save operation of the second MoCA device based on an amount of data stored in a buffer, wherein the data stored in the buffer is destined for the second device. The buffer may be in a third device which sends the data to the second device, and/or the buffer may be in the first device. The first device may be operable to buffer data destined for the second device while the second device is in a power-saving state.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: June 18, 2019
    Assignee: Maxlinear, Inc.
    Inventors: Timothy Gallagher, Glenn DeLucio, Curtis Ling
  • Patent number: 10324872
    Abstract: Systems, Methods and apparatuses relating to processor cores that respond to interrupts are disclosed. In one embodiment, an apparatus includes an interrupt interface, a memory interface; and a processor core to generate an interrupt acknowledge signal in response to a received interrupt; receive data in return; determine whether the received data is an interrupt service routine address, the interrupt service routine address being stored in an interrupt vector translation lookaside buffer; and, if not, use the received data to calculate the interrupt service routine address; wherein the processor core is further to use the interrupt service routine address to issue a request on the memory interface to fetch the interrupt service routine, and to execute the interrupt service routine.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Xiang Zou, Hong Wang, Gautham N. Chinya, Perry H. Wang
  • Patent number: 10324873
    Abstract: A device and method for communicating, via a memory-mapped communication path, between a host processor and a cellular-communication modem are disclosed. The method includes providing logical channels over the memory-mapped communication path and transporting data organized according to one or more cellular communication protocols over at least one of the logical channels. In addition, the method includes acknowledging when data transfer occurs between the host processor and the cellular-communication modem, issuing commands between the host processor and the cellular-communication modem, and communicating and managing a power state via one or more of the logical channels.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Vinod H. Kaushik, Igor Malamant, Sergio Kolor
  • Patent number: 10324874
    Abstract: A real-time operating system (OS) for an embedded system may be configured for asynchronous handling of input and output (I/O) operations. When application code is executing, the OS may be configured to register I/O interrupts and queue I/O operations. When no application code is executing, the OS may be configured to call appropriate interrupt handlers. As result, the OS may maintain the real-time execution that may be required of applications on an embedded system while providing the flexibility and scalability offered by an operating system.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 18, 2019
    Inventors: Jory Schwach, Brian Bosak
  • Patent number: 10324875
    Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: June 18, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hidemi Oyama, Masanobu Kawamura, Takuya Ikeguchi, Masanori Matsumoto, Hiroyuki Kawajiri
  • Patent number: 10324876
    Abstract: Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct data and clocking signals over the same transport medium. Embodiments are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 18, 2019
    Assignee: KANDOU LABS, S.A.
    Inventor: Amin Shokrollahi
  • Patent number: 10324877
    Abstract: USB controllers, systems and methods are presented to conserve power in a USB controller, in which a transmitter transmits data to a line of a connected USB cable according to a transmit data signal, and a pull down circuit selectively sinks current from a supply node of the transmitter when the transmit data signal is in a first state, refrains from sinking the first current from the supply node when the transmit data signal is in a different second state.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: June 18, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hassan Pooya Forghani-Zadeh, Byungchul Jang, Erick Torres, Timothy Bryan Merkin
  • Patent number: 10324878
    Abstract: In one or more embodiments, one or more systems, methods, and/or processes may detect commencement signals from respective backplanes. For each backplane of the backplanes, the one or more systems, methods, and/or processes may further configure a multiplexer to select a coupling associated with the backplane; may further provide, via a serial interface and the multiplexer, first information to the backplane; may further receive, via the serial interface, second information from the backplane; may further store the second information from the backplane; may further provide at least a portion of the second information to at least one of information handling system firmware, an operating system, and a boot management controller; and may further boot the operating system with the at least the portion of the second information associated with at least one of the backplanes.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: June 18, 2019
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Jeffrey Leighton Kennedy
  • Patent number: 10324879
    Abstract: An apparatus and method may detect and reduce noise on data busses by adjusting the phase of the input/output (I/O) signals in a controlled, predictable manner. The control may allow a maximum data rate to be achieved. In one embodiment, an algorithm used to determine phase change data may be handled by a feedback loop and may be dynamically adjusted. The system may detect noise on rails and critical signals for logging in call home data. The system may maintain a database of settings as a function of a workload. The system may be used in the field as the workload changes to determine that a signal has reached a first threshold. In response to determining that the signal has reached the first threshold, an alert is initiated. A system may determine that the signal has reached a second threshold. In response to determining that the signal has reached the second threshold, the signal may be coupled to logic circuitry.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: David D. Cadigan, Samuel R. Connor, Michael A. Cracraft, William V. Huott, Adam J. McPadden, Anuwat Saetow, Gary A. Tressler
  • Patent number: 10324880
    Abstract: A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics. A primary master central processing system is configured to couple the plurality of PCIe subfabrics and includes a primary master central processing unit.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: June 18, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Daniel Dufresne, Matthew Mullins, Antonio Fontes, Patrick J. Weiler
  • Patent number: 10324881
    Abstract: Systems and methods described herein facilitate configuration changes to an NIC teaming device while enabling multiple I/O threads continue to run through the NIC teaming device concurrently without interruption. At a given time, multiple configurations of the NIC teaming device, e.g., one for a current configuration of the NIC teaming device and one for a new configuration of the NIC teaming device, can co-exist. For the duration of one iteration, the current configuration of the NIC teaming device used by a specific I/O thread does not change and the new configuration of the NIC teaming device is not adopted by the I/O thread until the start of the next iteration. Once all of the I/O threads finish their current iteration, the configuration of the NIC teaming device is flipped from the current configuration to the new configuration and the current configuration is deleted.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: June 18, 2019
    Assignee: NICIRA, INC.
    Inventors: Jia Yu, Ronghua Zhang
  • Patent number: 10324882
    Abstract: An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: William R. Halleck, Rahul R. Shah, Venkatraman Iyer
  • Patent number: 10324883
    Abstract: This invention expands the scope of application of a pass-through technology in which a guest OS directly controls a remote device that is connected via a network. This data-processing apparatus is provided with a host OS that provides a virtual hardware environment to a guest OS that performs I/O processing with respect to a device implemented in a remote apparatus connected via a network. The host OS has a bus extension unit that traps I/O instructions issued by the guest OS, encapsulates the trapped I/O instructions, and delivers the encapsulated I/O instructions to the remote apparatus as network packets.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: June 18, 2019
    Assignee: NEC Corporation
    Inventors: Masahiko Takahashi, Youichi Hidaka
  • Patent number: 10324884
    Abstract: Technology is provided for a memory drive adapter. The memory drive adapter is used for combining memory drives within an alternative form factor. For example the memory drive adapter can include an adapter frame configured for compatibility with a peripheral component interface. The adapter frame can include first and second spaced apart cover panels. A mounting panel extends between the first and second cover panels. An end panel is positioned opposite the mounting panel and extends between the first and second cover panels. One or more divider tabs extend between the first and second cover panels substantially midway between the mounting panel and the end panel to define a pair of drive bays, each configured to receive a 2.5-inch solid state drive.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 18, 2019
    Assignee: Facebook, Inc.
    Inventor: Jon Brian Ehlen
  • Patent number: 10324885
    Abstract: A display device of an addin card generally includes, in structure, an addin card, a display device, a control board, and control software. The addin card is in information connection with the display device and the control board. The control software is loaded in the control board and is in information connection with the addin card. The display device access and reads hardware status data of the addin card, such as an operation temperature, a fan rotational speed, and a processing frequency. As such, in an attempt to observe the current hardware status data of the addin card, a user is allowed to make direct observation of the data on the display device without activating the control software. To change the operation performance of the addin card, the user may operate the control software to control the addin card, without entering BIOS, this being very convenient for the user.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 18, 2019
    Assignee: EVGA CORPORATION
    Inventor: Tai-Sheng Han
  • Patent number: 10324886
    Abstract: The invention relates to a holding device for securing at least one first expansion card in a rack server slot of one height unit. Incidentally, the holding device comprises a base body and a first holding tab, which is arranged on a first side of the base body. The first holding tab is configured to secure a riser card and a module to the holding device. Furthermore, the holding device comprises at least one second holding tab located on a second side of the base body opposite the first side. The at least one second holding tab is configured to secure a first expansion card to the holding device. Furthermore, the invention relates to an assembly having a holding device and a rack server slot of one height unit.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: June 18, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Gerhard Mühsam, Reinhard Salmen
  • Patent number: 10324887
    Abstract: A supercomputer comprising a memory device and a plurality of interconnected hardware processors capable of performing parallel processing is coupled to a mainframe computer comprising one or more hardware processors. The supercomputer functions as a part of the mainframe computer's memory hierarchy.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Thomas Ward, Blake Fitch
  • Patent number: 10324888
    Abstract: An apparatus, system, method, and program product for verifying a communication bus connection to a peripheral device are disclosed. The apparatus includes a data module that receives, over a communication bus, an identifier for a location where a peripheral device is installed. The peripheral device is communicatively coupled to an information handling device using the communication bus. The apparatus includes a verification module that compares the identifier received over the communication bus to a predefined identifier associated with the communication bus. The apparatus includes a notification module that sends a notification in response to the identifier received over the communication bus not matching the predefined identifier associated with the communication bus.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: June 18, 2019
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD
    Inventors: Luke Remis, Mark E. Andresen, Wilson Velez
  • Patent number: 10324889
    Abstract: Ringing on the clock line on a synchronous serial data bus limits the maximum distance between the clock transmitter and receiver. The present disclosure provides a serial transmission protocol and a synchronous serial data bus for long distance serial data transmission between the clock source and the clock receiver that tolerates ringing on the transmission lines by constructing the clock signal at the receiver end of the link.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: June 18, 2019
    Assignee: Demand Peripherals, Inc.
    Inventor: Robert Smith
  • Patent number: 10324890
    Abstract: A cache management system performs cache management in a Remote Direct Memory Access (RDMA) key value data store. The cache management system receives a request from at least one client configured to access a data item stored in a data location of a remote server, and determines a popularity of the data item based on a frequency at which the data location is accessed by the at least one client. The system is further configured to determine a lease period of the data item based on the frequency and assigning the lease period to the data location.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michel H. Hack, Yufei Ren, Yandong Wang, Li Zhang
  • Patent number: 10324891
    Abstract: Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip™ (HSIC) interface are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 18, 2019
    Assignee: Apple Inc.
    Inventors: Daniel Wilson, Anand Dalal, Josh De Cesare
  • Patent number: 10324892
    Abstract: Methods, apparatuses, and embodiments related to improving security of data that is stored at a data store distributed over a computer network. In an example, source data to be protected is partitioned into multiple files, and each file is obfuscated, such as by being encrypted, to created multiple obfuscated data files. Information as to how each obfuscated data file was obfuscated is stored in an associated trace file. The multiple obfuscated data files are moved around a computer network via a data movement process that includes sending each of the multiple obfuscated data files to a different randomly selected computer, where the computer further obfuscates the obfuscated data the trace file, and sends the further obfuscated data and trace file to a next randomly selected computer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 18, 2019
    Assignee: CRYPTOMOVE, INC.
    Inventor: Boris Burshteyn
  • Patent number: 10324893
    Abstract: The present disclosure provides for analyzing data stored in a data protection storage system to determine a prospective storage scheme that provides a more efficient use of storage resources in the data protection storage system. Data can be analyzed to identify a set of data suitable for long term storage in an archive. Data can be analyzed to identify a set of data suitable for deletion to reduce duplicate copies of data, and remove expired data. Protection policies that provide double coverage of data, causing additional inefficient storage of data, can be identified. A prospective amount of freed storage and other savings can be calculated, if all or part of the prospective storage scheme is implemented, where the prospective amount of freed storage and other savings can be displayed to in a report. A prospective storage scheme may also be determined for a client system that stores live data.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: June 18, 2019
    Assignee: Veritas Technologies LLC
    Inventor: Nilesh Telang
  • Patent number: 10324894
    Abstract: A storage device management method, a storage device management system and a memory storage device are provided. The method includes establishing multiple first temporary files in a first directory before receiving a setting instruction from a host, wherein the first temporary files are stored in multiple consecutive clusters of a file system and an operating system of the host is unable to access files in the first directory. The method further includes receiving the setting instruction from the host, wherein the setting instruction instructs to configure a temporary file directory in a second directory and the operating system of the host is able to access files in the second directory. The method further includes linking a cluster number of the consecutive clusters storing the first temporary files to the temporary file directory in the directory area corresponding to the file system.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: June 18, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Jen-Feng Yeh
  • Patent number: 10324895
    Abstract: An approach for generating an index in Darwin Information Typing Architecture (DITA) source files. The approach determines a gerund-noun listing based, at least in part, on one or more files. The approach determines a prioritized index of the gerund-noun listing. The approach determines one or more similar index entries of the prioritized index. The approach determines whether a fraternal association exists between at least two of the one or more similar index entries. Responsive to a determination that a fraternal association exists between at least two of the one or more similar index entries, the approach determines whether an inheritance from a parent exists. The approach determines based, at least in part, on whether a fraternal association exists and whether an inheritance from a parent exists, a DITA index.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Balaji S. Kumar, Vishal G. Palliyathu
  • Patent number: 10324896
    Abstract: A method and an apparatus for acquiring a resource. An embodiment of the present invention provides a method for acquiring a resource, including receiving, by a storage server, a resource check request sent by a first client, where the resource check request carries resource information of a resource to be uploaded by the first client, an identifier of an external link created by a second client, and storage location information corresponding to the external link; searching, by the storage server, according to the identifier, a database configured to store external-link information for an attribute of the external link corresponding to the identifier of the external link, and checking the resource information according to a value of the found attribute; and if the check succeeds, storing, by the storage server the acquired resource or acquired resource location information according to the storage location information.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 18, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jin Zhang, Changting Wang
  • Patent number: 10324897
    Abstract: A system for providing user access to electronic mail includes an email client and an email server. The email client receives and communicates a user interaction with an email message The email server that receives the communication, determines whether the email message stored in a live database or in a backup storage. Upon determination that the email message is stored in a backup storage, the email server performs a message exchange with a backup storage system to perform the user-requested action.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: June 18, 2019
    Assignee: Commvault Systems, Inc.
    Inventors: Arun Prasad Amarendran, Jun H. Ahn, Tirthankar Chatterjee, Manas Bhikchand Mutha, Ho-chi Chen, Prosenjit Sinha, Yongtao Liu
  • Patent number: 10324898
    Abstract: Provided are techniques for parallel container and record organization using buckets. In response to receiving an update to an entity in a file plan, a date associated with a disposition of the entity is determined and a reference to the entity is added to a bucket associated with the date.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruen R. Dineros, Jeffrey L. Wallace, Li Zhou
  • Patent number: 10324899
    Abstract: The selection and presentation of representative image content items and textual content. In one aspect, the present invention relates to the selection of one or more image/video content items that are likely to represent well a group of image/video content items. In another aspect, the present invention relates to presentation of the selected content items are discussed. In yet another aspect, the present invention relates to the composition of textual characterizations of content.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: June 18, 2019
    Assignee: NOKIA TECHNOLOGIES OY
    Inventors: Antti Sorvari, Jukka-Pekka Salmenkaita, Joonas Paalasmaa
  • Patent number: 10324900
    Abstract: Systems and methods including a database server application integrated with a non-volatile memory-based cache. The database system is configured for accelerating file system data file accesses of the database server application. The user can specify caching requirements in the terminology of the database server application. The system translates the specified caching requirements into cache directives and implements the cache directives in the non-volatile memory-based cache that satisfy the specified caching requirements.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: June 18, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yaron Klein, Allon Leon Cohen
  • Patent number: 10324901
    Abstract: In accordance with embodiments, there are provided mechanisms and methods for sharing tenant information utilizing a multi-tenant on-demand database service. These mechanisms and methods for sharing tenant information utilizing a multi-tenant on-demand database service can allow automatic sharing of information owned by a first tenant with other tenants of the multi-tenant on-demand database service. In this way, collaboration among tenants of the multi-tenant on-demand database service may be enabled via the sharing of the tenant information.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: June 18, 2019
    Assignee: salesforce.com, inc.
    Inventors: Aditya S. Kuruganti, Kedar Doshi, Chaitanya Bhatt, Sanjaya Lai
  • Patent number: 10324902
    Abstract: Embodiments of the present disclosure relate to a method and apparatus for locking a file in a memory. The method comprises enabling a thread to obtain a mixed lock of a file. The method further comprises, in response to enabling the thread to obtain the mixed lock, enabling a further thread to obtain a shared lock of the file, and prevent the further thread from obtaining the exclusive lock or mixed lock of the file. By adding a new mixed lock to a traditional read and write lock, embodiments of the present disclosure improve concurrent access performance of the file system.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: June 18, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Lester Ming Zhang, Denny Dengyu Wang, Chen Gong, Ted Guangkai Zhang, Donglei Wang, Bean Bin Zhao
  • Patent number: 10324903
    Abstract: The disclosed technology relates to a system configured to obtain a set of tree data structures including a remote tree representing a server state of content items associated with a user account on a content management system, a local tree representing a file system state of content items associated with the user account on a client device, and a sync tree representing a known sync state between the content management system and the client device. The system is configured to determine that the user account on the content management system includes at least one modification not synchronized to the client device by comparing the remote tree and the sync tree.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 18, 2019
    Assignee: Dropbox, Inc.
    Inventors: Isaac Goldberg, Elmer Charles Jubb, IV, Sujay Jayakar, John Lai, Robert Ying, Nipunn Koorapati, Gautam Gupta, Geoffry Song
  • Patent number: 10324904
    Abstract: Examples are generally directed towards converting complex structure attributes into flattened data. A configuration capture component analyzes a set of objects associated with a set of complex structure attributes. A complex structure attribute is an attribute of an object that is an array attribute or a nested object attribute. The configuration capture component performs a hash type conversion to convert nested object attributes into flattened data. The configuration capture component performs an array type conversion to convert nested array attributes into flattened data. The flattened data is stored or imported in a set of flattened data files. An expansion component converts the flattened data files back into the complex structure attributes without losing or corrupting the complex structure data.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: June 18, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Eric Wu, Jing Ding, Yourong Wang, Yujie Xie, Yingyan Zheng, Zhidong Mao
  • Patent number: 10324905
    Abstract: A particular node of a journal-based multi-node distributed storage system requests the addition of an acceptability verification request entry to the journal, indicating a proposed state change of the system. The particular node examines contents of entries added to the journal after the acceptability verification request entry. After determining that a targeted set of acceptability verification response entries have been added to the journal, indicating that the potential state change meets acceptance criteria at respective other nodes of the system, the particular node requests an addition of a committed transaction entry to the journal, indicating an approval of the proposed state change.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: June 18, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Andrew Wayne Ross, Artem Danilov, Timothy Daniel Cole, Tate Andrew Certain, Christopher Richard Jacques De Kadt, John Michael Morkel, Allan Henry Vermeulen
  • Patent number: 10324906
    Abstract: An XML fragmenting mechanism uses an XML schema for the XML file to split up the XML file in a hierarchal structure of data blocks for storage in a storage system with a limited block size such as a cluster coordination service. The XML fragmenting mechanism creates an XML file map to document the structure of the XML file in the storage system. The XML fragmenting mechanism stores the data blocks in the storage system according to the XML file map and supports retrieval of all or part of the data in a format that supports XML validation.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventor: David M. Koster
  • Patent number: 10324907
    Abstract: It is decided whether to increase a total amount of storage in a pool of Hadoop storage and whether to increase a total amount of processing in a pool of Hadoop processing. If it is decided to increase the total amount of storage and not increase the total amount of processing, the total amount of storage is increased without increasing processing. If it is decided to not increase the total amount of storage and increase the total amount of processing, the total amount of processing is increased without increasing storage. In response to receiving a request to perform a process on a set of data, processing is allocated from the pool of processing and storage is allocated from the pool of storage where the allocated processing and storage are used to perform the process on the set of data.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: June 18, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Hamid R. Djam, Craig Stewart, Michael Hancock, Qiyan Chen, Feng Guo, Kay Yan, Dong Xiang
  • Patent number: 10324908
    Abstract: Various examples are directed to exposing database artifacts. For example, a rules engine may receive schema data describing a database schema of an in-memory database. The schema data may describe a table, a view, and a procedure. The rules engine may generate a data model comprising a plurality of translation artifacts including a table translation artifact describing a table of the database schema, a view translation artifact describing a view of the database schema, and a procedure translation artifact describing a procedure of the database schema. A mapping service may receive from a client application a first client request comprising first metadata describing the view translation artifact. The mapping service may initiate execution of the view at an in-memory database to determine a view result; and send the view result to the client application.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: June 18, 2019
    Assignee: SAP SE
    Inventors: Apoorva Kumar, Suresh Pasumarthi, C Sachin
  • Patent number: 10324909
    Abstract: In a computing resource environment including at least two different resource name spaces, a method for generating a fully-qualified name for a resource based on a context-based name of that resource and a usage context is disclosed. Method steps include receiving the resource's name schema, its context-based name, and usage context; comparing an entry in the schema and an entry in the context-based name and identifying schema monikers missing from the context-based name. For a missing moniker, determining whether it is an attribute space (aspace) moniker. If it is an aspace moniker, adding it to a full name that includes the context-based name. If it is not an aspace moniker, determining the aspace associated with the missing moniker; searching the usage context for an association between the missing moniker, its aspace, and a value assigned to the missing moniker; and appending the searched-for items to the full name.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 18, 2019
    Assignee: Google LLC
    Inventors: John Wilkes, Indranil Gupta, Walfredo Cirne, Brian Grant, Todd Pu-Tse Wang
  • Patent number: 10324910
    Abstract: A contact record processing method includes: detecting whether a use time of a phone number stored in a contact record is greater than a use term of the phone number; and deleting the phone number from the contact record when the use time is greater than the use term.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: June 18, 2019
    Assignee: Xiaomi Inc.
    Inventors: Guilin Liu, Changliang Wu, Peng Zhang
  • Patent number: 10324911
    Abstract: An apparatus in one embodiment comprises a storage system that includes a database. A controller associated with the storage system is configured to perform rebalancing of bucket contents tables for respective buckets of the database where each such bucket contains a plurality of objects stored within the database. A given one of the bucket contents tables for a particular one of the buckets comprises a plurality of rows each associated with a different hash key. The given bucket contents table further comprises a plurality of columns each associated with multiple objects stored within the database. Each such object has a corresponding object key and is associated with a particular entry of the bucket contents table that includes metadata for that object. The controller illustratively performs the rebalancing of the given bucket contents table using adaptive partitioning of object key ranges associated with respective rows of the given bucket contents table.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 18, 2019
    Assignee: Virtustream IP Holding Company LLC
    Inventors: Andrey Smirnov, Artem Chernyshev, Ming Zhang, Braden Gibson
  • Patent number: 10324912
    Abstract: In accordance with aspects of the disclosure, systems and methods are provided for normalizing data representing entities and relationships linking the entities including defining one or more graph rules describing searchable characteristics for the data representing the entities and relationships linking the entities, applying the one or more graph rules to the data representing the entities and the relationships linking the entities, identifying one or more matching instances between the one or more graph rules and the data representing the entities and the relationships linking the entities, and performing one or more actions to update the one or more matching instances between the one or more graph rules and the data representing the entities and the relationships linking the entities.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: June 18, 2019
    Assignee: BMC Software, Inc.
    Inventors: Ajoy Kumar, Douglas Mueller, Josie George