Patents Issued in June 18, 2019
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Patent number: 10325015Abstract: Conversion of data ranges to table objects in an electronic spreadsheet document is provided. When an electronic spreadsheet document is being utilized, data ranges may be automatically converted to tables to allow the user to enjoy the full benefits of the table properties and functionalities. When a data range is automatically converted to a table object, a user will be given an opportunity to revert the table object back to the data range from which it was converted. Instead of automatic conversion, a suggestion may be provided to a user before a data range is converted to a table object. If the user accepts the suggestion, then the data range may be automatically converted to a table object.Type: GrantFiled: June 19, 2018Date of Patent: June 18, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Allison Jane Rutherford, Uhl Albert, John Campbell, Aaron Lamar Wilson
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Patent number: 10325016Abstract: Computer-based processes are disclosed for analyzing and improving document readability. Document readability is improved by using rules and associated logic to automatically detect various types of writing problems and to make and/or suggest edits for eliminating such problems. Many of the rules seek to generate more concise formulations of the analyzed sentences, such as by eliminating unnecessary words, rearranging words and phrases, and making various other types of edits. Proposed edits can be conveyed, e.g., through a word processing platform, by changing the visual appearance of text to indicate how the text would appear with (or with and without) the edit.Type: GrantFiled: October 15, 2018Date of Patent: June 18, 2019Assignee: WordRake Holdings, LLCInventor: Gary W. Kinder
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Patent number: 10325017Abstract: A computer-based system and method for intelligent resume search on online repositories is disclosed. The parameters in the resumes and the attributes related to the said parameters are identified and extracted by scanning the resumes sequentially and are stored in an index file. Search queries are constructed based on accepted query parts as input. The index file is indexed to locate the parameters relevant to the search queries. An initial score is assigned to the parameters located which is transformed to new score based on identifying additional domain intelligence in the derived attributes related to the located parameters. Finally, the resumes relevant to the parameters with the transformed score are retrieved and displayed.Type: GrantFiled: February 10, 2012Date of Patent: June 18, 2019Assignee: TATA CONSULTANCY SERVICES LIMITEDInventors: Rajiv Radheyshyam Srivastava, Girish Keshav Palshikar
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Patent number: 10325018Abstract: A first handwriting input is received comprising strokes corresponding to a set of first characters comprising one or more first characters forming a first language model unit. A set of candidate first characters and a set of candidate first language model units with corresponding probability scores are determined based on an analysis of the one or more sets of candidate first characters using the first language model and a corresponding first character recognition model. When no first probability score satisfies a threshold, one or more sets of candidate second characters and a set of candidate second language model units are determined based on an analysis of the first handwriting input using a second language model and a corresponding second character recognition model. A first candidate list is then output comprising at least one of the set of candidate second language model units.Type: GrantFiled: October 17, 2016Date of Patent: June 18, 2019Assignee: Google LLCInventors: Marcos Calvo, Victor Carbune, Henry Rowley, Thomas Deselaers
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Patent number: 10325019Abstract: The present disclosure is descriptive of discovering structure, content, and context of a media event, e.g., a live media event, using real-time discussions that unfold through short messaging services. Generally, a sampling of short messages of a plurality of users is obtained. The sampling of short messages corresponds to a media event. A segment in the media event is identified using the sampling of short messages, and at least one term taken from the sampling of short messages is identified. The at least one term is indicative of a context of the identified segment.Type: GrantFiled: July 17, 2017Date of Patent: June 18, 2019Assignee: EXCALIBUR IP, LLCInventors: David Ayman Shamma, Lyndon Kennedy, Elizabeth F. Churchill
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Patent number: 10325020Abstract: Systems and methods for identifying an adverse effect of a pharmaceutical substance are provided. A system may tokenize an electronic medical record for a plurality of tokens. The system may further generate a distance score between a first vector of a word embedding model and a second vector of the word embedding model. The first vector may correspond to a substance token and the second vector may correspond to a condition token. The system may further detect an absence of a preventative association between the substance token and the condition token in a prevention repository. The system may further generate a causal link indication indicative of a causal link between the substance token and the condition token in response to the distance score being greater than a threshold value and detection of the absence of the preventative association between the substance token and the condition token.Type: GrantFiled: June 29, 2017Date of Patent: June 18, 2019Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITEDInventors: Orlaith Burke, Md Faisal Zaman, John Vard, April Davis, Nut Limsopatham
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Patent number: 10325021Abstract: A system and method for extracting a relevant phrase from text. The system and method may build a plurality of n-gram phrases using a seed from a seed list as a start, a middle, or an end of each n-gram phrase. The seed list may be directed to a specific vehicle system and each seed may indicate a symptom, part, or action to extract relevant phrases from vehicle information verbatims. The plurality of n-gram phrases may be filtered to obtain one or more relevant phrases. The filtering process may include calculating an external relevance factor, an internal relevance factor, or a context pattern relevance factor.Type: GrantFiled: June 19, 2017Date of Patent: June 18, 2019Assignee: GM Global Technology Operations LLCInventors: Prakash Mohan Peranandam, Soumen De
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Patent number: 10325022Abstract: A system is capable of automatically adjusting or reconstructing a baseline expression to generate a parallelized expression. Evaluation of the parallelized expression provide a substantially similar output as the evaluation of the baseline query in more efficient manner. In some implementations, data indicating an expression to be evaluated on a primary thread of the one or more processors is obtained. Elements of the expression are identified. The elements are grouped into a parse tree representation. Elements of the expression are classified as belonging to either a first category that includes elements that are eligible for parallel processing or a second category that includes elements that are not eligible for parallel processing. A particular element that is classified as belonging to the first category is identified and evaluated on a non-primary thread of the one or more processors. The non-primary thread is evaluated in parallel with the primary thread.Type: GrantFiled: March 13, 2018Date of Patent: June 18, 2019Assignee: Appian CorporationInventors: Brian Joseph Sullivan, Matthew David Hilliard
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Patent number: 10325023Abstract: A method is provided for controlling a device based on acquired text data. The method includes acquiring the text data indicating a voice spoken by a user, and analyzing a meaning of the text data based on a table, in which a word and a vector representing a meaning of the word in a vector space of predetermined dimensions are associated. The method also includes generating a command to control the device based on the analyzed meaning of the text data. The table is generated by performing a learning process by assigning to a first word a first vector representing a meaning of the first word in the vector space, and by assigning to a second word a second vector representing a meaning of the second word in the vector space, in accordance with an arrangement of a word string in a first text corpus and a second text corpus.Type: GrantFiled: May 18, 2018Date of Patent: June 18, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Katsuyoshi Yamagami, Takashi Ushio, Yasunori Ishii
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Patent number: 10325024Abstract: Embodiments relate to an intelligent computer platform to provide a contextual analogy response. The aspect of providing a contextual analogy response includes receiving a communication that includes an analogy. The analogy within the communication is identified and parsed into grammatical components. The grammatical components are utilized to identify a meaning of the analogy that correlates to a response statement. The grammatical structure of the analogy is analyzed and then utilized together with the grammatical components to construct an analogy representation. A response is communicated as output including both the response statement together with the analogy representation.Type: GrantFiled: November 30, 2016Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Corville O. Allen, Andrew R. Freed
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Patent number: 10325025Abstract: Embodiments relate to an intelligent computer platform to provide a contextual analogy response. The aspect of providing a contextual analogy response includes receiving a communication that includes an analogy. The analogy within the communication is identified and parsed into grammatical components. The grammatical components are utilized to identify a meaning of the analogy that correlates to a response statement. The grammatical structure of the analogy is analyzed and then utilized together with the grammatical components to construct an analogy representation. A response is communicated as output including both the response statement together with the analogy representation.Type: GrantFiled: November 30, 2016Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Corville O. Allen, Andrew R. Freed
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Patent number: 10325026Abstract: A technique for generating a new equivalent phrase for an input phrase includes receiving a first input phrase for natural language expansion. Tokens that correspond to parts of speech are generated for the first input phrase. An original grammar tree is generated using at least some of the tokens. One or more alternate grammar trees are generated that are different from the original grammar tree but substantially equivalent to the original grammar tree. One or more synonyms for at least one of the tokens are generated. Finally, one or more new phrases are generated based on the one or more alternate grammar trees and the one or more synonyms.Type: GrantFiled: September 25, 2015Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventor: Bryan D. Cardillo
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Patent number: 10325027Abstract: An approach is provided for changing a language for a replay of a session of a user. Data from requests and responses of the session is captured. Based on the captured data, an initial language of content presented to the user in the session is determined. A selection by an analyst of a preferred language for the replay of the session is obtained. It is determined whether the preferred language matches the initial language. If the preferred language does not match the initial language, the captured data is translated from the initial language into the preferred language and the session is replayed by presenting the content in the preferred language and not in the initial language. The replayed session is viewed by the analyst. If the preferred language matches the initial language, the session is replayed by presenting the content in the initial language, without translating the captured data.Type: GrantFiled: February 7, 2017Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Sunil Chelani, Malarvizhi Kandasamy, Mali Hansraj, Mohammad N. Nazmi
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Patent number: 10325028Abstract: Systems, methods, and tangible, non-transitory, computer readable media is described herein. For example, a system includes a portable non-destructive testing (NDT) device. The NDT device includes a display, a user interface, a memory storing an operations object having a first text in a first language, and a processor. The processor is configured to present the first text on the operations object via the display during an operation of the portable NDT device, and wherein the processor is configured to create a second text in a second language via the user interface of the NDT device, and to present the second text on the operations object as an alternative to the first text via the display during the operation of the NDT device.Type: GrantFiled: September 19, 2017Date of Patent: June 18, 2019Assignee: General Electric CompanyInventors: Chen Goldberger, Bryan David Maule, Thomas Charles Ward, Thomas Durkee Britton
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Patent number: 10325029Abstract: A respective volatility attribute associated with each of one or more tables of a computerized database is used in any of various aspects to (a) determine how table data is stored in a physical storage device; (b) regulate the use of a materialized query table using database table data; and/or (c) influence circumstances under which indexes are created or advised by database analytic software. Various optional additional uses of a volatility attribute to manage a database are disclosed. Preferably, database parameters are automatically monitored over time and database table volatility state is automatically determined and periodically adjusted.Type: GrantFiled: December 10, 2014Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Rafal P. Konik, Roger A. Mittelstadt, Brian R. Muras, Mark W. Theuer
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Patent number: 10325030Abstract: Embodiments of the systems and methods disclosed include a durable multiversion modification of B+-tree with full transaction semantics. In-memory and persistent page images are managed without a buffer manager. Instead, a non-leaf page downlink directly points either to in-memory or on-disk pages. In turn, the reduced amount of fetches per page access improves scalability on multi-core hardware platforms. Embodiments include structurally consistent copy-on-write checkpoints that enable using row-level write-ahead logs. In combination with in-memory undo log for multiversion concurrency control, the amount of persistent storage operations is significantly reduced.Type: GrantFiled: June 25, 2018Date of Patent: June 18, 2019Assignee: Oriole DB Inc.Inventor: Alexander Evgenievich Korotkov
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Patent number: 10325031Abstract: Embodiments of methods and/or systems of manipulating tree expressions are disclosed.Type: GrantFiled: August 29, 2016Date of Patent: June 18, 2019Assignee: Robert T. and Virginia T. Jenkins as Trustees of the Jenkins Family Trust dated Feb. 8, 2002Inventor: Jack J. LeTourneau
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Patent number: 10325032Abstract: Example resource provisioning systems and methods are described. In one implementation, an execution platform accesses multiple remote storage devices. The execution platform includes multiple virtual warehouses, each of which includes a cache to store data retrieved from the remote storage devices and a processor that is independent of the remote storage devices. A resource manager is coupled to the execution platform and monitors received data processing requests and resource utilization. The resource manager also determines whether additional virtual warehouses are needed based on the data processing requests and the resource utilization. If additional virtual warehouses are needed, the resource manager provisions a new virtual warehouse.Type: GrantFiled: October 20, 2014Date of Patent: June 18, 2019Assignee: SNOWFLAKE INC.Inventors: Benoit Dageville, Thierry Cruanes, Marcin Zukowski
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Patent number: 10325033Abstract: A computer-implemented method of determining a content score of resource content comprises receiving one or more main topics highly relevant to the resource content; receiving the resource content; determining, using the one or more main topics, a content score value indicating the content score; and outputting the determined content score value, a corresponding system, computing device and non-transitory computer-readable storage medium.Type: GrantFiled: October 28, 2016Date of Patent: June 18, 2019Assignee: SEARCHMETRICS GMBHInventors: Alexander Kagoshima, Kai Londenberg, Fang Xu
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Patent number: 10325034Abstract: An analyzer refers to information included in a recorded product drawing, builds a part of or the entire wire harness by drawing corresponding graphic data of each member constituting the wire harness, adds non-corresponding graphic data to the built wire harness, and displays the product drawing.Type: GrantFiled: November 25, 2015Date of Patent: June 18, 2019Assignee: YAZAKI CORPORATIONInventors: Yasuhiro Saki, Yuya Saito, Shin Urano
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Patent number: 10325035Abstract: Certain embodiments include a computer-implemented method that includes receiving image data corresponding to a three-dimensional (3D) parametric model, receiving a selection of a scope of the 3D model, receiving a selection of one or more base lines for the scope, determining a slip type for the scope, calculating planes of the scope, calculating candidate dimension lines, selecting a dimension line of the candidate dimension lines based on dimension line placement rules, and displaying the selected dimension line adjacent to the scope that correspond to the selected one or more base lines. The calculated planes of the scope can be based on the one or more base lines and the slip type. The calculated candidate lines can be based on the calculated planes and dimension line placement guidelines.Type: GrantFiled: March 17, 2016Date of Patent: June 18, 2019Assignee: ENVIRONMENTAL SYSTEMS RESEARCH INSTITUTE (ESRI)Inventors: Tom Kelly, Pascal Mueller
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Patent number: 10325036Abstract: A method for determining a welding sequence including a plurality of welding operations is disclosed. The method includes steps of determining a population of welding sequences based on a set of user-generated constraints, and simulating welding for at least one welding sequence in the population of welding sequences to obtain a multi-objective dependent distortion model of the at least one welding sequence. The method further includes steps of comparing a merit value of the multi-objective dependent distortion model for the at least one welding sequence with one or more predetermined criteria, and outputting a set of welding sequences as potential welding sequences based on the comparison between the merit value and the multi-objective dependent distortion model.Type: GrantFiled: March 7, 2016Date of Patent: June 18, 2019Assignee: Caterpillar Inc.Inventors: Vijay K. Yalamanchili, Justin C. Mach, Joshua D. Webb, Julian Norato, Badrinarayan P. Athreya
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Patent number: 10325037Abstract: A system for analyzing one or more operations associated with a component of a machine is disclosed. The system includes a data warehouse for storing data associated with the machine. The system includes a data extraction module, which extracts the data from the data warehouse and receives a customer input. The data extraction module generates an input parameter based on the data from the data warehouse and the customer input. The system includes a failure injection module for storing information of the one or more failures associated with the component of the machine. The system also includes a machine model, which is in communication with the data extraction module and the failure injection module. The machine model derives an output parameter associated with the one or more operations of the component of the machine, based on the input parameter and the information of the one or more failures.Type: GrantFiled: April 28, 2016Date of Patent: June 18, 2019Assignee: Caterpillar Inc.Inventors: Evan E. Jacobson, Qiang Chen, Michael D. Anderson, Nathan S. Pauli, Benjamin J. Hodel
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Patent number: 10325038Abstract: A method of simulating shaping a textile strip by winding on a mold presenting a surface of revolution is described. The textile strip is made by three-dimensional weaving between a plurality of layers of warp yarns and a plurality of layers of weft yarns, the warp yarn layers being interlinked by the weft yarn layers. For each warp yarn layer, the method includes positioning crossing points between at least some of the warp yarns of the warp yarn layer and at least some of the weft yarns, the warp yarns of the at least some of the warp yarns including a reference warp yarn having a determined axial position on the mold.Type: GrantFiled: January 29, 2015Date of Patent: June 18, 2019Assignee: SAFRAN AIRCRAFT ENGINESInventors: Francis Barreau, Yann Didier Simon Marchal
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Patent number: 10325039Abstract: A method and a computer programme product for virtually inspecting an actual produced part, comprising providing an ideal Finite Element (FE)-mesh corresponding to an ideal produced part, said ideal produced part comprising two or more mounting places, by measuring the actual produced part, generating a numerical representation of the actual produced part, generating an actual FE-mesh by modifying the ideal FE-mesh such that the shape of the ideal FE-mesh adapts to the numerical representation of the actual produced part, and performing an FE-analysis, by forcing the actual FE-mesh into position by constraining the mounting places of the actual FE-mesh, and determining a deformation of the actual FE mesh resulting from its constraint.Type: GrantFiled: March 28, 2017Date of Patent: June 18, 2019Assignee: HEXAGON TECHNOLOGY CENTER GMBHInventors: William Wilcox, Derek Peeling
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Patent number: 10325040Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine two or more input sequences of signal transition representations associated with an input net of an indicated component in an RTL circuit design, where the two or more input sequences of signal transition representations are associated with a mode element. Each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). The mode element indicates a selection between two or more output sequences of signal transition representations. It is determined, based on the indicated component and the mode element, two or more output sequences of signal transition representations derived from the input sequence(s) of signal transition representations.Type: GrantFiled: November 19, 2014Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10325041Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in a register transfer level circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to one or more possible signal states. Determining the input sequence of signal transition representations includes determining that a subsequence of the input sequence of signal transition representations indicates at most one transition within the subsequence of the input sequence.Type: GrantFiled: August 31, 2015Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10325042Abstract: Methods for debugging a failure in a logic circuit design simulation by tracing a X-value are provided. In one aspect, a method includes detecting during a X-propagation logic circuit design simulation a failure at a register transfer level of a logic circuit comprising one or more logic blocks and tracing a X-value in a data path of the one or more logic blocks until the X-value is observed in a control path of the one or more logic blocks. The method also includes identifying a logic block comprising a control signal of the control path in which the X-value is observed, and identifying the logic block in which the X-value is observed as a root cause of the failure. Systems and machine-readable media are also provided.Type: GrantFiled: August 25, 2016Date of Patent: June 18, 2019Assignee: Cadence Design Systems, Inc.Inventors: Amit Sharma, Amit Aggarwal, Amit Dua, Manu Chopra, Vincent Reynolds, Abhishek Raheja
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Patent number: 10325043Abstract: The time domain response of a simulated system is simulated by first receiving variables for the simulated system. A frequency domain simulation is performed over different frequencies using each of the variables to provide simulated frequency domain responses for the simulated system. A time domain simulation is performed over the different frequencies using a subset of simulated frequency domain responses to produce a plurality of simulated time domain responses for the simulated system. The subset of the simulated frequency domain responses is mapped to the plurality of simulated time domain responses to produce a frequency-domain-to-time-domain mapping. A plurality of mapped time domain responses is determined using the frequency-domain-to-time-domain mapping, where the plurality of simulated time domain responses and the plurality of mapped time domain responses provide time domain responses for each of the plurality of variables for the simulated system.Type: GrantFiled: March 25, 2015Date of Patent: June 18, 2019Assignee: Dell Products L.P.Inventors: Bhyrav Mutnury, JayaGowri Anand Burji, Nikita Ambasana
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Patent number: 10325044Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.Type: GrantFiled: May 2, 2016Date of Patent: June 18, 2019Assignee: Imagination Technologies LimitedInventors: Ashish Darbari, Sam Elliott
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Patent number: 10325045Abstract: A computer system for estimating timing convergence using assertion comparisons. The computer system receives predefined golden assertions associated with a macro to be tested. The computer system executes the macro to obtain current feedback assertion values. The computer system calculates one or more metrics based on a comparison between the current feedback assertion values and values of one or more different sets of assertions. The computer system estimates a time to convergence based on the one or more calculated metrics. The computer system generates a schedule based on the estimated time to convergence.Type: GrantFiled: May 25, 2017Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Ofer Geva, Yaniv Maroz, Limor Plotkin, Shiran Raz
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Patent number: 10325046Abstract: Configuring a hardware verification system includes receiving first data representing a first integrated circuit design configured to operate via a first clock signal derived from a second clock signal and a third signal generated by the second clock signal. The computer transforms the first data into second data representing a second design that includes functionality of the first design. The transformation replaces the first clock signal with the second clock signal. A first Boolean function is defined by first and second values of the third signal corresponding to a first transition of the second clock signal being in a same direction as a transition of the first clock signal. A second Boolean function is defined by the first and second values of the third signal corresponding to a second transition of the second clock signal being in a direction opposite to the associated transition of the first clock signal.Type: GrantFiled: September 15, 2017Date of Patent: June 18, 2019Assignee: SYNOPSYS, INC.Inventors: Lingyi Liu, Ngai Ngai William Hung, Sitanshu Seth, Leonid Alexander Broukhis, Dhiraj Goswami
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Patent number: 10325047Abstract: In the present invention the issue of calculating voltage drop at the contact points of the power network with injected power currents is proposed. The method consists of the three steps. First, the said power network is partitioned into sub-networks. Secondly, the said sub-networks are expressed in terms of their admittance matrices and voltage transfer functions, which are then fed into timing simulator handling both time and frequency to compute the voltage drop at the said contact points. To achieve better partition result, inputs, outputs including user assigned nodes for recording voltages, are utilized to absorb the sub-network without inputs and outputs into the same partition as its parent node, and generate output cone with single input and outputs. Timing simulator uses convolution to get input voltage at each time step recursively and then voltage transfer used to evaluate output voltage at the same time step with minimal computational overhead.Type: GrantFiled: October 1, 2015Date of Patent: June 18, 2019Assignee: Sage Software, Inc.Inventor: Mau-chung Chang
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Patent number: 10325048Abstract: An integrated circuit test method provides an interactive shell environment having analysis modules organized as a directory such that for a given session a user can access any of the analysis modules. This invention describes a virtual directory structure for navigating through the entire test data starting from design, test configuration, ATPG patterns, failure information and callout information. This structure also allows the creation of a scripting environment for the user to select a specific configuration and process the information. User can achieve all of this in a single session as opposed to working on every test configuration in an independent session.Type: GrantFiled: December 14, 2016Date of Patent: June 18, 2019Assignee: CADENCE DESIGN SYSTEMS, INC.Inventors: Sameer Chakravarthy Chillarige, Sonam Kathpalia, Mehakpreet Kaur, James S. Allen, Krishna Vijaya Chakravadhanula
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Patent number: 10325049Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.Type: GrantFiled: January 18, 2017Date of Patent: June 18, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashraf ElSharif, Kenneth Douglas Klapproth, Jason D. Kohl
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Patent number: 10325050Abstract: A method for designing a circuit. The method may include obtaining a register-transfer level (RTL) file for an integrated circuit. The method may further include generating, using an RTL-synthesis compiler and from the RTL file, a gate-level netlist including a plurality of cells assigned to a plurality of cell groups. The method may further include obtaining, from a user, a selection of a user-defined criterion and a selected cell group from the plurality of cell groups. The method may further include partitioning the selected cell group into a first partitioned cell group including a first subset of the plurality of cells and a second partitioned cell group comprising a second subset of the plurality of cells. The method may further include generating a floorplan comprising the first partitioned cell group and the second partitioned cell group.Type: GrantFiled: April 14, 2016Date of Patent: June 18, 2019Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Mani Viswanath, Thomas Mitchell, John Eitrheim
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Patent number: 10325051Abstract: Systems and techniques for optimizing an integrated circuit (IC) design are described. A logic-function identifier can be determined based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone. An arrival-time-pattern identifier can be determined based on a set of arrival times at inputs of the fan-in combinational-logic-cone. An optimized combinational-logic-cone can be obtained by performing, in addition to optionally other operations, a database lookup by using the logic-function identifier and the arrival-time-pattern identifier. Next, the fan-in combinational-logic-cone can be replaced with the optimized combinational-logic-cone in the IC design.Type: GrantFiled: April 25, 2018Date of Patent: June 18, 2019Assignee: Synopsys, Inc.Inventors: Luca Gaetano Amaru, Patrick Vuillod, Jiong Luo
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Patent number: 10325052Abstract: The present embodiments relate generally to techniques for creating and/or modifying multi-layer buses in an IC design. According to some more particular aspects, embodiments relate to techniques for allowing an IC designer to efficiently transition a multi-layer bus section made of N wires and M layers to another multi-layer bus section made of N wires and any other M? layers. In some embodiments, the user describes, programmatically, one or several custom transitions called a custom transition procedure and saved in a human-readable text file that can also be read by a layout editor tool. By a command associated with the custom transition procedure that is exposed to the user in the layout editor tool, a multi-layer bus is automatically transitioned from a set of layers to another.Type: GrantFiled: September 15, 2016Date of Patent: June 18, 2019Assignee: CADENCE DESIGN SYSTEMS, INC.Inventor: Christophe Fouassier
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Patent number: 10325053Abstract: A method and apparatus for matching the lengths of traces of differential signal pairs. The method includes determining that a first trace is longer than a second trace and modifying the second trace so that the length is substantially equal to the length of the first trace. In some implementations, the second trace can be modified by replacing one or more sections of the trace with two line segments that are substantially equal in length and meet at a vertex that is less than 180 degrees.Type: GrantFiled: June 9, 2017Date of Patent: June 18, 2019Assignee: CISCO TECHNOLOGY, INC.Inventors: Lin Shen, Yongming Xiong, Stephen Ong, Shahbaz Mahmood
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Patent number: 10325054Abstract: Methods and apparatuses are described for sharing inductive invariants while performing formal verification of a circuit design. Specifically, some embodiments assume at least an inductive invariant for a property to be true while proving another property. According to one definition, an inductive invariant of a property is an inductive assertion such that all states that satisfy the inductive assertion also satisfy the property. According to one definition, an inductive assertion describes a set of states that includes all legal initial states of the circuit design and that is closed under a transition relation that models the circuit design.Type: GrantFiled: January 29, 2014Date of Patent: June 18, 2019Assignee: Synopsys, Inc.Inventors: Himanshu Jain, Per M. Bjesse, Carl P. Pixley
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Patent number: 10325055Abstract: This application discloses a computing system configured to determine a timing window for reception of a signal propagated through a victim channel in a circuit design, generate an aggressor window bump for each noise bump capable of being induced on the victim channel by one or more aggressor channels, determine a delta delay corresponding to the timing window for the signal propagated through the victim channel based, at least in part, on one or more of the aggressor window bump, and utilize the delta delay corresponding to the timing window for the signal to determine whether the victim channel operates within a timing constraint associated with the circuit design.Type: GrantFiled: April 3, 2015Date of Patent: June 18, 2019Assignee: Mentor Graphics CorporationInventors: Dhananjay Kumar Griyage, Mohan Rangan Govindaraj
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Patent number: 10325056Abstract: A system, methods, and a computer program product for estimating a yield and creating corners of a circuit design with the aid of a failure boundary classification. The system, methods and computer program product provide for determining, based on how many sampling factors have failures, whether data samples are sufficient as input to scaled-sigma sampling. If the data samples are insufficient, the failure boundary classification is usable to determine whether the yield is high enough to meet a yield target. A design corner can be located by applying a binary search to results of scaled-sigma sampling. The failure boundary classification can aid in setting up the search.Type: GrantFiled: June 10, 2016Date of Patent: June 18, 2019Assignee: CADENCE DESIGN SYSTEMS, INC.Inventors: Wangyang Zhang, Hongzhou Liu
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Patent number: 10325057Abstract: A system and method for testing a device under test (DUT) combines measurement data of field components values made at different sampling locations away from the DUT with computer-aided design layout of the DUT. The combined computer-aided design layout of the DUT and the measurement data can then be displayed for analysis.Type: GrantFiled: August 17, 2016Date of Patent: June 18, 2019Assignee: AMBER PRECISION INSTRUMENTS, INC.Inventors: Giorgi Muchaidze, Besarion Chikhradze, Hamed Kajbaf
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Patent number: 10325058Abstract: An integrated circuit of a semiconductor device is fabricated by forming patterns on a wafer in conformance with a layout of the patterns. A method for verifying the layout includes providing a virtual pattern on a predicted defect point in the layout, and identifying at least one pattern from among those of the layout using the virtual pattern. The predicted defect point corresponds to a weak point where it is determined in advance that a defect will occur when the layout is transcribed on a wafer. The identified pattern is a pattern that is adjacent to the virtual pattern in the layout.Type: GrantFiled: February 27, 2017Date of Patent: June 18, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Moo-Kyung Lee, Jaeick Son, Sunghoon Kim
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Patent number: 10325059Abstract: A method, system, and computer program product for performing incremental common path pessimism analysis in integrated circuit design includes performing common path pessimism removal (CPPR) analysis to provide timing credit for one or more paths that are subject to common path pessimism. The method also includes identifying one or more post-CPPR critical paths based on the CPPR analysis, setting flags for critical nodes of the one or more post-CPPR critical paths, performing a design fix to address the one or more post-CPPR critical paths, and applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths. Invalidating and re-performing the CPPR analysis is done only for paths associated with the seed points.Type: GrantFiled: October 27, 2017Date of Patent: June 18, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tsung-Wei Huang, Kerim Kalafala, Vasant B. Rao, Debjit Sinha, Natesan Venkateswaran
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Patent number: 10325060Abstract: A hotspot correction method is provided. The layout patterns in the hotspot regions are accurately corrected by using an ILT method. Then the layout patterns in the extension regions are corrected by using an OPC method. As a result, the layout patterns in the hotspot regions can be accurately corrected while pattern distortion of the extension regions generated due to the regional ILT correction can be prevented. Moreover, high demanding of calculation capability and long calculation time of global ILT correction can be avoided.Type: GrantFiled: November 30, 2017Date of Patent: June 18, 2019Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventors: Yiqun Tan, Shirui Yu, Xuan Zhao
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Patent number: 10325061Abstract: Various aspects of the disclosed technology relate to axial thrust analysis of turbomachinery designs. A cavity of a turbomachinery design is divided into sub-cavities. Magnitudes of horizontal components of forces exerted on rotational faces in each of the sub-cavities are computed based on computational fluid dynamics, areas of the rotational faces and angles of the rotational faces. The horizontal components are components along a rotational axis of the turbomachinery design. Directions of the horizontal components of the forces are determined based on how many faces a line parallel to the rotational axis intersects between a rotational face of interest and a side of the cavity. A thrust force on a turbine of the turbomachinery design attributed to secondary fluid systems is computed using the magnitudes and the directions of the horizontal components of the forces.Type: GrantFiled: March 9, 2017Date of Patent: June 18, 2019Assignee: Mentor Graphics CorporationInventors: Michael James Croegaert, Douglas Mitchell Kolak, Jacob Arlington Nuetzel
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Patent number: 10325062Abstract: The present invention relates to a method and device for generating an engineering topology of a digital substation. The method may include: generating, by a single line diagram generation module, a single line diagram of the digital substation based on input information regarding a plurality of substation component devices and connection relations therebetween; converting, by a topology conversion module, the single line diagram of the digital substation into an engineering topology conforming to international standards by use of conversion conditions stored in a topology component management module; verifying, by a topology verification module, whether the engineering topology is suitable for the digital substation based on the international standards; and generating, by an international standard file generation module, a single line diagram engineering file of the digital substation as a system specification description (SSS) by use of the verified engineering topology.Type: GrantFiled: February 24, 2017Date of Patent: June 18, 2019Assignee: KOREA ELECTRIC POWER CORPORATIONInventors: Byung Tae Jang, Nam Ho Lee, Yong Ho An, Jong Kee Choi, Jeong Yeol Han, You Jin Lee, Eung Bo Shim, Dong Il Lee
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Patent number: 10325063Abstract: A system is provided with memory and a processor. The memory is configured to store data representative of a multi-valued decision diagram (MDD). The processor is in communication with the memory and is programmed to receive a current selection of one or more of the features, and to determine a feature state for each of the one or more features, based on the current selection and the possible configurations defined by the MDD. The processor is further programmed to calculate an availability bitset indicative of which features as available for further selection, consistent with the valid configurations and without violating existing constraints of the current selection.Type: GrantFiled: October 14, 2016Date of Patent: June 18, 2019Assignee: Ford Motor CompanyInventors: Melinda Kaye Hunsaker, David Mark Newton, Essam Mahmoud Sabbagh
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Patent number: 10325064Abstract: Facilities are provider herein for predicting potentially preventable patient readmissions after discharge from a health care provider. A patient readmission prediction model is built based on received patient data for one or more health care providers. Patient attributes discernible from that patient data are extracted and analyzed, and certain attributes are selected as being meaningful in predicting likelihood of post-discharge, potentially preventable patient readmission by patients newly admitted to a health care provider. Patient data for a newly admitted patient is obtained, and the readmission prediction model is applied against that patient data for the newly admitted patient to obtain a predictive risk score that is indicative of the likelihood that the newly admitted patient will experience a potentially preventable readmission post-discharge from the health care provider.Type: GrantFiled: January 18, 2013Date of Patent: June 18, 2019Assignee: 3M INNOVATIVE PROPERTIES COMPANYInventor: Herb Fillmore