Patents Issued in December 17, 2019
  • Patent number: 10509685
    Abstract: Methods, systems, and computer readable mediums for optimizing a system configuration are disclosed. In some examples, a method includes determining whether a system configuration for executing a workload using a distributed computer system is optimizable and in response to determining that the system configuration is optimizable, modifying the system configuration such that at least one storage resource for storing workload data is located at a server node that is executing the workload in the distributed computer system.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: December 17, 2019
    Assignee: VCE IP Holding Company, LLC
    Inventors: Changbin Gong, Volodymyr Korolyov
  • Patent number: 10509686
    Abstract: Systems and methods for distributing computing tasks are disclosed. One system includes a first computing system and a second computing system. The first computing system includes a processing unit and a memory, the memory storing a computer-executable workload including a plurality of procedures including at least one distributable procedure, the at least one distributable procedures capable of execution independent of underlying operating system or platform resources of the first computing system and configured for execution on an architecture of the first computing system. The system further includes a distributable computation unit executable on a second computing system, the distributable computation unit including the at least one distributable procedure, a state of computing resources of the first computing system, and an application capable of execution on the second computing system to perform the at least one distributable procedure.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: December 17, 2019
    Assignee: Unisys Corporation
    Inventor: Andrew Ward Beale
  • Patent number: 10509687
    Abstract: There is provided a method and system for process migration in a data center network. The method includes selecting processes to be migrated from a number of overloaded servers within a data center network based on an overload status of each overloaded server. Additionally, the method includes selecting, for each selected process, one of a number of underloaded servers to which to migrate the selected process based on an underload status of each underloaded server, and based on a parameter of a network component by which the selected process is to be migrated. The method also includes migrating each selected process to the selected underloaded server such that a migration finishes within a specified budget.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 17, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Navendu Jain, Ishai Menache, F. Bruce Shepherd, Joseph (Seffi) Naor
  • Patent number: 10509688
    Abstract: A system and method is provided for migrating a virtual machine between servers to access physical resources. An exemplary method includes intercepting a request from a client device to access a physical resource; identifying a virtual machine on a first server that is currently hosting a remote application for the client device; identifying a second server associated with the physical resource; and migrating the virtual machine from the first server to the second server, such that the client device can access the physical resource using the second server.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: December 17, 2019
    Assignee: Parallels International GmbH
    Inventors: Anton Zelenov, Nikolay Dobrovolskiy, Serguei M. Beloussov
  • Patent number: 10509689
    Abstract: The present disclosure provides a terminal and a method for processing an application. The method includes: monitoring a temperature change state of a CPU; searching for an APP with a first CPU occupancy rate exceeding a corresponding normal numerical range if it is monitored that a second CPU occupancy rate is also in an increase state upon monitoring that temperature of the CPU is in an increase state; determining the APP as an APP that causes a temperature increase of the CPU; and stopping using the APP that causes the temperature increase of the CPU. According to the method, the influence on the terminal from an APP that causes the temperature increase of the CPU is reduced and the condition that the CPU of the terminal is overheated is avoided.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: December 17, 2019
    Assignee: BEIJING KINGSOFT INTERNET SECURITY SOFTWARE CO., LTD.
    Inventors: Chao Xiao, Jianxun Fu, Haiying Yang, Jialin Xiong
  • Patent number: 10509690
    Abstract: The exposing of a server function to a browser. From the browser's perspective, the browser submits a request for a web page to a web server, the web page being one of multiple web pages in a web application offered by the web server. The web server responds to the request by, for at least one of the server functions, formulating a corresponding script language function that defines a matching name and parameter set of the server side function. The script language function has a body that, when executed, serializes at least the name and parameter set of the server side function. The web server then provides the web page code and the corresponding script language function to the browser. The browser may then calls the server side function via the script language function.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: December 17, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vikas Ahuja, Brian Charles Blomquist
  • Patent number: 10509691
    Abstract: A method including retrieving, from an operating system of a client device, a timestamp associated with a physical action on an input device coupled with the client device, is provided. The method includes tagging the timestamp with an action metadata of an application running in the client device, the physical action being associated with the application, and forming an aggregated dataset comprising the timestamp and the action metadata. The method also includes associating an acuity value to the timestamp based on the aggregated dataset, and modifying a display of an application output to indicate the acuity value within the application. A system and a non-transitory, computer readable medium storing instructions to perform the method are also provided.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 17, 2019
    Assignee: Colossio, Inc.
    Inventor: Joseph A. Jaroch
  • Patent number: 10509692
    Abstract: A system and method enables loosely-coupled lock-step computing including sensors that detect or measure a physical property and server groups. Each server group is serially linked to another server group and includes server instances operating in virtual synchrony. Virtual synchrony middleware receives outputs from multiple server instances and renders a single reply based on the outputs from the multiple server instances. The virtual synchrony middleware replicates and orders incoming requests to the server groups to ensure each of the server instances of that server group receives the same incoming requests in the same order.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 17, 2019
    Assignee: 2236008 Ontario Inc.
    Inventors: Kerry Wayne Johnson, Christopher William Lewis Hobbs, Peter Shook
  • Patent number: 10509693
    Abstract: According to an aspect of the present inventive concept there is provided a method for identifying a cause for a failure of a computer-implemented test performed on a latest software code revision in a sequence of a plurality of software code revisions, the method comprising: identifying a first revision of said sequence of revisions for which said test passes and a second revision of said sequence of revisions which is subsequent to the first revision and for which said test fails, determining a first change between the software code of the first revision and the software code of the second revision, generating a first modified version of the software code of the latest revision using the determined first change, determining whether said test passes or fails when performed on the first modified version, in response to determining that said test fails when performed on the first modified version: identifying a third revision and a fourth revision of said sequence which are intermediate the latest revision
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: December 17, 2019
    Assignee: VERIFYTER AB
    Inventor: Daniel Hannson
  • Patent number: 10509694
    Abstract: System and methods are provided for optimal error detection in programmatic environments through the utilization of at least one user-defined condition. Illustratively, the conditions can include one or more triggers initiating the collection of log data for methods associated with the provided at least one condition. Operatively, the disclosed systems and methods observe the run-time of the programmatic environment and initiate the collection of log data based on the occurrence of a condition trigger. A rank score can also be calculated to rank the methods associated with the defined condition to isolate those methods that have higher probability of causing the defined condition. Dynamic instrumentation of the methods associated with the user defined conditions during run time are used to calculate the rank score, which is used for ranking the methods.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: December 17, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Lenin Ravindranath Sivalingam, Sergey Kanzhelev, Suman Kumar Nath, Madan Musuvathi
  • Patent number: 10509695
    Abstract: Detection of abnormalities in HDBD is performed by processing it to obtain a dictionary from a training data. This is done by computing a low rank randomized LU decomposition which enables constant online updating of the training data and thus gets constant updating of the normal profile in the background.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 17, 2019
    Assignee: ThetaRay Ltd.
    Inventors: Amir Averbuch, Gil Shabat, Yaniv Shmueli
  • Patent number: 10509696
    Abstract: Errors may be detected and mitigated during the migration of data. Migration of data from a source data store to a target data store may be monitored for errors. When an error is detected, one or more responsive actions may be identified to modify performance of the migration. In some embodiments, responsive actions may include further analyses to validate the migration. In some embodiments, the responsive actions may be corrective actions to correct the detected error. Once identified, the responsive actions may be performed to modify performance of the migration.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: December 17, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Ilia Gilderman, Arun Kumar Thiagarajan, John MacDonald Winford
  • Patent number: 10509697
    Abstract: A data storage device includes a flash memory, a controller and a random-access memory. The flash memory includes a plurality of blocks, and each of the blocks includes a plurality of pages. The controller divides the pages of the blocks into a plurality of super pages which include a plurality of first pages and a plurality of second pages. The controller writes at least one super page data to one of the first pages, generates a parity code based on the at least one super page data, and stores the parity code on the random-access memory.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: December 17, 2019
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Yao Chiang
  • Patent number: 10509698
    Abstract: A system, method and apparatus for encoding and decoding data. A host processor and host memory are coupled to a block I/O device. The host processor issues encode and decode commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device encodes the data specified in the encode command, thus relieving the host processor of performing the encoding/decoding and freeing the host processor for other tasks.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: December 17, 2019
    Assignee: Goke US Research Laboratory
    Inventors: Steven Schauer, Xinhai Kang, Engling Yeo
  • Patent number: 10509699
    Abstract: A method begins with receiving an encoded data slice that has associated therewith a slice name that is representative of a dispersed storage network (DSN) logical address. The method continues with accessing a DSN address to memory device mapping based on the DSN logical address to identify a memory device of the storage unit. The method continues with retrieving a logical zone to physical address space mapping of the identified memory device. The method continues with determining information regarding the encoded data slice and a logical zone of the memory device from the logical zone to physical address space mapping based on the encoded data slice information. The method continues with generating a physical address within the identified logical zone for storing the encoded data slice. The method continues with storing the encoded data slice within the identified memory device at the physical address.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Manish Motwani, Jason K. Resch
  • Patent number: 10509700
    Abstract: A storage system has a storage controller and a RAID group. The storage controller has policy management information such that one failure recovery process among a plurality of differing failure recovery processes is associated with each RAID group, and when an error in a command issued to a RAID group is detected, the failure recovery process associated with the RAID group to which the command was issued is specified on the basis of the policy management information, and the specified failure recovery process is executed.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: December 17, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoshi Honda, Naoto Shiino, Toru Ando, Keiichiro Uchida
  • Patent number: 10509701
    Abstract: The embodiments set forth a technique for carrying out a backup of data managed at a computing device. According to some embodiments, the technique can include the steps of (1) receiving a request to carry out the backup of the data, (2) in response to the request, generating a current snapshot of the data, (3) identifying, in accordance with the current snapshot of the data, block data of at least one data block to be reflected in the backup of the data, wherein the at least one data block is tagged with an identifier of a file node to which the at least one data block corresponds, and (4) providing information to a storage to cause the block data to be reflected in the backup of the data.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 17, 2019
    Assignee: Apple Inc.
    Inventors: Eric B. Tamura, Dominic B. Giampaolo
  • Patent number: 10509702
    Abstract: An application may store data to a dataset comprising a plurality of volumes stored on a plurality of storage systems. The application may request a dataset image of the dataset, the dataset image comprising a volume image of each volume of the dataset. A dataset image manager operates with a plurality of volume image managers in parallel to produce the dataset image, each volume image manager executing on a storage system. The plurality of volume image managers respond by performing requested operations and sending responses to the dataset image manager in parallel. Each volume image manager on a storage system may manage and produce a volume image for each volume of the dataset stored to the storage system. If a volume image for any volume of the dataset fails, or a timeout period expires, a cleanup procedure is performed to delete any successful volume images.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: December 17, 2019
    Assignee: NetApp Inc.
    Inventors: Stephen Wu, Prathamesh Deshpande, Manan Patel
  • Patent number: 10509703
    Abstract: Improved apparatus and system for the backup and recovery of a computer system with minimized key strokes and steps for a user. The improved apparatus and system includes an external hard drive, power controls, keyboard controller, and flash drive, all of which are referred to as the present invention DittoDriveâ„¢, to allow a user to copy the contents of a computer hard drive to a second hard drive and then allow the user to operate the computer from either the first hard drive or the second hard drive.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: December 17, 2019
    Inventors: Gonen Ravid, Josef Rabinovitz
  • Patent number: 10509704
    Abstract: Disclosed are systems, methods and computer program products for automatic data backup based on multi-factor environment monitoring. An example method includes monitoring an occurrence of one or more danger events; detecting when a danger event occurs or about to occur; determining a danger level of the detected danger event; determining an importance level of each of a plurality of backup data items; determining a backup time for performing backup of the backup data items based on the determined danger level of detected danger event; determining a backup order of the plurality of backup data items based on the determined importance level of the backup data items; selecting a backup storage for the backup data items and performing a backup of the plurality of backup data items to the selected backup storage.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: December 17, 2019
    Assignee: Acronis International GmbH
    Inventors: Alexey Makhov, Stanislav Protasov, Serguei M. Beloussov, Andrey Polevoy
  • Patent number: 10509705
    Abstract: A method for providing application functionality protection. The method includes accessing a distributed computer system having a cluster including a plurality of nodes, and receiving an indication of an application failure. The method further includes attempting to restore the application through a number of application restart attempts, and receiving an indication that the restart attempts have not restored the application. An image history is then accessed to obtain a last known good point in time image of the application. The application is restored in accordance with the last known good point in time image.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: December 17, 2019
    Assignee: Veritas Technologies LLC
    Inventors: Srineet Sridharan, Vikas Jain, Phani Karthik Maradani, Jahangir Ahmad
  • Patent number: 10509706
    Abstract: Examples disclosed herein relate to identification of an alternate principal member port by a target device in a Storage Area Network (SAN). In some examples, a target device in a SAN may determine that a principal member port of a target driven peer zone on the target device is likely to fail based on diagnostic information related to the principal member port. The target driven peer zone may be configured in the SAN via the target device. In response to determining, the target device may identify an alternate principal member port on the target device. The target device may perform an action to indicate the alternate principal member port as the principal member port.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: December 17, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vivek Agarwal, Krishna Puttagunta, Rupin T. Mohan
  • Patent number: 10509707
    Abstract: Described are techniques for mirroring data that may include issuing, by an application on a host, a write operation that writes first data to a primary storage entity having data stored in accordance with a first format and first structure; intercepting, on the host, the write operation; and performing, on the host, first processing to process the write operation. The first processing may include: sending the write operation to a data storage system including the primary storage entity; determining whether the primary storage entity is mirrored as a second storage entity having data stored in a second format and second structure different from the first format and first structure; and responsive to determining the primary storage entity is mirrored as the second storage entity, issuing one or more second write operations to mirror the first data on the second storage entity in accordance with the second format and second structure.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 17, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Douglas E. LeCrone, Paul A. Linstead
  • Patent number: 10509708
    Abstract: Techniques are disclosed for resynchronizing a node of a distributed storage system with other nodes of the distributed storage system. Some embodiments presented herein include a computer-implemented method for resynchronizing a node of a distributed storage system with other nodes of the distributed storage system. The method comprises identifying an out-of-sync block of the node. The method further comprises determining that the out-of-sync block is a code block, wherein the code block is generated by performing an erasure coding operation on data blocks which are stored in the other nodes. The method further comprises locating a mirrored code block in an address space maintained for mirrored code blocks. The method further comprises storing contents of the mirrored code block in a storage location of the out-of-sync block.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 17, 2019
    Assignee: VMware, Inc.
    Inventors: Enning Xiang, Yiqi Xu
  • Patent number: 10509709
    Abstract: A method begins by a dispersed storage processing module obtaining data for storage. The method continues with the dispersed storage processing module encoding the data in accordance with an error coding dispersal storage function to produce a plurality of sets of encoded data slices. The method continues with the dispersed storage processing module determining a proxy unit. The method continues with the dispersed storage processing module transmitting the plurality of sets of encoded data slices to the proxy unit, wherein the proxy unit disperses the plurality of sets of encoded data slices to a plurality of dispersed storage units.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: December 17, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 10509710
    Abstract: Disclosed are a method, a terminal, a device, and a computer readable storage medium for improving the performance of a virtual machine. The method includes determining whether a failure of a disk of a host having a virtual disk file stored therein occurs if a virtual machine sends a read request or a write request to the virtual disk file; sending the read or write request to a storage device which is associated with the host and has the virtual disk file stored therein if the failure occurs, so that the storage device is able to feed back data; detecting whether the disk of the host is recovered if the data fed back from the write request is received; and writing the data fed back from the write request into the disk of the host if the disk of the host is recovered.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: December 17, 2019
    Assignee: PING AN TECHNOLOGY (SHENZHEN) CO., LTD.
    Inventor: Qiguo Zhang
  • Patent number: 10509711
    Abstract: A microcontroller includes a signal interface for transmitting signals. The microcontroller further includes an error injection module. The error injection module is configured to tap a transmission signal associated with the signal interface. The error injection module includes a synchronization unit. The synchronization unit is configured to detect within the tapped transmission signal an occurrence of a synchronization event. Further, the error injection module is configured to modify the tapped transmission signal by adding at least one disturbance to the transmission signal in synchronization with at least the detected occurrence of the synchronization event.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: December 17, 2019
    Assignee: Infineon Technologies AG
    Inventors: Jayakrishna Guddeti, Deepa Chandran, Shivaprasad Sadashivaiah
  • Patent number: 10509712
    Abstract: Automated methods and systems to determine a baseline event-type distribution of an event source and use the baseline event type distribution to detect changes in the behavior of the event source are described. In one implementation, blocks of event messages generated by the event source are collected and an event-type distribution is computed for each of block of event messages. Candidate baseline event-type distributions are determined from the event-type distributions. The candidate baseline event-type distribution has the largest entropy of the event-type distributions. A normal discrepancy radius of the event-type distributions is computed from the baseline event-type distribution and the event-type distributions. A block of run-time event messages generated by the event source is collected. A run-time event-type distribution is computed from the block of run-time event messages.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 17, 2019
    Assignee: VMware, Inc.
    Inventors: Ashot Nshan Harutyunyan, Arnak Poghosyan, Nicholas Kushmerick, Naira Movses Grigoryan
  • Patent number: 10509713
    Abstract: A method, performed in a debug host, for observing software execution on a computer having one or more processor cores, a cache attached to the one or more processor cores via respective execution pipelines forming a cache arrangement, and a memory, comprises obtaining an instruction trace of the cache arrangement and a data trace for data being loaded from the memory into the cache. The instruction trace is synchronized with the data trace to generate a synchronized data trace and/or a synchronized instruction trace. A state of a memory model, representing a memory readable by the one or more processor cores via a respective instruction is updated using the synchronized data trace and the synchronized instruction trace.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: December 17, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (publ)
    Inventors: Peter Svensson, Bengt Wikenfalk
  • Patent number: 10509714
    Abstract: An object of the present invention is to provide an information processing apparatus capable of performing a performance evaluation easily without using a specific communication protocol.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: December 17, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Norio Ikeda, Mitsuo Shimotani, Shinji Ota
  • Patent number: 10509715
    Abstract: A system is provided to run new code modules safely in a duplicative, protected environment without affecting the code modules that are already trusted to be on the system. The system receives a new code module that validates operational data of a computing device, and instantiates a new, parallel execution engine to run the new code module on the operational data in parallel with another execution engine running the trusted/verified code modules that also validate the same operational data. The new engine runs the new code module with the operational data to produce new code module results. The production engine runs the trusted/verified code modules with the operational data to produce verified code module results. The new code module results are combined with the verified code module results to produce combined results describing the operational status of the computing device.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: December 17, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: David C. White, Jr., Magnus Mortensen, Jay K. Johnston
  • Patent number: 10509716
    Abstract: Methods and systems for managing a flighted software feature. One embodiment provides a system for disabling a flighted software feature enabled for selected users in a computing environment. The system includes a memory storing instructions and an electronic processor coupled to the memory. The electronic processor configured to execute the instructions to determine a set of related service requests submitted by a plurality of users in the computing environment, and, for each of the plurality of users, query a server servicing the user for a list of flighted software features enabled for the user during a predetermined time period. The electronic processor is also configured to determine, based on the list of flighted software features enabled for each of the plurality of users during the predetermined time period, a common flighted software feature, and automatically disable the common flighted software feature for at least one of the plurality of users.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 17, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vadivelan Ramalingam, Ilker Celikyilmaz, Esha Sharma, Divyachapan S. Padur, Donovan Isaak, Mark Gilbert
  • Patent number: 10509717
    Abstract: A system, method, and computer program product are provided for automatically testing software applications including dynamic web pages. In operation, an automated testing system identifies at least one software application on which to perform automated testing. The automated testing system identifies at least one graphical user interface (GUI) associated with the at least one software application. Further, the automated testing system identifies at least one input object associated with the at least one graphical user interface. The automated testing system determines whether the at least one input object is present in an object repository including known input objects and corresponding testing data. If it is determined that the at least one input object is present in the object repository, the automated testing system automatically generates a test for the at least one input object utilizing corresponding test input data from the object repository.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: December 17, 2019
    Assignee: AMDOCS DEVELOPMENT LIMITED
    Inventor: Sagar Subhash Surana
  • Patent number: 10509718
    Abstract: A system and computer-implemented method for generating software testing scripts from test cases is provided. The system comprises a test case importing module configured to receive test cases and a Natural Language Processing (NLP) module configured to scan and mine text of the received test cases. Furthermore, the system comprises a user interface object identifier to identify one or more User Interface (UI) elements, functional flow models and test steps and corresponding test data. The system also comprises a user interface object mapper to map the one or more identified UI elements from the test cases with one or more user interface elements corresponding to one or more wireframes. In addition, the system comprises a test script generator to receive the mapped one or more UI elements, the identified functional flow models and the identified test steps and corresponding test data for generating test scripts.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: December 17, 2019
    Assignee: COGNIZANT TECHNOLOGY SOLUTIONS INDIA PVT. LTD
    Inventors: Ramakrishnan Venkatasubramanian, Amarnath Sankar, Carnelian Lamech, Ghatak Anit, Srinivasan Kumarappan, Suraj Sangavkar
  • Patent number: 10509719
    Abstract: Example implementations relate to automatically identifying regressions. Some implementations may include a data capture engine to capture data points during test executions of the application under test. The data points may include, for example, test action data and application action data. Additionally, some implementations may include a data correlation engine to correlate each of the data points with a particular test execution of the test executions, and each of the data points may be correlated based on a sequence of events that occurred during the particular test execution. Furthermore, some implementations may also include a regression identification engine to automatically identify, based on the correlated data points, a regression between a first version of the application under test and a second version of the application under test.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: December 17, 2019
    Assignee: MICRO FOCUS LLC
    Inventors: Inbar Shani, Ayal Cohen, Yaron Burg
  • Patent number: 10509720
    Abstract: An apparatus may include: a memory device suitable for writing data while erasing at least one monitor cell among a plurality of memory cells in a write mode, and reading the at least one monitor cell by supplying a monitor voltage in a monitor mode; and a controller suitable for transmitting a monitor command and address information for reading the at least one monitor cell to the memory device in the monitor mode, and determining whether to perform a reclaim operation based on the values of the at least one monitor cell read by the memory device.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: December 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Tae-Hoon Kim
  • Patent number: 10509721
    Abstract: In some examples, performance counters for computer memory may include ascertaining a request associated with a memory address range of computer memory. The memory address range may be assigned to a specified performance tier of a plurality of specified performance tiers. A performance value associated with a performance attribute of the memory address range may be ascertained, and based on the ascertained performance value, a weight value may be determined. Based on the ascertained request and the determined weight value, a count value associated with a counter associated with the memory address range may be incremented. Based on an analysis of the count value associated with the counter, a determination may be made as to whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: December 17, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: John G. Bennett, Siamak Tavallaei
  • Patent number: 10509722
    Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block, and designate a storage mode for an available memory block based on the valid data measure, wherein the storage mode is for controlling a number of bits stored per each of the memory cells for subsequent or upcoming data writes.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
  • Patent number: 10509723
    Abstract: A computing device includes an interface configured to interface and communicate with a communication system, a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory that is configured to execute the operational instructions to perform various operations. The computing device determines to de-stage information stored in a cache memory to a nonvolatile memory device. The computing device determines whether the de-stage is based on a power interruption and when the de-stage is not based on a power interruption the computing device updates access counters associated with the information and the target location for the information in the nonvolatile memory, updates a data access tracking module and initiates a data relocation function to transfer the information to the nonvolatile memory device.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: December 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Grzegorz P. Szczepanik, Lukasz Jakub Palus, Sarvesh Patel, Kushal Patel
  • Patent number: 10509724
    Abstract: Implementations of this disclosure are directed to systems, methods and media for assessing the status of data being stored in distributed, cached databases that includes retrieving, from a data cache, variables which include a cache loss indicator and a non-null value. The variables are analyzed to determine a state of the cache loss indicator. If the cache loss indicator indicates an intentional cache loss state, the cache loss indicator is removed and the non-null value is provided to an application. Otherwise, a cache restore process is initiated.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 17, 2019
    Assignee: MZ IP HOLDINGS, LLC
    Inventors: Ajk Palikuqi, Garth Gillespie, Arya Bondarian, Jai Kim
  • Patent number: 10509725
    Abstract: Techniques are provided for performing a flush operation in a non-coherent cache. In response to determining to perform a flush operation, a cache unit flushes certain data items. The flush operation may be performed in response to a lapse of a particular amount of time, such as a number of cycles, or an explicit flush instruction that does not indicate any cache entry or data item. The cache unit may store change data that indicates which entry stores a data item that has been modified but not yet been flushed. The change data may be used to identify the entries that need to be flushed. In one technique, a dirty cache entry that is associated with one or more relatively recent changes is not flushed during a flush operation.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 17, 2019
    Assignee: Oracle International Corporation
    Inventors: Sungpack Hong, Hassan Chafi, Eric Sedlar
  • Patent number: 10509726
    Abstract: A processor includes an execution unit to execute instructions to load indices from an array of indices, optionally perform scatters, and prefetch (to a specified cache) contents of target locations for future scatters from arbitrary locations in memory. The execution unit includes logic to load, for each target location of a scatter or prefetch operation, an index value to be used in computing the address in memory for the operation. The index value may be retrieved from an array of indices identified for the instruction. The execution unit includes logic to compute the addresses based on the sum of a base address specified for the instruction, the index value retrieved for the location, and a prefetch offset (for prefetch operations), with optional scaling. The execution unit includes logic to retrieve data elements from contiguous locations in a source vector register specified for the instruction to be scattered to the memory.
    Type: Grant
    Filed: December 20, 2015
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Indraneil M. Gokhale, Elmoustapha Ould-Ahmed-Vall, Charles R. Yount, Antonio C. Valles
  • Patent number: 10509727
    Abstract: A method and an apparatus for performing task-level cache management in an electronic device are provided. The method may be applied to a processing circuit of the electronic device, and may include: before a task of a plurality of tasks runs on a processor core, performing at least one checking operation on the task to generate at least one checking result, wherein the at least one checking result indicates whether the task is a risky task with risk of evicting cached data of an urgent task from a cache, and the cache is dedicated to a set of processor cores including the processor core; and according to the at least one checking result, determining whether to temporarily limit cache access permission of the processor core during a time period in which the task runs on the processor core, for preventing cache eviction of the cache due to the task.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: December 17, 2019
    Assignee: MEDIATEK INC.
    Inventors: Sheng-Ju Wei, Jia-Ming Chen, I-Cheng Cheng, Shun-Chieh Chang
  • Patent number: 10509728
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive a request from a core, the request associated with a memory operation to read or write data, and the request comprising a first address and an offset, the first address to identify a memory location of a memory. Embodiments include performing a first iteration of a memory indirection operation comprising reading the memory at the memory location to determine a second address based on the first address, and determining a memory resource based on the second address and the offset, the memory resource to perform the memory operation for the computing resource or perform a second iteration of the memory indirection operation.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 17, 2019
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Mark Schmisseur, Thomas Willhalm
  • Patent number: 10509729
    Abstract: Embodiments of an invention for address translation for scalable I/O device virtualization are disclosed. In one embodiment, an apparatus includes PASID table lookup circuitry. The PASID table lookup circuitry is to find a PASID-entry in a PASID table. The PASID-entry is to include a PASID processing mode (PPM) indicator and a first pointer to a first translation structure. The PPM indicator is to specify one of a plurality of translation types, the one of the plurality of translation types to use the first translation structure.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Rajesh M Sankaran, Randolph L Campbell, Prashant Sethi, David J Harriman
  • Patent number: 10509730
    Abstract: A method and a processing device are provided for sequentially aggregating data to a write log included in a volume of a random-access medium. When data of a received write request is determined to be suitable for sequentially aggregating to a write log, the data may be written to the write log and a remapping tree, for mapping originally intended destinations on the random-access medium to one or more corresponding entries in the write log, may be maintained and updated. At time periods, a checkpoint may be written to the write log. The checkpoint may include information describing entries of the write log. One or more of the checkpoints may be used to recover the write log, at least partially, after a dirty shutdown. Entries of the write log may be drained to respective originally intended destinations upon an occurrence of one of a number of conditions.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: December 17, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Shi Cong, Scott Brender, Karan Mehra, Darren G. Moss, William R. Tipton, Surendra Verma
  • Patent number: 10509731
    Abstract: Methods and apparatus for providing for a cache replacement policy for page caches for storage having a first memory tier having regions and virtual memory having mmaps of ones of the regions in the first memory tier. In an embodiment, the cache replacement policy includes setting a color hint to a first one of the cached pages, wherein the color hint includes a value indicating hotness of the first one of the cached pages.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: December 17, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Adrian Michaud, Roy E. Clark, Kenneth J. Taylor
  • Patent number: 10509732
    Abstract: A cache controller applies an aging policy to a portion of a cache based on access metrics for different test regions of the cache, whereby each test region implements a different aging policy. The aging policy for each region establishes an initial age value for each entry of the cache, and a particular aging policy can set the age for a given entry based on whether the entry was placed in the cache in response to a demand request from a processor core or in response to a prefetch request. The cache controller can use the age value of each entry as a criterion in its cache replacement policy.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: December 17, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul Moyer
  • Patent number: 10509733
    Abstract: Systems and methods for performing data deduplication one storage blocks while the data is encrypted. An example method may comprise: selecting a first storage block and a second storage block from a plurality of encrypted storage blocks, wherein the first storage block and the second storage block are encrypted using different cryptographic input; causing the first storage block and the second storage block to be decrypted and further encrypted using a common cryptographic input; determining that a cipher text of the first storage block and a cipher text of the second storage block are the same; and updating a reference to the first storage block to reference the second storage block in response to the determining that the cipher text of the first storage block and the cipher text of the second storage block are the same.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 17, 2019
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Henri Han Van Riel
  • Patent number: 10509734
    Abstract: A computing device includes technologies for securing indirect addresses (e.g., pointers) that are used by a processor to perform memory access (e.g., read/write/execute) operations. The computing device encodes the indirect address using metadata and a cryptographic algorithm. The metadata may be stored in an unused portion of the indirect address.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: David M. Durham, Baiju Patel