Abstract: According to one embodiment, a data storage apparatus includes a controller with a data protection function. The controller manages first and second personal identification data. The first personal identification data only includes authority to request inactivation of the data protection function. The second personal identification data includes authority to request inactivation of the data protection function and activation of the data protection function. The controller permits setting of the first personal identification data, when the second personal identification data is used for successful authentication and the first personal identification data is an initial value, or when the data protection function is in an inactive state.

Abstract: An input-output (IO) memory management unit (IOMMU) uses a reverse map table (RMT) to ensure that address translations acquired from a nested page table are correct and that IO devices are permitted to access pages in a memory when performing memory accesses in a computing device. A translation lookaside buffer (TLB) flushing mechanism is used to invalidate address translation information in TLBs that are affected by changes in the RMT. A modified Address Translation Caching (ATC) mechanism may be used, in which only partial address translation information is provided to IO devices so that the RMT is checked when performing memory accesses for the IO devices using the cached address translation information.

Abstract: A data processing system for a graphical interface includes at least one graphics processing unit (GPU) and at least one central processing unit (CPU) which communicates with the graphics processing unit, said processing unit and said central processing unit each including a group of data processing cores (C1, . . . , C6, C?1, . . . C?6). The data processing cores of the graphics processing unit are each connected to a data processing core of the central processing unit via a single dedicated bus (B1, . . . , B6) in such a way as to carry out a data transfer in parallel between said graphics processing unit and said central processing unit.

Abstract: An extension of node architecture and proxy requests enables a node to expose memory computation capability to remote nodes. A remote node can request execution of an operation by a remote memory computation resource, and the remote memory computation resource can execute the request locally and return the results of the computation. The node includes processing resources, a fabric interface, and a memory subsystem including a memory computation resource. The local execution of the request by the memory computation resource can reduce latency and bandwidth concerns typical with remote requests.

Abstract: In one embodiment, a storage system receives a number of input/output (IO) request transactions at the storage system having multiple storage devices. For each of the plurality of IO request transactions, the system determines a number of child IO requests required to complete the IO request transaction. The system tags the IO request transaction and/or the associated child IO requests with a tag identifier. For each of the child requests that is a write IO request, the system determines an optimal write IO request size, segments the write IO request into a number of sub-IO write requests, each having an optimal request size, and interleaves sub-IO write requests with read IO requests for servicing to avoid impact in performance to read IO requests for a mixed IO workload.

Abstract: Methods and systems for mutual exclusion in a non-coherent memory hierarchy may include a non-coherent memory system with a shared system memory. Multiple processors and a memory connect interface may be configured to provide an interface for the processors to the shared memory. The memory connect interface may include an arbiter for atomic memory operations from the processors. In response to an atomic memory operation, the arbiter may perform an atomic memory operation procedure including setting a busy flag for an address of the atomic memory operation, blocking subsequent memory operations from any of the processors to the address while the busy flag is set, issuing the atomic memory operation to the shared memory, and in response to an acknowledgement of the atomic memory operation from the shared memory, clearing the busy flag and allowing subsequent memory operations from the processors for the address to proceed to the shared memory.

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

Abstract: In some examples, a media controller includes a buffer and controller circuitry. The controller circuitry may receive, from a memory device linked to the media controller, an indication of a number of memory subunits that the memory device is divided into. The controller circuitry may also allocate, within the buffer, a number of logical memory buffers for the memory device greater than the number of memory subunits and indicate to a memory controller that a number of memory units accessible for the memory device is the number of logical memory buffers.

Abstract: A master device has a buffer for storing data transferred from, or to be transferred to, a memory system. Control circuitry issues from time to time a group of one or more transactions to request transfer of a block of data between the memory system and the buffer. Hardware or software mechanism can be provided to detect at least one memory load parameter indicating how heavily loaded the memory system is, and a group size of the block of data transferred per group can be varied based on the memory load parameter. By adapting the size of the block of data transferred per group based on memory system load, a better balance between energy efficiency and quality of service can be achieved.

Abstract: A semiconductor system includes a CPU connected to a heterogeneous memory module via a system bus. The heterogeneous memory module includes; a volatile memory module, a nonvolatile memory module, an internal bus separate from the system bus and connecting the volatile memory module and the nonvolatile memory module, and a swap manager configured to control execution of a swap operation transferring target data between the volatile memory module and nonvolatile memory module using the internal bus and without using of the system bus.

Abstract: A method and system for configuring a USB3 input/output port in a camera are disclosed. The method comprises responsive to an indication that a peripheral device is a non-USB3 device, remapping pins of the USB3 input/output port to a first predefined port configuration associated with an I2C protocol by remapping a RX1? pin to communicate a first I2C signal and remapping a RX1+ pin to communicate a second I2C signal, and responsive to successful authentication between the camera and the peripheral device via the I2C protocol, enabling communication with the peripheral device and remapping the pins of the USB3 input/output port to a second predefined port configuration compatible with operation of the authenticated peripheral device by remapping a TX2+ pin to communicate a first general purpose input/output signal and remapping a TX2? pin to communicate a second general purpose input/output signal.

Abstract: An information processing apparatus includes a processor; and a management controller coupled to the processor and configured to prohibit interruption from a slot to the processor when an input/output (IO) device is mounted in the slot by exchange or expansion; performs setting of the IO device while the interruption from the slot to the processor is prohibited; and permit the interruption from the slot to the processor when the setting of the IO device is completed.

Abstract: A memory controller manages memory access operations through a flash memory interface of a memory array of a solid-state storage device connected to a host. The memory controller executes a first memory access operation in the memory array. The first memory access operation has a first priority. The memory controller detects a suspending memory access operation available for execution in the memory array and having a higher priority than the first priority. The detection operation distinguishes between suspending memory access operations and non-suspending memory access operations. The memory controller suspends execution of the first memory access operation in the memory array and executes one or more memory access operations having higher priorities than the first priority and being available for execution in the memory array. The memory controller resumes the execution of the first memory access operation in the memory array.

Abstract: Memory sharing techniques are provided for offloading an application from a host processor to an integrated sensor hub (ISH). A methodology implementing the techniques according to an embodiment includes allocating a shared region of memory to be accessed by the host processor and by the ISH, in connection with the execution of a location application. The method also includes storing a location database in the shared region of memory. The location database is divided into segments, where each segment is associated with an area, for example, defined by a range of latitudes and longitudes. The method further includes transferring, through a direct memory access (DMA), one or more of the segments between the shared memory region and a second memory associated with the ISH. The method further includes executing at least a portion of the location application on the ISH, based on the data segments stored in the second memory.

Abstract: In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current.

Abstract: Systems and methods for controlling multi-function general purpose input/output (GPIO) pins in a management controller stack, such as a baseboard management controller (BMC) stack. The system includes a management controller, which includes multiple pins. The management controller provides multiple functionalities, and each of the functionalities is related to at least one of the pins. In operation, the management controller provides a graphic user interface, which shows the functionalities, allowing the user to input an instruction to select one of the functionalities. Upon receiving the selected functionality, for each of the pins related to the selected functionality, the management controller sets a value of a corresponding register to indicate a functional status of the pin, such that the pins may provide the selected functionality based on the value of the corresponding registers.

Abstract: In cases where local devices (6, 6a) support a master transfer function, a portion of the memory space, of each of local devices (6, 6a), to be controlled from system host (2) is mapped onto a memory space on system host (2) side and a plurality of local devices (6, 6a) are reconfigured as one virtual local device. This provides information processing apparatus (4) which, in cases of connection with the plurality of local devices (6, 6a), resolves resource shortage on system host (2) side by appropriately mapping necessary registers of local devices (6, 6a) onto a memory space for system host (2).

Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.

Abstract: A peripheral component interconnect express (PCIe) physical function is coupled to a controller. The controller is configured to allocate a first portion of resources for use by the PCIe physical function. A PCIe virtual function is coupled to the controller. The is configured to allocate a second portion of resources for use by the PCIe virtual function based, at least in part, on a total number of PCIe physical functions and a total number of PCIe virtual functions associated with the apparatus.

Abstract: An information processing apparatus includes a plurality of processing modules that are connected to each other on a ring bus, a connector for optionally attaching to an extension processing unit, a detection unit configured to detect attachment of the extension processing unit to the connector, and a bus switching unit configured to change, in a case where the detection unit detects the attachment of the extension processing unit, a path of the ring bus in such a manner that an extension processing module in the extension processing unit is connected.

Abstract: An automatic switching apparatus and an automatic switching method are disclosed. The automatic switching apparatus includes a universal serial bus Type-C input connector, a plurality of main links, at least one video output connector and at least one USB output connector. The automatic switching method includes the steps of: (a) detecting a use state of the plurality of main links; and (b) automatically switching the specification of the at least one USB output connector.

Abstract: A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus that comply with a USB standard, on in a first period and off in a second period, and a processing circuit that performs, in the second period, processing for transferring packets on a transfer route that includes the first bus, the first and second physical layer circuits, and the second bus. When a host chirp K/J is detected on the first bus by the first physical layer circuit, the second physical layer circuit outputs a host chirp K/J to the second bus in the state where connection between the first bus and the second bus is switched off by the bus switch circuit.

Abstract: Integrated circuits may have programmable logic circuitry and hard-coded circuitry. The hard-coded circuitry may include data circuitry, a processor, and memory. As the hard-coded circuitry has a limited capacity, a portion of the programmable logic circuitry may be configured using configuration data to serve as expanded soft-coded memory for the hard-coded processor. Instructions for controlling settings of the data circuitry may be stored on the hard-coded and soft-coded memory. An additional portion of the programmable logic circuitry may be configured using the configuration data to serve as a soft-coded processor that executes the instructions stored on the soft-coded memory. Use of the soft-coded processor and/or expanded soft-coded memory may allow for more advanced algorithms for initialization and calibration of the data circuitry than when only hard-coded memory is used and may allow for updated processor circuitry to be implemented.

Abstract: Provided are systems and methods for hot-plugging emulated peripheral devices (e.g., endpoints) into host devices that either have a hypervisor that does not support virtualized peripheral device or that do not include a hypervisor. In various implementations, a configurable peripheral device can emulate a switch that includes upstream ports and downstream ports. When a new endpoint device is requested, the configurable peripheral device can, using an emulation configuration for the new endpoint device, generate an emulation for the new endpoint device. The configurable peripheral device can connect the endpoint device to a downstream port, and then trigger a hot-plug mechanism, through which the host device can add the new endpoint device to the known hardware of the host device.

Abstract: Provided are an apparatus, system, and method relating to detecting, during a system boot operation, whether a device arranged to implement a first bus interface protocol is coupled to a system through a connector. A bus clock is programmed to be off in response to detection of no device implementing the first bus interface protocol being coupled to the system through the connector. After the bus clock is programmed to be off, a buffer is reprogrammed to assume that the connector implements a second bus interface protocol coupled to a storage device. After reprogramming the buffer, the apparatus, system, and method detect whether a device arranged to implement the second bus interface protocol is coupled to the connector, and the device arranged to implement the second bus interface protocol is initialized in response to detection that the device is coupled to the connector. Other embodiments are described and claimed.

Abstract: A buffer controller includes a pointer generator, a code converter, a synchronizer, a code restorer, and a comparator. The pointer generator operates according to a first clock signal, and generates a first pointer by encoding a first address of a buffer with a first code. The code converter generates a first transmission pointer by converting the first pointer with a second code or a third code according to an amount of data stored in or read from the first address. The synchronizer synchronizes the first transmission pointer with a second clock signal. The code restorer generates a first comparison pointer by restoring the first transmission pointer, synchronized with the second clock signal, with the first code. The comparator compares the first comparison pointer with a second pointer. The second pointer defines a second address of the buffer with the first code.

Abstract: A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

Abstract: Systems, methods, and computer-readable media for transferring data between a host platform and modem circuitry are provided. At low data rates, data may be stored by on-chip memory, and data may be transferred from the on-chip memory to the host platform over an interconnect (IX) when a first aggregation period expires. At medium data rates, data may be stored in both the on-chip memory and in in-package or off-chip memory, and the data may be transferred from the on-chip memory and off-chip memory to the host platform over the IX when a second aggregation period expires. At high data rates, the on-chip memory may serve as an elastic buffer, and the data may be streamed directly through the on-chip memory to the host platform over the IX. Other embodiments are described and/or claimed.

Abstract: A board portal system provides the ability to manage multiple boards, where each of the boards may be a separate legal entity. The board portal may provide the ability to establish links between the multiple boards and create parent-child relationships with subsidiary boards. With the board portal, users can create content and make it viewable and accessible across multiple boards that related through a parent-child relationship. At the same time, the board portal maintains a requisite level of separation between the related boards in the portal using encryption and/or other separation techniques. As a result, the board portal facilitates flexible workflow patterns and communication processes based on the proper hierarchical structure that exists between the parent organization and its subsidiaries.

Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

Abstract: A neural network unit includes a programmable indicator, a first memory that holds first operands, a second memory that holds second operands, neural processing units (NPU), and activation units. Each NPU has an accumulator and an arithmetic unit that performs a series of multiply operations on pairs of the first and second operands received from the first and second memories to generate a series of products, and a series of addition operations on the series of products to accumulate an accumulated value in the accumulator. The activation units perform activation functions on the accumulated values in the accumulators to generate results. When the indicator specifies the first action, the neural network unit writes to the first memory the results generated by the activation units. When the indicator specifies the second action, the neural network unit writes to the first memory the accumulated values in the accumulators.

Abstract: Provided are techniques for storing and retrieving restricted datasets to and from a cloud network with non-restricted datasets. A request to dump datasets from one or more storage devices to the cloud storage is received, wherein the datasets include restricted datasets and non-restricted datasets, and wherein the restricted datasets are in a format that is not supported by the cloud storage. The restricted datasets are identified. The restricted datasets are converted to a format that is supported by the cloud storage to generate converted datasets. The converted datasets and the non-restricted datasets are dumped to one container in the cloud storage.

Abstract: The embodiments set forth techniques for generating snapshots of file system volumes without requiring the implementation of reference counts. A file system can manage snapshot identifiers (IDs) within an object map that corresponds to the file system volume, where each snapshot ID represents a different existing snapshot of the file system volume. A new snapshot can be generated simply by (1) establishing a new snapshot ID based on a current transaction ID managed for the file system volume, and (2) closing the current transaction ID and generating a new current transaction ID. In turn, the new current transaction ID is assigned as a transaction ID within mapping entries that are established/updated after the snapshot is established. In this manner, the transaction ID assigned to each mapping entry can be analyzed against the snapshot IDs to determine the snapshots (if any) to which the mapping entry corresponds.

Abstract: A method for secure storage of data and retrieval of desired data from a cloud-based service environment includes receiving the data from a tenant having a unique tenant ID, dynamically extracting data to be indexed from the received data, and creating index information from the extracted data. The index information is encrypted with a tenant private key, the encrypted index information is uploaded into the cloud environment in the form of index files, and a last uploaded index file is queried for in the cloud environment. The encrypted index information of the index file is decrypted with the tenant private key, the decrypted index information is searched for a relevant patient record, and the corresponding desired data is retrieved from the cloud environment. The desired data is rendered onto a client application. The index files are created from the index information in chronological order of receipt of the data.

Abstract: Managing data blocks stored in a data processing system comprises logging input/output (I/O) accesses to an in-memory buffer with each log entry recording at least identifiers of the data blocks accessed and when the data blocks were accessed. When the size of the log entries reaches a predetermined threshold, the system may append log entries of the in-memory buffer to the end of a history log file. The history log file is analyzed to determine patterns of accesses, and each pattern is stored in a record in an access heuristics database. While processing a request for access to a data block, the data processing system queries the access heuristics database to obtain prior access patterns associated with the data block. A data management action may be taken based on the prior access patterns.

Abstract: An interface for enabling a computer device to utilize data property-based data placement inside a nonvolatile memory device comprises: executing a software component at an operating system level in the computer device that monitors update statistics of all data item modifications into the nonvolatile memory device, including one or more of update frequencies for each data item, accumulated update and delete frequencies specific to each file type, and an origin of the data item; storing the update statistics of each of the data items and each of the data item types in a database; and intercepting all operations, including create, write, and update, of performed by applications to all the data items, and automatically assigning a data property identifier to each of the data items based on current update statistics in the database, such that the data items and assigned data property identifiers are transmitted over a memory channel to the non-volatile memory device.

Abstract: A system and method for data storage, transfer, synchronization, and security using recursive encoding, wherein data is deconstructed into chunklets, and is processed through a series of reference code libraries that reduce the data to a sequence of reference codes, and where the output of each reference library is used as the input to the next.

Abstract: The present disclosure provides systems and techniques for efficient locking of datasets in a database when updates to a dataset may be delayed. A method may include accumulating a plurality of updates to a first set of one or more values associated with one or more features. The first set of one or more values may be stored within a first database column. Next, it may be determined that a first database column update aggregation rule is satisfied. A lock assigned to at least a portion of at least a first database column may be acquired. Accordingly, one or more values in the first set within the first database column may be updated based on the plurality of updates. In an implementation, the first set of one or more values may be associated with the first lock.

Abstract: A method for generating a query for version information on a file stored a database file system that is managed by a database server. When a client on a remote client machine sends a file operation request, the database management system, receives the file operation request and creates a database query for the requested file operation and an additional query for a set of version identifiers that identify the previous versions of the requested file of the requested file operation. The database management system executes the queries and generates a set of version identifiers, where each identifier from the set of version identifiers represents a specific version of the requested file at a particular point in time in the past.

Abstract: Secure containerized user specific isolated data storage is disclosed. For example, a first isolated guest is instantiated, including a first account specific database with a write-protected schema, a write-protected first lower storage layer and a first upper storage layer. A first account is authenticated with the first isolated guest. A first change to the first account specific database is saved in the first upper storage layer based on executing a first database command from the first account. A second isolated guest is instantiated, including a second account specific database with the write-protected schema, a write-protected second lower storage layer and a second upper storage layer. The second account is authenticated with the second isolated guest. A second change to the second account specific database is saved in the second upper storage layer based on executing the second database command from the second account.

Abstract: Techniques for dynamically generating database views and class objects for allowing access to domain data stored in a repository are provided. A computer-implemented method, a system, and/or a machine-readable medium storing instructions executable by one or more processors may include generating a database view and a class object using metadata included in a domain model, and retrieving domain data from a repository using the database view and the class object. For example, a method may include obtaining a domain model from a repository, the domain model including metadata corresponding to a set of domain data stored in the repository, generating a database view of a subset of the set of domain data using the metadata, generating a class object for the subset using the metadata, generating mapping information, and retrieving the subset of domain data from the repository using the database view, the class object, and the mapping information.

Abstract: An apparatus, system, and method are disclosed for data management. The method includes writing data in a sequential log structure. The method also includes receiving a time sequence request from a client. The method further includes servicing the time sequence request based on a temporal order of the data in the sequential log structure.

Abstract: In one embodiment, a method includes identifying and recursively populating a geographic tile with entities. Recursively populating a geographic tile with entities includes: sending a request to a third-party server for entities located near a representative point of the geographic tile; calculating a maximum distance from the representative point among the entities received; and determining whether a bounding perimeter based on the maximum distance encompasses the geographic tile. If the bounding perimeter encompasses the geographic tile, the retrieved entities located within the geographic tile are stored in association with an identifier for the geographic tile. If the bounding perimeter does not encompass the geographic tile, the geographic tile is divided and the subdivision tiles are recursively populated.

Abstract: A method includes executing an initial instance of a change log process for a distributed system, each instance of the change log process configured to store, on memory hardware in communication with the data processing hardware, a transaction history of transactions executed on the distributed system. The method also includes receiving transaction requests for executing corresponding transactions on the distributed system and determining a change log load based on the received transaction requests. The method includes executing at least one subsequent instance of the change log process when the change log load satisfied a threshold load. When multiple instances of the change log process are executing, the method includes ceasing execution of the at least one subsequent instance of the change log process and merging the transaction history of the initial instance of the change log process and the transaction history of the at least one subsequent instance of the change log process.

Abstract: Embodiments are directed to a self-cleaning token vault for managing tokens generated on behalf of a resource provider. The generated tokens may be stored at the token vault. Embodiments provide a token manager (which can be embodied in the token vault or provided as a separate module) that continuously monitor the token vault for expired or redundant tokens. The token manager may enable the resource provider to assign level flags to the tokens and assign level values to the level flags. The level value may indicate an importance or a use characteristic of the token. Upon identifying tokens that are no longer necessary, the self-cleaning token vault or the token manager may automatically remove the tokens from the token vault.

Abstract: An information handling system maintains a log-with-index (LWI) structure that includes a log for inserting and deleting records, each of which includes a key, and a binary index for maintaining an index of log records. The log may be stored to disk for persistence. Insertions of new records into the log may occur sequentially to ensure adequate performance. The index tree may be maintained in memory for performance. When the log is full, log records may be written in key-sorted order to a new tablet in a tablet library. Two tablets may be merged from time to time. Merging may include iteratively performing a plurality of atomic merges for each of a plurality of atomic portions. During atomic merges, tablet index data may be modified in copy-on-write fashion to preserve existing data until the atomic merge completes.

Abstract: The present disclosure relates to systems and methods for updating a node profile status based on automated electronic activity. The method may include accessing electronic activities transmitted or received via electronic accounts; identifying, for an electronic activity account, a second electronic activity automatically generated and transmitted in response to a first electronic activity transmitted from the electronic activity account; determining that the second electronic activity is an automated electronic activity responsive to the first electronic activity; determining, responsive to parsing content included in a body of the second electronic activity, a context related to the second electronic activity; identifying a node profile corresponding to the recipient of the first electronic activity and identified by the second electronic activity; and updating the identified node profile corresponding to the recipient based on the context.

Abstract: A method for enriching an object in a database may include determining, by a trained machine learning model, that a first object at the database is same and/or similar to a second object at the database. The first object and the second object may be part of a schema of the database. The second object may be subordinate to the first object. In response to the determination that the first object is same and/or similar to the second object, one or more attributes associated with the second object may be added to the first object. Related systems and articles of manufacture including computer program products are also provided.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for dynamic partition selection. One of the methods includes receiving a representation of a query plan generated for a query, wherein the query plan includes a dynamic scan operator that represents a first computing node obtaining tuples of one or more partitions of a table from storage and transferring the tuples to a second computing node that executes a parent operator of the dynamic scan operator. A partition selector operator is generated corresponding to the dynamic scan operator. A location in the query plan is determined for the partition selector operator. A modified query plan is generated having the partition selector operator at the determined location.

Abstract: A method includes receiving an initial pipeline including a sequence of commands for execution on a computing system, and obtaining, for each command in the sequence of commands, semantic information. The sequence of commands includes a command with incomplete semantic information. The method further includes generating an abstract semantic tree (AST) with the semantic information and a placeholder for the incomplete semantic information, and manipulating the AST to generate a revised AST. The revised AST corresponds to a revised pipeline that reduces an execution time on the computing system. The method further includes executing the revised pipeline.