Abstract: A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer comprises a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material.

Abstract: A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.

Abstract: A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip.

Abstract: A semiconductor device, and a method of fabrication, is introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and a first plurality of bonding pads and a second plurality of bonding pads are formed in the recesses. In an embodiment, the first plurality of bonding pads have a first width and a first pitch, and the second plurality of bonding pads have the first width and are grouped into clusters. The first plurality of bonding pads and the second plurality of bonding pads in the first substrate are aligned to a third plurality of bonding pads in a second substrate and are bonded using a direct bonding method.

Abstract: A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, an isolation structure surrounding the pixel sensor and disposed in the substrate, a dielectric layer disposed over the pixel sensor on the front side of the substrate, and a plurality of conductive structures disposed in the dielectric layer and arranged to aligned with the isolation structure.

Abstract: In some embodiments, the present disclosure relates to an image sensor integrated chip. The integrated chip has an image sensing element arranged within a substrate. A first dielectric is disposed in one or more trenches within a first side of the substrate. The one or more trenches laterally surround the image sensing element. The substrate includes a recessed portion arranged along the first side of the substrate and defined by second sidewalls of the substrate directly over the image sensing element. The second sidewalls of the substrate are angled to meet at a point disposed along a horizontal plane that intersects the first dielectric within the one or more trenches.

Abstract: A group of shared pixels comprises: a first shared pixel comprising a first photodiode and a first transfer gate; a second shared pixel comprising a second photodiode and a second transfer gate; a third shared pixel comprising a third photodiode and a third transfer gate; a fourth shared pixel comprising a fourth photodiode and a first transfer gate; a first floating diffusion shared by the first shared pixel and the second shared pixel; a second floating diffusion shared by the third shared pixel and the fourth shared pixel; a capacitor coupled to the first floating diffusion through a first dual conversion gain transistor, and the second floating diffusion through a second dual conversion gain transistor; wherein the capacitor is formed in an area covering most of the first shared pixel, the second shared pixel, the third shared pixel, and the fourth shared pixel.

Abstract: A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, and a color filter disposed over the pixel sensor. The pixel sensor includes a plurality of first micro structures disposed over the back side of the substrate, and the color filter includes a plurality of second micro structures disposed over the back side of the substrate.

Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate and an image sensing element disposed within the substrate. The substrate has sidewalls defining a plurality of protrusions over the image sensing element. A first one of the plurality of protrusions including a first sidewall having a first segment. A line that extends along the first segment intersects a second sidewall of the first one of the plurality of protrusions that opposes the first sidewall.

Abstract: An integrated circuit is provided with a (bridge) rectifier circuit configured to couple to an alternating current (AC) supply to a (string of) LEDs monolithically fabricated on substrate, preferably on a patterned sapphire substrate (PSS). The rectifier including at least one schottky barrier diode configured to have a reverse-bias breakdown voltage substantially equal to or greater than half a peak voltage of the AC supply. Further embodiments include a method for fabricating an integrated Schottky barrier diode (SBD) with a LED on a LED wafer. Some embodiments can include etching processes to a wafer that may include a plurality of processing cycles. Some embodiments can further include a wafer having a patterned substrate. The wafer with the patterned substrate may have an interface layer configured to facilitate increasing a forward bias current density of the SBD.

Abstract: It is an object of the present invention to provide an image display device in which it is possible to adjust the spectrum of light emitted by pixels and adjust the chromaticity of the light emitted by the pixels. Provided is an image display device having a pixel region in which each pixel comprises a plurality of subpixels and the pixels are arranged in a matrix, wherein each of the subpixels includes a plurality of light-emitting layers overlapping each other with an electrode sandwiched therebetween, and the plurality of light-emitting layers each contain a quantum dot material and have different peak emission wavelengths from each other.

Abstract: A semiconductor device includes a first conductive wiring, at least one first dielectric layer, at least one second dielectric layer and a second conductive wiring. The at least one first dielectric layer is over the first conductive wiring. The at least one second dielectric layer is over the at least one first dielectric layer. The second conductive wiring is over the at least one second dielectric layer. The dielectric constant of the at least one second dielectric layer is higher than the dielectric constant of the at least one first dielectric layer.

Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Abstract: The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate and a doped region at least partially in the substrate, a first metal layer over the transistor region, and a magnetic tunneling junction (MTJ) between the transistor region and the first metal layer. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a transistor region over a substrate, the transistor region comprising a gate and a doped region, forming a magnetic tunneling junction (MTJ) over the transistor region, electrically coupling to the transistor region, and forming a first metal layer over the MTJ, electrically coupling to the MTJ and the transistor region.

Abstract: The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.

Abstract: A highly reliable light-emitting element which can keep favorable characteristics throughout long-time driving is provided. In addition, a light-emitting element with high color purity and high emission efficiency is provided. Furthermore, a light-emitting device having a long lifetime in which the light-emitting element is used is provided. Moreover, an electronic device and a lighting device each of which has a long lifetime are provided. In the light-emitting element including an EL layer between a pair of electrodes, the EL layer has a stacked-layer structure of a first light-emitting layer, a second light-emitting layer, and a third light-emitting layer. The light-emitting layer includes an electron-transport material, a hole-transport material, and a light-emitting material. Furthermore, light emitted from the first light-emitting layer and light emitted from the third light-emitting layer have the same color and each have a longer wavelength than light emitted from the second light-emitting layer.

Abstract: In this manufacturing method, in a blue fluorescent light-emitting layer formation step, a blue fluorescent light-emitting layer is formed in both a subpixel and a subpixel; in a green fluorescent light-emitting layer formation step, a green fluorescent light-emitting layer is formed in both the subpixel and a subpixel; and in a red light-emitting layer formation step, a red light-emitting layer is formed in both the subpixel and a subpixel. In at least two of the abovementioned steps, linear vapor deposition is performed using a slit mask having an opening that is provided so as to extend across a plurality of pixels.

Abstract: An organic light-emitting structure is described. The organic light-emitting structure includes a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, and a fourth light-emitting unit. Each of the first light-emitting unit, the second light-emitting unit, the third light-emitting unit, and the fourth light-emitting unit comprises a first electrode, a second electrode, and an organic laminated body placed between the first electrode and the second electrode. One of the first electrode and the second electrode is a translucent electrode. At least one light-emitting unit is a fluorescent light-emitting unit. The color gamut range of the organic light-emitting structure is increased, the color saturation of the light-emitting device is improved, and quantity of colors is increased, so that the development trend of color reproducibility for the display devices can be satisfied.

Abstract: The present invention provides an OLED display, comprising a substrate, a thin film transistor layer, a blue light emitting layer, a cover plate and a color conversion layer; wherein the color conversion layer comprises a plurality of red conversion units and green conversion units, and both materials of the red conversion units and the green conversion units are organic metal halide perovskite materials; the blue light emitted by the blue light OLED correspond to the red, the green and the blue sub pixel regions, and respectively converted into red light by the red conversion units to emit, converted into green light by the green conversion units to emit and emitted through the cover plate, directly to obtain the red, green, blue lights of high color saturation to realize the color display of the high color gamut.

Abstract: A display device, in which a first pixel and a second pixel are defined, includes: a display panel including a base substrate and a light-emitting element disposed on the base substrate; a color filter layer disposed over the display panel and including a first color filter disposed in the first pixel and a second color filter disposed in the second pixel; and a first organic layer disposed over the display panel, and including a pigment or a dye. The first pixel displays a first color, and the second pixel displays a second color different from the first color. The organic layer is integrally formed over the first pixel and the second pixel.

Abstract: The present invention disclosures a color filter used for a WOLED display apparatus. The color filter includes a red pixel section, a green pixel section, a blue pixel section and a white pixel section. A red photoresist is disposed in the red pixel section, a green photoresist is disposed in the green pixel section, and a blue photoresist is disposed in the blue pixel section. The white pixel section includes a first sub-section, and a red photoresist, a green photoresist or a blue photoresist is disposed in the first sub-section. The present invention further disclosures a WOLED display apparatus including above color filter. The color filter of the present invention can reduce a Y value of chromaticity coordinate of the white pixel. Required brightness of the monochromatic pixels drops at a white image and power consumption is reduced. Accordingly, the life of display devices rises.

Abstract: In one embodiment, an electronic display includes a first plurality of hexagon-shaped pixels and a second plurality of hexagon-shaped pixels that are coplanar with the first plurality of hexagon-shaped pixels. The first plurality of hexagon-shaped pixels each include an infrared (IR) emitter subpixel that is operable to emit IR light. The second plurality of hexagon-shaped pixels each include an IR detector subpixel that is operable to detect IR light. Each IR emitter subpixel and each IR detector subpixel includes an anode layer and a cathode layer. Each particular IR emitter subpixel includes an IR emissive layer located between the anode layer and the cathode layer of the particular IR emitter subpixel. Each particular IR detector subpixel includes an IR detector layer located between the anode layer and the cathode layer of the particular IR detector subpixel.

Abstract: Disclosed is a transparent display device. The transparent display device includes a first display panel, including a transmissive area and an emissive area where a first pixel including a plurality of subpixels displaying an image is provided, and a second display panel including a second pixel provided to overlap the emissive area and the transmissive area of the first display panel, the second display panel being provided on a first surface of the first display panel. The second pixel of the second display panel controls an amount of light incident on the first display panel, thereby preventing a visibility of an image displayed by the first display panel from being reduced by external light.

Abstract: An OLED display panel and a display device are provided. An image sensor is added below OLED light-emitting devices, a light shielding layer including at least one pinhole imaging region is added between the image sensor and the OLED light emitting device, with the pinhole imaging region corresponding to a gap position between the OLED light-emitting devices in the light shielding layer and staggered from light shielding parts in a signal routing and a control device, an object located above the OLED display panel is imaged on the image sensor.

Abstract: The present disclosure provides an AMOLED back plate and a method for manufacturing the same. The manufacturing method includes: forming source and drain electrodes and a first via hole on a substrate having a light shielding layer and a buffer layer formed thereon, by a patterning process; depositing an active layer film and a gate insulating layer film sequentially, and forming an active layer, a gate insulating layer and a second via hole by a patterning process, wherein the active layer connected with the light shielding layer by the first via hole; forming a gate electrode and a transparent anode sequentially, wherein the transparent anode is arranged in a light emitting area and connected with one of the source and drain electrodes through the second via hole.

Abstract: A display device according to an embodiment includes a substrate having a display area, and a peripheral area outside the display area including a first peripheral area adjacent to the display area, a first bending area extending from the first peripheral area, and a second peripheral area extending from the first bending area, and overlapping the first peripheral area, a display member at the display area, and including a first display area, and a second display area around the first display area, and a plurality of align keys on the substrate, wherein the first peripheral area includes a flat peripheral area corresponding to an area between the first display area and the first bending area, and a second bending area between the second display area and an end of the substrate, and wherein the plurality of align keys include a first align key at the flat peripheral area, and a second align key at the second peripheral area.

Abstract: The present disclosure discloses a method for manufacturing an OLED display device, including: forming a pixel-defining layer on a substrate to define a plurality of pixel regions, forming an organic film layer in each pixel region, determining at least one area to be compensated in the pixel region according to a surface shape of the organic film layer; aligning an evaporation source, an opening of a mask and the pixel region, making each opening of the mask respectively correspond to the position of each area to be compensated; forming an electron function layer in the area to be compensated by means of evaporation of the evaporation source, wherein the electron function layer is configured to compensate a surface shape of the organic film layer in the pixel region.

Abstract: An OLED display device is disclosed, and the metal connection electrode is connected to the auxiliary electrode through a recessed hole; the recessed hole forms a first cavity and a second cavity communicating with each other, and the first cavity extends from an edge line of the second cavity away from the pixel electrode in the same direction; the pixel definition layer is above the array substrate, and reserved with grooves corresponding to the recessed holes and the pixel electrodes; an OLED semiconductor layer on the pixel definition layer covers on the pixel electrode and the metal connection electrode, and also extends into the first cavity to be connected with the auxiliary electrode; a cathode is on the OLED semiconductor layer, and extends into the first cavity to be connected with the auxiliary electrode, and is in a discontinuous connection state with the recessed hole as a breakpoint.

Abstract: There is provided a method of forming a light source, the method comprising providing a backplane comprising a backplane substrate and a semiconductor particle formed separately from the backplane substrate and then fixed upon the backplane substrate at a predetermined position. The semiconductor particle can be planarized to remove a portion of the semiconductor particle and to expose at a cross-section of the semiconductor particle a planar surface. Moreover, the backplane may comprise a controllable gated electronic component on or directly beneath the planar surface. The controllable gated electronic component may be configured to control an LED emitter. The method further comprises providing the LED emitter comprising one or more LEDs electrically connected to the backplane such that at least one of the LEDs is electrically connected to the controllable gated electronic component.

Abstract: To make it possible to improve display quality more. Provided is a display device including: a pixel unit in which a plurality of pixel circuits (PIX_A, PIX_B, PIX_C) each of which includes a light emitting element and a driving circuit configured to drive the light emitting element are arranged in a matrix form. In a diffusion layer in which transistors included in the driving circuits of the pixel circuits (PIX_A, PIX_B, PIX_C) are formed, an electricity supply region (223) that is an active area for supplying an electric potential to a well is provided between mutually adjacent ones of the pixel circuits (PIX_A, PIX_B, PIX_C).

Abstract: A display device includes: a substrate; and a plurality of pad terminals on the substrate, wherein each of the plurality of pad terminals includes a lower conductive layer and an upper conductive layer disposed on the lower conductive layer, an elastic layer disposed between the lower conductive layer and the upper conductive layer, and at least a portion of the lower conductive layer being electrically connected to at least a portion of the upper conductive layer in a region in which the elastic layer is not arranged.

Abstract: A display device includes a substrate having a display area and a non-display area, a plurality of pixels in the display area, scan lines for supplying a scan signal to the pixels, the scan lines extending in a first direction, data lines for supplying a data signal to the pixels, the data lines extending in a second direction crossing the first direction, and a first dummy part in the non-display area, adjacent to an outermost pixel, connected to an outermost data line of the display area, forming a parasitic capacitor with the outermost pixel, and including a first dummy data line and a first dummy power pattern extending in parallel to the data lines.

Abstract: An impedance circuit includes a poly-resistor and a controller. The poly-resistor has a first terminal and a second terminal. The controller generates a first control voltage and a second control voltage. The resistance between the first terminal and the second terminal of the poly-resistor is determined according to the first control voltage and the second control voltage. The second control voltage is different from the first control voltage. The proposed impedance circuit can improve the linearity of the poly-resistor.

Abstract: A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration CX. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration CY lower than the concentration CX. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration CX. A sign of a TCR of the second polycrystalline silicon changes at the concentration CY.

Abstract: A reliable metal insulator metal (MIM) capacitor is disclosed. The MIM capacitor is disposed over at least an interlevel dielectric (ILD) layer of a plurality of ILD layers with interconnects disposed over a substrate. The MIM capacitor includes a capacitor dielectric disposed between top and bottom metal capacitor electrodes. The edges of the top metal electrode at the interface with the capacitor dielectric are rounded. The rounded edges of the top capacitor electrode at the interface with the capacitor dielectric reduce edge electric field, thereby improves time-dependent dielectric breakdown (TDDB) reliability of the capacitor.

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.

Abstract: High aspect ratio passive electrical components are presented formed from a single-piece silicon (Si) substrate having a textured surface with at least one high aspect ratio structure. The high aspect ratio structure includes a Si core having a width (CX), a height (CZ), and a minimum aspect ratio of CZ-to-CX of at least 5:1. An electrical conductor layer overlies the Si core. The electrical component may be a capacitor, inductor, or transmission line. In the case of a capacitor, the substrate textured first surface is made up of a plurality of adjacent high aspect ratio conductor-dielectric-Si (CDS) structures. Each CDS structure includes: a Si core, a dielectric layer overlying the Si core, and an electrical conductor layer overlying the dielectric layer. The Si cores may be formed in the geometry of parallel ridges, columns, or as a honeycomb. Each Si core comprises at least 90% of the CDS structure height.

Abstract: A method for forming a semiconductor structure is disclosed. The method provides a substrate with an insulator pad overlying at least a top portion of the substrate. The method further includes forming a plurality of dielectric columns overlying the substrate and the dielectric pad. Each dielectric column is separated from another dielectric column to form a corresponding plurality of aspect-ration trapping (ART) trenches. The insulator pad spans a bottom portion of a first ART trench of the plurality of ART trenches. A portion of the substrate spans a bottom portion of a second ART trench of the plurality of ART trenches. The method further includes forming a III-V semiconductor material stack in the second ART trench. The method further includes forming a first resistive region in the first ART trench, wherein the first resistive region is in contact with the insulator pad.

Abstract: An N-type polysilicon crystal, a manufacturing method thereof, and an N-type polysilicon wafer are provided. The N-type polysilicon crystal has a slope of resistivity and a slope of defect area percentage. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to resistivity presented by a unit of Ohm·cm (?·cm), the slope of resistivity is 0 to ?1.8 at the solidified fraction of 0.25 to 0.8. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to defect area percentage (%), the slope of defect area percentage is less than 2.5 at the solidified fraction of 0.4 to 0.8.

Abstract: A high voltage transistor with low on resistance is disclosed. The transistor may include at least one cut out region in the drift region under the drain of the transistor. The cut out region is devoid of the drift well which connects the drain to the channel. Cut out regions may be distributed along the width direction of the drain region of the transistor. The transistor may alternatively or further include a vertical polysilicon plate surrounding the device region. The vertical polysilicon plate may be implemented as a deep trench isolation region. The deep trench isolation region includes a deep trench lined with an insulation collar and filled with polysilicon. The vertical polysilicon plate reduces an on resistance to improve device performance.

Abstract: A semiconductor device including: a drift region formed on a semiconductor substrate; a gate trench portion provided on an upper surface of the semiconductor substrate; a first and second mesa portion adjacent to one and the other of the gate trench portions; an accumulation region provided above the drift region in the first mesa portion; a base region provided above the accumulation region; a emitter region provided between the base region and the upper surface of the semiconductor substrate; an intermediate region provided above the drift region in the second mesa portion; a contact region provided above the intermediate region, wherein the gate trench portion has a gate conductive portion; a bottom portion of the gate conductive portion has a first step and second step; and, at least part of the intermediate region is provided between the steps and the bottom portion of the gate trench portion will be provided.

Abstract: A method for manufacturing a semiconductor device comprises forming first groove, depositing, and ion-implanting. At the step of forming the first groove, the first groove is formed in a stacked body comprising a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first groove has a bottom portion located in the second semiconductor layer. At the depositing step, a p-type impurity is deposited on side portion and the bottom portion of the first groove. At the ion-implanting step, a p-type impurity is ion-implanted into the first semiconductor layer through the first groove.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate structure including a high side region, a low side region, a level shift region and an isolation region. The low side region is separated from the high side region. The level shift region and the isolation region are disposed between the low side region and the high side region. The level shift region is separated from the high side region by the isolation region. A doped isolation region, which is disposed in the isolation region, includes a first doped portion and a second doped portion adjacent to the first doped portion. The depth of the first doped portion is decreased linearly along a first direction from the isolation region to the level shift region. The depth of the second doped portion is decreased linearly along a second direction from the isolation region to the high side region.

Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.

Abstract: A semiconductor device includes a gate trench extending into a Si substrate, the gate trench including a gate electrode and a gate dielectric separating the gate electrode from the Si substrate. The semiconductor device further includes a body region in the Si substrate adjacent the gate trench, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure extending along at least part of the channel region and disposed between the channel region and the highly doped body contact region. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si.

Abstract: Structures, devices and methods are provided for forming nanowires on a substrate. A first protruding structure is formed on a substrate. The first protruding structure is placed in an electrolytic solution. Anodic oxidation is performed using the substrate as part of an anode electrode. One or more nanowires are formed in the protruding structure. The nanowires are surrounded by a first dielectric material formed during the anodic oxidation.

Abstract: Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region.

Abstract: A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer over the semiconductor substrate is formed. A plurality of dopants are formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion.