Patents Issued in December 17, 2019
  • Patent number: 10510589
    Abstract: Methods for seam and void-free gapfilling, such as gapfilling high aspect ratio trenches with amorphous silicon, are provided. A method generally includes depositing amorphous silicon over a semiconductor device having one or more features thereon, annealing the deposited amorphous silicon to heal one or more seams in the deposited amorphous silicon between the one or more features, and etching the annealed amorphous silicon to remove one or more voids in the annealed amorphous silicon between the one or more features. The deposition, anneal, and etch processes are generally repeated any suitable number of times to achieve amorphous silicon gapfill without any seam or void between the one or more features.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 17, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Rui Cheng, Yi Yang, Abhijit Basu Mallick
  • Patent number: 10510590
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: December 17, 2019
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Patent number: 10510591
    Abstract: A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Chin-Fu Kao, Chih-Yuan Chien, Szu-Wei Lu
  • Patent number: 10510592
    Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Kuan-Chieh Huang
  • Patent number: 10510593
    Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
  • Patent number: 10510594
    Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
  • Patent number: 10510595
    Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee
  • Patent number: 10510596
    Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 10510597
    Abstract: Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit. Additional methods are disclosed.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pin-Nan Tseng, Chia-Shiung Tsai, Ping-Yin Liu
  • Patent number: 10510598
    Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10510599
    Abstract: An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Ho Che Yu
  • Patent number: 10510600
    Abstract: A butted contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region. The structure includes a butted contact disposed above and extending from the first source or drain region to at least one of the first or second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Leo Hsu, Sheng-Liang Pan
  • Patent number: 10510601
    Abstract: A method of manufacturing a device includes exposing at least one of a source/drain contact plug or a gate contact plug to a metal ion source solution during a manufacturing process, wherein a constituent metal of a metal ion in the metal ion source solution and the at least one source/drain contact plug or gate contact plug is the same. If the source/drain contact plug or the gate contact plug is formed of cobalt, the metal ion source solution includes a cobalt ion source solution. If the source/drain contact plug or the gate contact plug is formed of tungsten, the metal ion source solution includes a tungsten ion source solution.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ling-Fu Nieh, Chun-Wei Hsu, Pinlei Edmund Chu, Chi-Jen Liu, Liang-Guang Chen, Yi-Sheng Lin
  • Patent number: 10510602
    Abstract: Methods and apparatus to form fully self-aligned vias are described. A first metal film is formed in the recessed first conductive lines and on the first insulating layer of a substrate comprising alternating conductive lines and a first insulating layer. Pillars and a sheet are formed from the first metal film. Some of the pillars and a portion of the sheet are selectively removed and a second insulating layer is deposited around the remaining pillars and sheet. The remaining pillars and sheet are removed to form vias and a trench in the second insulating layer. A third insulating layer is deposited in the vias and trench and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Mirocmaterials LLC
    Inventors: Ying Zhang, Abhijit Basu Mallick, Yung-Chen Lin, Qingjun Zhou, He Ren, Ho-yung David Hwang, Uday Mitra
  • Patent number: 10510603
    Abstract: An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Hui Huang, Hung-Pin Chang, Sao-Ling Chiu, Shang-Yun Hou, Wan-Yu Lee
  • Patent number: 10510604
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 10510605
    Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
  • Patent number: 10510606
    Abstract: A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a second IC die, and a passivation layer is formed. The scribe line separates the first and second IC dies, and the passivation layer covers the first and second IC dies. The first IC die comprises a circuit and a pad structure electrically coupled to the circuit. The pad structure comprises a first pad, a second pad, and a bridge. The bridge is within the scribe line and connects the first pad to the second pad. The passivation layer is patterned to expose the first pad, but not the second pad, and testing is performed on the circuit through the first pad. The semiconductor workpiece is cut along the scribe line to individualize the first and second IC dies, and to remove the bridge.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yueh-Chuan Lee, Chia-Chan Chen, Ching-Heng Liu
  • Patent number: 10510607
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device is provided. The method generally includes forming a recess in a fin, the fin being on a substrate. The recess is proximate a gate structure over the fin. The method includes epitaxially growing a source/drain region in the recess using a remote plasma chemical vapor deposition (RPCVD) process. The RPCVD process includes using a silicon source precursor and a hydrogen carrier gas.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ching Lin, Chii-Horng Li, Chien-I Kuo, Li-Li Su
  • Patent number: 10510608
    Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie-Cheng Deng, Horng-Huei Tseng, Yi-Jen Chen
  • Patent number: 10510609
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; forming a mask layer on the first fin-shaped structure; and performing a first anneal process so that the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: December 17, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin
  • Patent number: 10510610
    Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: December 17, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
  • Patent number: 10510611
    Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 17, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Che-Wei Yang, Hao-Hsiung Lin, Samuel C. Pan
  • Patent number: 10510612
    Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Cyuan Lu, Chunyao Wang, Jr-Hung Li, Chung-Ting Ko, Chi On Chui
  • Patent number: 10510613
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Xusheng Wu, Haigou Huang, John H. Zhang, Pei Liu, Laertis Economikos
  • Patent number: 10510614
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
  • Patent number: 10510615
    Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor strip protruding above a substrate, forming isolation regions on opposing sides of the semiconductor strip, recessing the isolation regions in a first chamber using a first etching process, and increasing a planarity of the isolation regions in the first chamber using a second etching process.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Chan Weng, Wan-Chun Kuan, Yi-Wei Chiu, Meng-Je Chuang
  • Patent number: 10510616
    Abstract: A method of making a semiconductor device with an air gap for a terminal of a semiconductor device includes forming a sacrificial sidewall spacer and removing the spacer after the formation of contact structures for the semiconductor device. The air gap is located in portions of the wafer where the sacrificial air gap was removed. Since the contacts are formed prior to the removal of the sacrificial spacers, air gaps can advantageously be formed without electrically conductive contact material undesirably being deposited in locations of the desired air gap.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 17, 2019
    Assignee: NXP USA, INC.
    Inventors: Mehul D. Shroff, Douglas Michael Reber
  • Patent number: 10510617
    Abstract: Embodiments are directed to a complementary metal oxide semiconductor having source and drain contacts formed using trench. An n-type field effect transistor (NFET) includes a p-type semiconductor fin vertically extending from an n-type bottom source or drain region disposed on the substrate. A p-type FET (PFET) includes an n-type semiconductor fin vertically extending from a p-type bottom source or drain region disposed on the substrate. A first gate of the NFET is formed around a channel region of the p-type semiconductor fin and a second gate of the PFET is formed around a channel region of the n-type semiconductor fin. The first gate and the second gate include a dipole layer. The NFET and PFET each has a threshold voltage of about 150 mV to about 250 mV and a difference between the threshold voltages of the NFET and PFET is less than about 50 mV.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: December 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita
  • Patent number: 10510618
    Abstract: A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Han Lee, Chih-Yu Ma, Shih-Chieh Chang
  • Patent number: 10510619
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes following operations. A plurality of fin structures and a plurality of trenches are formed over a semiconductor substrate, wherein the fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer. A dielectric layer is formed over the substrate, wherein the dielectric layer is in the plurality of trenches. The dielectric layer is annealed. A plurality of dopants in the dielectric layer are formed when the fin structures are covered by the mask layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Chang Lin, Shih-Hsiang Chiu, Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
  • Patent number: 10510620
    Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. A first WFM for one FET is deposited over the first active nanostructure, the pillar and the second active nanostructure. The first WFM is removed from a part of the pillar. The removing creates a discontinuity in the first WFM over the first active nano structure from the first WFM over the second active nanostructure but leaves the first WFM on sidewalls of the pillar. When the first WFM surrounding the second active nanostructure is removed, the pillar and the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. Depositing a second WFM surrounding the second active nanostructure and the isolation pillar forms part of the gate for the second FET and couples the FETs together.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Daniel Chanemougame, Steven R. Soss, Steven J. Bentley, Julien Frougier, Ruilong Xie
  • Patent number: 10510621
    Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zoe Chen, Ching-Hwanq Su, Cheng-Lung Hung, Cheng-Yen Tsai, Da-Yuan Lee, Hsin-Yi Lee, Weng Chang, Wei-Chin Lee
  • Patent number: 10510622
    Abstract: A method includes forming a stack of semiconductor material layers. A first spacer is formed adjacent a lower region at a first end of the stack, and a second spacer is formed adjacent an upper region positioned at a second end of the stack. A gate structure and sidewall spacer are formed above the stack. The gate structure and a first subset of the semiconductor layers are removed to define inner cavities and a gate cavity. A gate insulation layer is formed. A first conductive material is formed in the inner cavities. The first conductive material is selectively removed from the inner cavities in the upper region. The first conductive material in the inner cavities in the lower region remains as a first gate electrode. A second conductive material is formed in the inner cavities in the upper region to define a second gate electrode.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ruilong Xie, Puneet Harischandra Suvarna
  • Patent number: 10510623
    Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Wei Fang, Jing-Sen Wang, Yuan-Yao Chang, Wei-Ray Lin, Ting-Hua Hsieh, Pei-Hsuan Lee, Yu-Hsuan Huang
  • Patent number: 10510624
    Abstract: Embodiments of the disclosure provide a metrology system. In one example, a metrology system includes a laser source adapted to transmit a light beam, a lens adapted to receive at least a portion of the light beam from the laser source, a first beam splitter positioned to receive at least the portion of the light beam passing through the lens, a first beam displacing device adapted to cause a portion of the light beam received from the beam splitter to be split into two or more sub-light beams a first recording device having a detection surface, and a first polarizer that is positioned between the first displacing device and the first recording device, wherein the first polarizer is configured to cause the two or more sub-light beams provided from the first displacing device to form an interference pattern on the detection surface of the first recording device.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: December 17, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Mehdi Vaez-Iravani, Todd Egan, Samer Banna, Kyle Tantiwong
  • Patent number: 10510625
    Abstract: An apparatus for supporting a wafer during a plasma processing operation includes a pedestal configured to have bottom surface and a top surface and a column configured to support the pedestal at a central region of the bottom surface of the pedestal. An electrical insulating layer is disposed over the top surface of the pedestal. An electrically conductive layer is disposed over the top surface of the electrical insulating layer. At least three electrically conductive support structures are distributed on the electrically conductive layer. The at least three support structures are configured to interface with a bottom surface of a wafer to physically support the wafer and electrically connect to the wafer. An electrical connection extends from the electrically conductive layer to connect with a positive terminal of a direct current power supply at a location outside of the pedestal.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: December 17, 2019
    Assignee: Lam Research Corporation
    Inventors: Yukinori Sakiyama, Edward Augustyniak, Douglas Keil
  • Patent number: 10510626
    Abstract: In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: December 17, 2019
    Assignee: Infineon Technologies AG
    Inventors: Michaela Braun, Markus Menath
  • Patent number: 10510627
    Abstract: A display device includes a display panel having a display area and a non-display area. A window is disposed on the display panel. A bezel portion is disposed on the window. The bezel portion at least partially overlaps the non-display area. An adhesive layer is disposed between the display panel and the window. An interlayer is disposed between the bezel portion and the adhesive layer. The interlayer has at least one ultrasound transmitting area overlapping the bezel portion.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: December 17, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Eunhye Park, Hyangyul Kim, Hyoungjoon Kim, Joohyung Lee
  • Patent number: 10510628
    Abstract: For multidimensional transducer array interconnection, circuit boards with electronics are stacked to form a surface for connection with the array. The surface of the circuit boards for connecting with the transducer array is metalized and diced. Rather than relying on small exposed traces, larger contact pads are formed by metalizing the surface and then dicing the surface. This forms an array of contact pads for connecting with the z-axis or other connectors for elements of the multidimensional transducer array.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: December 17, 2019
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: BaikWoo Lee, Stephen R. Barnes, David A. Petersen
  • Patent number: 10510629
    Abstract: A package and a method of forming the same are provided. The package includes: a die stack bonded to a carrier, the die stack including a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the carrier, a front side of the first integrated circuit die facing the carrier; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a backside of the first integrated circuit die being in physical contact with a backside of the second integrated circuit die, the backside of the first integrated circuit die being opposite the front side of the first integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack; and an encapsulant extending along sidewalls of the die stack and sidewalls of the heat dissipation structure.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 10510630
    Abstract: Apparatus, and methods of manufacture thereof, in which a molding compound is formed between spaced apart microelectronic devices. The molding compound comprises micro-filler elements. No boundary of any of the micro-filler elements is substantially parallel to a substantially planar surface of the molding compound, or to a substantially planar surface of any of the microelectronic devices.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 10510631
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a first connector. The RDL structure is connected to the die and includes a plurality of RDLs. The TIV is aside the die and penetrates through the RDL structure. The first connector is in electrical contact with the TIV and electrically connected to the die. The TIV is in electrical contact with the RDLs of the RDL structure.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
  • Patent number: 10510632
    Abstract: A semiconductor device has a carrier and a semiconductor die disposed over the carrier. A dummy die is disposed over the carrier as well. A first encapsulant is deposited over the semiconductor die and dummy die. The dummy die and a first portion of the first encapsulant is backgrinded while a second portion of the first encapsulant remains covering the semiconductor die. Backgrinding the dummy die fully removes the dummy die while the second portion of the first encapsulant remains covering the semiconductor die. A second encapsulant is optionally deposited over the dummy die prior to disposing the dummy die over the carrier. A conductive pillar is optionally formed over the dummy die prior to depositing the second encapsulant. The carrier is removed to expose an active surface of the semiconductor die. A build-up interconnect structure is formed over the active surface after removing the carrier.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 17, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Won Kyoung Choi, Pandi Chelvam Marimuthu
  • Patent number: 10510633
    Abstract: Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 10510634
    Abstract: In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Szu-Wei Lu, Chen-Hua Yu
  • Patent number: 10510635
    Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
  • Patent number: 10510636
    Abstract: An electronic module comprises a substrate 11, 21, an other-side electronic component 18, 23 provided on the other side of the substrate 11, 21, a one-side electronic component 13, 28 provided on one side of the substrate 11, 21 and a connecting terminal 115, 125 having an other-side extending part 119a, 129a extending to circumferential outside of the substrate 11, 21 on the other side of the substrate 11, 21, a one-side extending part 119b, 129b extending to circumferential outside of the substrate 11, 21 on one side of the substrate 11, 21, and a connecting part 118, 128 connecting the other-side extending part 119a, 129a with the one-side extending part 119b, 129b at the circumferential outside of the substrate 11, 21.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: December 17, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Kosuke Ikeda, Osamu Matsuzaki
  • Patent number: 10510637
    Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Chieh Yang, Yung-Chow Peng, Chung-Peng Hsieh, Sa-Lly Liu
  • Patent number: 10510638
    Abstract: There is provided an electronic component-embedded board. The electronic component-embedded board includes: a first insulating layer; a metal layer formed on the first insulating layer; a first electronic component disposed on the metal layer; a second insulating layer formed on the first insulating layer and the metal layer such that the first electronic component is buried in the second insulating layer; a second electronic component disposed above the second insulating layer; and a heat radiating member thermally connected to the metal layer exposed from the second insulating layer and thermally connected to the second electronic component.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 17, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Shigeru Mizuno, Tomoya Kubo, Katsuya Fukase