Abstract: Provided a light emitting device including a first metal reflection layer including a phase modulation surface configured to magnetically resonate incident light, a color conversion layer provided on the phase modulation surface of the first metal reflection layer and including a photoluminescent material, a first electrode provided on the color conversion layer opposite to the first metal reflection layer, a white organic light emitting layer provided on the first electrode opposite to the color conversion layer, and a second electrode provided on the white organic light emitting layer opposite to the first electrode.

Abstract: The present disclosure relates to an electroluminescence display having micro-lens layer. The electroluminescence display according to the present disclosure comprises: a lower substrate having a light emitting layer at middle portions; an upper substrate facing the upper substrate; a dam disposed at circumferences of the lower substrate and surrounding the light emitting layer; a filling layer filling space surrounded by the dam and covering the light emitting layer; a micro-lens layer disposed on the inner surface of the upper substrate; a color filter disposed as corresponding to the light emitting layer under the micro-lens layer; and a black matrix disposed at a side of the color filters under the micro-lens layer.

Abstract: A display device includes a display member including a substrate and a plurality of light-emitting elements disposed on the substrate, a sensing member disposed on the display member, and a polarizing member disposed on the sensing member. The sensing member includes a sensing insulating layer and a sensing conductive layer disposed on the sensing insulating layer. The polarizing member includes a polarizing layer and a polarizing adhesive layer disposed between the polarizing layer and the sensing conductive layer. The polarizing adhesive layer is in contact with the sensing conductive layer.

Abstract: A display apparatus includes: a display panel comprising a transmission area, a display area, and a middle area that includes at least one groove and is located between the transmission area and the display area; an input sensing layer stacked on the display panel, wherein a metal layer that overlaps the at least one groove in a plan view is in one of the display panel and the input sensing layer.

Abstract: A display device includes a flexible display module and provides a display surface on which an image is displayed. The flexible display module includes a display panel including a light-emitting device and a sensor unit disposed on the display panel. The sensor unit senses pressure applied to the flexible display module in a folded-in mode in which the flexible display module is folded such that a portion of the display surface faces another portion of the display surface.

Abstract: The present disclosure provides a pixel structure, a display panel and a display apparatus. The pixel structure according to an embodiment of the present disclosure includes a pixel structure including: a plurality of pixel units. Each of the plurality of pixel units includes a plurality of sub-pixels, each of the plurality of sub-pixels is divided into at least two target sub-pixels, and a separation region is provided between two adjacent target sub-pixels.

Abstract: An array substrate, a display panel, and a display device.

Abstract: A display panel includes a pixel arrangement structure. The pixel arrangement structure includes a plurality of first pixel rows and a plurality of second pixel rows arranged alternately. Each of the first pixel rows comprises a plurality of first pixels arranged at intervals, and each of the second pixel rows comprises a plurality of second pixels and a plurality of third pixels arranged alternately and at intervals. A shape of the first pixel comprises a shape formed by an arc. Each of the second pixel and the third pixel comprises a plurality of concave arcs and a plurality of convex arcs, the plurality of concave arcs and the plurality of convex arcs of the second pixel are alternately connected and form a closed figure, and the plurality of concave arcs and the plurality of convex arcs of the third pixel are alternately connected and form a closed figure.

Abstract: Provided are a display panel and a display device. After deposition of a thin-film transistor layer and a display layer in which emitting devices are disposed, a sensing layer including a piezoelectric material is disposed under the thin-film transistor layer to facilitate implementation of a display panel having built-in piezoelectric devices. Further, as thin-film transistors for ultrasonic sensing and thin-film transistors for display driving are disposed in different layers, a display panel capable of ultrasonic sensing in an active area may be provided without affecting a display resolution or implementation of display pixels.

Abstract: Organic light emitting diode display module includes a substrate, a flat layer formed on the substrate, an anode layer formed on the flat layer and within the second through hole, a pixel definition layer formed on the flat layer and the anode layer, a light-emitting layer and a cathode layer formed within third layer through hole and on anode layer. A lead and a power cable are formed on the substrate. The cathode layer is formed on the pixel definition layer, light-emitting layer and lead. The cathode layer includes wire blocks arranged at intervals. The wire blocks includes a bent conductive wire, and both ends of the conductive wire are coupled to the lead and the power cable respectively. The present disclosure also discloses a manufacturing method of the display module and an electronic device.

Abstract: A display apparatus includes: a substrate including a display area in which thin film transistors and display devices electrically connected to the thin film transistors are arranged and a first non-display area outside the display area; a through portion vertically penetrating the substrate; a second non-display area between the through portion and the display area; and an encapsulation layer on the display devices and including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, which are sequentially stacked. The first inorganic encapsulation layer and the second inorganic encapsulation layer extend to the through portion and directly contact each other in the second non-display area, and the first inorganic encapsulation layer directly contacts another inorganic layer thereunder in the second non-display area.

Abstract: The present disclosure provides a transparent OLED substrate, a display panel, and an OLED substrate. The transparent OLED substrate includes: a base substrate; a first electrode layer formed over the base substrate; a pixel defining layer formed over the first electrode layer, the pixel defining layer including a plurality of pixel defining holes penetrating the pixel defining layer to the first electrode layer, and an exposed area of the first electrode layer is equal to an area of the pixel defining hole; a light emitting layer formed over the pixel defining layer and including organic light emitting blocks; a second electrode layer formed over the light emitting layer; wherein each of the pixel defining holes corresponds to a plurality of the organic light emitting blocks.

Abstract: An organic light emitting diode display includes a substrate, a semiconductor layer disposed on the substrate, a first insulating layer which covers the semiconductor layer, a first conductive layer disposed on the first insulating layer, a second insulating layer which covers the first conductive layer, a second conductive layer disposed on the second insulating layer, a third insulating layer which covers the second conductive layer, a third conductive layer disposed on the third insulating layer, a first organic layer which covers the third conductive layer, and a fourth conductive layer disposed on the first organic layer, where the fourth conductive layer includes a lower layer, a middle layer, and an upper layer, and the lower layer is disposed between the first organic layer and the middle layer, and includes a transparent conductive oxidization film.

Abstract: A display panel includes: a substrate including a first area, a second area, and a third area; a stacked structure corresponding to a plurality of display elements in the second area, the stacked structure including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode; and a plurality of grooves in the third area, wherein the stacked structure includes at least one organic material layer that is disconnected by the plurality of grooves, at least one groove of the plurality of grooves is defined in a first multi-layer including a first lower layer and a first upper layer, and at least one of the first lower layer and the first upper layer includes a plurality of sub-layers.

Abstract: A display panel and an OLED display device using the same are disclosed. The display panel includes an active region including data lines, gate lines crossing the data lines, and pixels arranged in a matrix, and a shift register arranged distributively in the active region and configured to supply a gate pulse to the gate lines.

Abstract: A display apparatus includes: a thin-film transistor including a source electrode, a drain electrode, and a gate electrode; a data line in a layer different from the source electrode, the drain electrode, and the gate electrode, wherein the data line is configured to transmit a data signal; and a shield layer between the data line and a component of the thin-film transistor.

Abstract: A display apparatus includes: a thin-film transistor including a source electrode, a drain electrode, and a gate electrode; a data line in a layer different from the source electrode, the drain electrode, and the gate electrode, wherein the data line is configured to transmit a data signal; and a shield layer between the data line and a component of the thin-film transistor.

Abstract: A display device including a lower substrate having a display area and a pad area, a display structure disposed in the display area of the lower substrate, an upper substrate disposed on the display structure in the display area, and facing the lower substrate, pad electrodes disposed in the pad area of the lower substrate and spaced apart from each other in a first direction parallel to a top surface of the lower substrate, a conductive film member including conductive balls disposed on the pad electrodes and having a first area overlapping the pad electrodes and a second area not overlapping the pad electrodes, and a film package disposed on the conductive film member and including bump electrodes overlapping the first area of the conductive film member, in which the shape of the conductive balls disposed in the first area is different from those disposed in the second area.

Abstract: An electronic device according to certain embodiments, comprises a sensor module configured to emit or detect light; and a display disposed above the sensor module, the display comprising a first area corresponding to a location of the sensor module and a second area which is a remaining area other than the first area, wherein the display comprises: a pixel layer comprising pixels; an electrode layer disposed beneath the pixel layer, the electrode layer comprising electrodes electrically connected to the pixels; conductive patterns electrically connected to the pixels and the electrodes; and nonconductive patterns between the pixels, wherein the conductive patterns are spaced apart from each other, at different intervals in the first area, and wherein the nonconductive patterns are spaced apart from each other, at different intervals in the first area.

Abstract: A display apparatus includes: a substrate comprising a display area and a non-display area; and a pad on the non-display area, wherein the pad comprises: a first conductive layer comprising, in a plan view, a plurality of bent portions and a plurality of connection portions connecting the plurality of bent portions with each other, the connection portions alternately extending in a first direction and a second direction opposite to the first direction; a second conductive layer on the first conductive layer and overlapping at least part of the first conductive layer; and a third conductive layer on the second conductive layer and overlapping the second conductive layer.

Abstract: A display panel including a substrate having a first area, a display area, and an intermediate area between the first area and the display area; a plurality of data lines extending in a first direction in the display area; and a data distributor including switches electrically connected to the plurality of data lines. The plurality of data lines include a first data line and a second data line, and each of the first data line and the second data line bypasses an edge of the first area in the intermediate area, and a bypass portion of the first data line and a bypass portion of the second data line overlap each other in the intermediate area.

Abstract: A display device includes a substrate having a display area and a non-display area, a plurality of pixels in the display area, scan lines for supplying a scan signal to the pixels, the scan lines extending in a first direction, data lines for supplying a data signal to the pixels, the data lines extending in a second direction crossing the first direction, and a first dummy part in the non-display area, adjacent to an outermost pixel, connected to an outermost data line of the display area, forming a parasitic capacitor with the outermost pixel, and including a first dummy data line and a first dummy power pattern extending in parallel to the data lines.

Abstract: A display apparatus includes a substrate, a driving thin-film transistor arranged on the substrate and including a driving semiconductor layer and a driving gate electrode, a first scanning line arranged on the first substrate and which extends in a first direction, a data line which extends in a second direction that intersects with the first direction, a node connection line arranged in the same layer as the first scanning line, and a shielding conductive layer arranged between the data line and the node connection line and disposed in the same layer as the driving gate electrode, where an end of the node connection line is connected to the driving gate electrode through a first node contact hole.

Abstract: This disclosure relates to a pixel defining structure, a display panel, a method of manufacturing the same, and a display device. The pixel defining structure includes: a first pixel defining layer with a first opening, located on a substrate, wherein the first pixel defining layer includes a first portion formed by a first hydrophilic-hydrophobic material and a second portion formed by a second hydrophilic-hydrophobic material, projections of the first portion and the second portion on a surface of the substrate are substantially not overlapped, a side surface of the first pixel defining layer facing the first opening includes a first side surface formed by the first hydrophilic-hydrophobic material and a second side surface formed by the second hydrophilic-hydrophobic material, and the first hydrophilic-hydrophobic material has a different hydrophilicity and hydrophobicity from that of the second hydrophilic-hydrophobic material.

Abstract: In one example an electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate, the first resistive layer having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate, the second resistive layer having a second sheet resistance different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion, the outer portion including first and second regions, and an inner portion inside the outer portion, a dielectric film on the lower electrode to extend along the first region of the outer portion, and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion.

Abstract: A capacitor structure includes an insulative layer, a first electrode over the insulative layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The first electrode includes a first portion extending along a lateral direction of the insulative layer and a second portion connected to the first portion and extending along a depth direction of the insulative layer. The dielectric layer is substantially conformal with respect to a profile of the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.

Abstract: Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.

Abstract: An FET comprises a source, a drain, a channel, and a gate encompassing the channel. The channel has a first region that is thinner than in a second region. The Threshold Voltage, Vth, is larger in the first region than in the second region causing an asymmetric Vth across the length of the channel. Modeling has shown that the Vth increases along the channel from about 50 milliVolts (mV) for N-FETs (about 55 mV for a P-FETs) to about 125 mV for N-FETs (about 180 mV for P-FETs) as the channel width decreases from 4 nanometers (nm) to 2 nm.

Abstract: A silicon carbide semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, first base regions of the second conductivity type, second base regions of the second conductivity type, gate insulating films, gate electrodes, a first electrode, a second electrode, and trenches. Between the trenches, the first base regions are in contact with the second semiconductor layer. The second base regions are provided at positions facing the trenches in a depth direction, respectively, and have a first surface facing the second electrode and a second surface facing the first electrode, where a curvature of the first surface is smaller than a curvature of the second surface.

Abstract: The present invention provides a conducting material comprising a carbon-based material selected from a diamond or an insulating diamond-like carbon, having a hydrogen-terminated surface and a layer of tungsten trioxide, rhenium trioxide, or chromium oxide coating said hydrogen-terminated surface. Such conducting materials are useful in the fabrication of electronic components, electrodes, sensors, diodes, field effect transistors, and field emission electron sources.

Abstract: A chemically-doped graphene transistor comprising a plurality of graphene layers and having a first doped region separated from a second doped region by a third doped region, wherein the first and second doped regions are of an opposite doping type to the third doped region, and wherein each of the first, second and third doped regions each comprise a separate electrical contact.

Abstract: A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×1022 cm?3 or more, a SiO2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO2 layer and that has a carbon density of 1.0×1019 cm?3 or less.

Abstract: A semiconductor apparatus capable of reducing the leakage current in the reverse direction, and keeping characteristics thereof, even when using n type semiconductor (gallium oxide, for example) or the like having a low-loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC is provided. A semiconductor apparatus includes a crystalline oxide semiconductor having a corundum structure as a main component, and an electric field shield layer and a gate electrode that are respectively laminated directly or through other layers on the n type semiconductor layer, wherein the electric field shield layer includes a p type oxide semiconductor, and is embedded in the n type semiconductor layer deeper than the gate electrode.

Abstract: In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type formed on the semiconductor substrate and having a first conductivity type impurity concentration higher than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type formed above the first semiconductor layer, a first device region formed in the second semiconductor layer and configured to operate based on a first reference voltage, a second device region formed in the second semiconductor layer and configured to operate based on a second reference voltage, the second device region being spaced apart from the first device region, and a region isolation structure interposed between the first and second device regions and formed in a region extending from a front surface of the second semiconductor layer to the first semiconductor layer so as to electrically isolate the first and second device regions from each other.

Abstract: In order to improve the reliability of a semiconductor device, in a memory cell of a split-gate type MONOS memory formed on a fin, a drain region is formed in an epitaxial layer on the fin, and a source region is formed in the fin, and a silicide layer is formed on an upper surface of the fin in which the source region is formed.

Abstract: A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.

Abstract: A device includes a nanowire, a gate dielectric layer, a gate electrode, a gate pickup metal layer, and a gate contact. The nanowire extends in a direction perpendicular to a top surface of a substrate. The gate dielectric layer laterally surrounds the nanowire. The gate electrode laterally surrounds the gate dielectric layer. The gate pickup metal layer is in contact with a bottom surface of the gate electrode and extends laterally past opposite sidewalls of the gate electrode. The gate contact is in contact with the gate pickup metal layer.

Abstract: A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.

Abstract: A semiconductor device includes a substrate including a recess, a first gate insulation layer on a lower sidewall and a bottom of the recess, the first gate insulation layer including an insulation material having hysteresis characteristics, a first gate electrode on the first gate insulation layer inside the recess, a second gate electrode contacting the first gate electrode in the recess, the second gate electrode including a material different from a material of the first gate electrode, and impurity regions on the substrate and adjacent to sidewalls of the recess, bottoms of the impurity regions being higher than a bottom of the second gate electrode relative to a bottom of the substrate.

Abstract: A memory cell comprises, in the following order, channel material, a charge-passage structure, programmable material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. The first and third materials comprise SiO2. The second material has a thickness of 0.4 nanometer to 5.0 nanometers and comprises SiOx, where “x” is less than 2.0 and greater than 0. Other embodiments are disclosed.

Abstract: Described is a transistor which includes: a source region; a drain region; and a gate region between the source and drain regions, wherein the gate region comprises: high-K dielectric material between spacers such that the high-K dielectric material is recessed; and metal electrode on the recessed high-K dielectric material. The gate recessed gate dielectric allows for using thick gate dielectric even with much advanced process technology nodes (e.g., 7 nm and below).

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate, forming a polymer block on a corner between the gate structure and the substrate, performing an oxidation process to form a first seal layer on sidewalls of the gate structure, and forming a source/drain region adjacent to two sides of the gate structure. Preferably, the polymer block includes fluorine, bromide, or silicon.

Abstract: A semiconductor structure and a formation method thereof are provided. In one form, the method includes: providing a base; patterning the base to form a substrate and discrete fins and pseudo fins which protrude from the substrate, wherein the fins are located in a device region, and the pseudo fins are located in isolation regions; removing the pseudo fins in the isolation regions; forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins.

Abstract: A method of fabricating a semiconductor device includes forming a semiconductor fin structure over a substrate, where the semiconductor fin structure includes a plurality of semiconductor fins and defines trenches among the semiconductor fins, and forming a dielectric fin structure having a plurality of dielectric fins. Forming the dielectric fin structure includes filling the trenches with a first dielectric material layer and a second dielectric material layer over the first dielectric material layer, the second dielectric material layer having a composition different from that of the first dielectric material layer, removing a portion of the second dielectric material layer to form a recess, and filling the recess with a third dielectric material layer, the third dielectric material layer having the same composition as the first dielectric material layer.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method for manufacturing a fin structure for a vertical field effect transistor (VFET) includes: forming on a substrate mandrels having at least one first gap therebetween; forming first spacers on side surfaces of the mandrels such that at least one second gap, smaller than the first gap, is formed between the first spacers; forming a second spacer on side surfaces of the first spacers; removing the mandrels and the first spacers to leave the second spacer on the side surfaces of the first spacers; removing the second spacer, on the side surfaces of the first spacers, at a predetermined portion so that the remaining second spacer has a same two-dimensional (2D) shape as the fin structure; and removing a portion of the substrate, except below the remaining second spacer, and the remaining second spacer so that the substrate below the remaining second spacer forms the fin structure.