Abstract: The present invention discloses a flash. A channel region comprises a first shallow trench formed in the surface area of a semiconductor substrate. A tunneling dielectric layer and a polysilicon floating gate are formed in the first shallow trench and extended to the outside of the first shallow trench. A control dielectric layer and a polysilicon control gate are sequentially formed on the two side surfaces in the width direction and the top surface of the polysilicon floating gate. A source region and a drain region are formed in a self-aligned manner in active regions on the two sides in the length direction of the polysilicon floating gate. The present invention further discloses a method for manufacturing a flash. The present invention can break through the limitation of the length of the channel on the size of the memory cell, thus reducing the area of the memory cell.

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack.

Abstract: Fins lined up in a Y direction, a control gate electrode and a memory gate electrode each extending in the Y direction so as to straddle the fins, a plurality of first plugs electrically connected with a drain region formed in each of the fins, and a plurality of second plugs electrically connected with a source region formed in each of the fins are formed. Here, a N-th plug of the plurality of first plugs lined up in the Y direction is coupled with each of (2N?1)-th and 2N-th fins in the Y direction. Also, a N-th plug of the plurality of second plugs lined up in the Y direction is coupled with each of 2N-th and (2N+1)-th fins in the Y direction.

Abstract: A first semiconductor die includes a first substrate, first semiconductor devices, first dielectric material layers having a first silicon oxide surface as an uppermost surface and forming first metal interconnect structures. A second semiconductor die includes a second substrate, second semiconductor devices, and second dielectric material layers forming second metal interconnect structures. A handle substrate is attached to a topmost surface of the second semiconductor die. The second substrate is thinned, and a second silicon oxide surface is provided as a bottommost surface of the second semiconductor die. The second semiconductor die is bonded to the first semiconductor die by inducing oxide-to-oxide bonding between the second silicon oxide surface and the first silicon oxide surface. The handle substrate is detached, and inter-die connection via structures are formed through the second substrate and the bonding interface to contact the first metal interconnect structures.

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same are provided. A memory device may include a semiconductor layer including first and second regions, first vertical structures on the first region and extending in a first direction perpendicular to a top surface of the semiconductor layer, and second vertical structures on the second region and extending in the first direction. The first vertical structure may include a vertical semiconductor pattern extending in the first direction and in contact with the semiconductor layer, and a first data storage pattern surrounding the vertical semiconductor pattern. The second vertical structure may include an insulation structure extending in the first direction and in contact with the semiconductor layer, and a second data storage pattern surrounding the insulation structure.

Abstract: An alternating layer stack of insulating layers and sacrificial material layers is formed over a semiconductor substrate, and memory stack structures are formed through the vertically-alternating layer stack. A pair of unconnected barrier trenches or a moat trench is formed through the alternating stack concurrently with formation of backside trenches. Backside recesses are formed by isotropically etching the sacrificial material layers selective to the insulating layers while a dielectric liner covers the barrier trenches or the moat trench. A vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches or inside the moat trench. Electrically conductive layers are formed in the backside recesses. A first conductive via structure is formed through the vertically alternating sequence concurrently with formation of a second conductive via structure through a dielectric material portion adjacent to the alternating stack.

Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.

Abstract: A three-dimensional flash memory device is described that may include a substrate, a plurality of cell gate patterns and a plurality of mold insulating layers alternately stacked on the substrate, and a vertical channel structure in contact with side surfaces of the plurality of cell gate patterns and side surfaces of the plurality of mold insulating layers. Each of the plurality of cell gate patterns may include a cell gate electrode and a blocking barrier pattern adjacently disposed on one side surface of the cell gate electrode. An inner side surface of the blocking barrier pattern may include an upper inner side surface, a middle inner side surface, and a lower inner side surface. The middle inner side surface of the blocking barrier pattern may face the one side surface of the cell gate electrode.

Abstract: A three-dimensional flash memory device including a lower and upper word line stack; a cell channel structure; and a dummy channel structure, wherein the cell channel structure includes a lower cell channel structure; an upper cell channel structure; and a cell channel enlarged portion between the lower and upper cell channel structures and having a width greater than that of the lower cell channel structure, wherein the dummy channel structure includes a lower dummy channel structure; an upper dummy channel structure; and a dummy channel enlarged portion between the lower and upper dummy channel structures, the dummy channel enlarged portion having a width greater than that of the lower dummy channel structure, wherein a difference between the width of the dummy channel enlarged portion and the lower dummy channel structure is greater than a difference between the width of the cell channel enlarged portion and the lower cell channel structure.

Abstract: A vertical memory device is provided including a first structure on a substrate. The first structure includes gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate to form a plurality of layers. A second structure is connected to the first structure. The second structure includes pad patterns electrically connected to the gate patterns of a respective one of the layers. A channel structure passes through the gate patterns. A first contact plug passes through the second structure and electrically connects with a pad pattern of one of the layers. The first contact plug is electrically insulated from gate patterns of other layers. At least one bent portion is included at each of a sidewall of the channel structure and a sidewall of the first contact plug.

Abstract: A semiconductor device includes a channel structure arranged on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers arranged on the substrate and surrounding the channel structure, the plurality of insulating layers spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; and a plurality of second gate electrodes surrounding the channel structure. Between adjacent insulating layers from among the plurality of insulating layers are arranged a first gate electrode from among the plurality of first gate electrodes spaced apart along the first direction from a second gate electrode from among the plurality of second gate electrodes.

Abstract: A vertical memory device includes gate electrodes disposed on a substrate and spaced apart from each other in a vertical direction. A channel extends in the vertical direction and is positioned adjacent to the gate electrodes. A tunnel insulation pattern is disposed on a portion of an outer sidewall of the channel that is adjacent to each of the gate electrodes. Charge trapping pattern structures are disposed between the tunnel insulation pattern and each of the gate electrodes. Each of the charge trapping pattern structures includes upper and lower charge trapping patterns spaced apart from each other in the vertical direction. Blocking pattern structures are between the charge trapping patterns and each of the gate electrodes. A first portion of the channel that is adjacent to the tunnel insulation pattern has a thickness in a horizontal direction that is smaller than a thickness of other portions of the channel.

Abstract: According to one embodiment, storage device comprises first wiring layers stacked along a first direction and a memory pillar extending through the first wiring layers. A second wiring layer is above an upper end of the memory pillar. A second semiconductor layer has a first portion between the first semiconductor layer and the second wiring layer and a second portion extending away from the first semiconductor layer. A first insulating layer is between the first portion and the second wiring layer in first direction, and also between the second portion and the second wiring layer in a second direction intersecting the first direction.

Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.

Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous.

Abstract: A memory device and a manufacturing method are provided. The method includes: forming a first conductive pattern on a substrate; forming an active structure over the first conductive pattern, wherein the active structure comprises a gate pattern, a channel pillar and a charge storage layer, the channel pillar penetrates the gate pattern and electrically connects with the first conductive pattern, and the charge storage layer is disposed between the gate pattern and the channel pillar; forming a second conductive pattern over the active structure, wherein the second conductive pattern is electrically connected with the channel pillar; and performing formation of the active structure one more time, such that the channel pillars of the active structures are vertically spaced apart from each other, and electrically connected to the second conductive pattern extending in between the channel pillars.

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The method comprises: forming a recess region in a substrate including multiple protruding islands; forming a gate dielectric layer to cover top surfaces and sidewalls of the multiple protruding islands and a top surface of the recess region of the substrate; forming an underlying sacrificial layer on the gate dielectric layer to surround the sidewalls of the multiple protruding islands; forming an alternating dielectric stack including multiple alternatively stacked insulating layers and sacrificial layers on the underlying sacrificial layer and the multiple protruding islands; forming multiple channel holes penetrating the alternating dielectric stack, each channel hole is located corresponding to one of the multiple protruding islands; and forming a memory layer in each channel hole, wherein a channel layer of the memory layer is electrically connected with a corresponding protruding island.

Abstract: A semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a semiconductor material layer, a memory opening and a support opening extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a semiconductor material portion in contact with the semiconductor material layer, and a support pillar structure located in the support opening. The support pillar structure lacks a semiconductor material portion which is in contact with the semiconductor material layer.

Abstract: The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.

Abstract: Embodiments include diode devices and transistor devices. A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts.

Abstract: An array substrate and a method of manufacturing the same are provided. By setting a gate driver on array (GOA) signal area above a GOA driving circuit area, space occupied by a GOA circuit area is reduced, thereby reducing a frame of a display device, and further increasing a screen ratio of the display device.

Abstract: A flexible display device of which esthetic appearance is improved by reducing a bezel is disclosed. The flexible display device comprises a substrate including a display area and a non-display area including a bending area; a link line in the non-display area on the substrate; and a bending connection line in the bending area pf the substrate and connected with the link line, and the bending connection line located between a first buffer layer and a second buffer layer of the flexible display device.

Abstract: The purpose of the present invention is to improve reliability of the TFT of the oxide semiconductor. The feature of the invention is: A display device comprising: a substrate including a display area where plural pixels are formed, the pixel includes a first TFT of a first oxide semiconductor, a first gate insulating film is formed under the first oxide semiconductor, a first gate electrode is formed under the first gate insulating film, an interlayer insulating film is formed on the first oxide semiconductor; a drain wiring, which connects with the first oxide semiconductor, and a source wiring, which connects with the first oxide semiconductor, are formed on the interlayer insulating film; the drain wiring or the source wiring is a laminated structure of a second oxide semiconductor and a first metal, the second oxide semiconductor is under the first metal.

Abstract: A thin film transistor and a method for manufacturing the same, and a display device including the same are disclosed, in which a P type semiconductor characteristic is realized using an active layer that includes a Sn based oxide. The thin film transistor comprises an active layer that includes an Sn(II)O based oxide; a metal oxide layer being in contact with one surface of the active layer; a gate electrode overlapped with the active layer; a gate insulating film provided between the gate electrode and the active layer; a source electrode being in contact with a first side of the active layer; and a drain electrode being in contact with a second side of the active layer.

Abstract: The present invention provides a display panel and a manufacturing method thereof. The display panel comprises an array substrate provided with a first inclined plane at an edge of one side of the array substrate; a color filter substrate disposed on one side surface of the array substrate; the color filter substrate provided with a second inclined plane at an edge of one side of the color filter substrate, and the second inclined plane on a same plane with the first inclined plane; and a chip on film bonded to the first inclined plane and the second inclined plane. A manufacturing method of the display panel comprises an array substrate providing step, a color filter substrate disposing step, a cutting step and a bonding step. The technical effect of the present invention is reducing the thickness of the bottom frame of the display panel and increasing the screen ratio.

Abstract: An optoelectronic device is disclosed, comprising: a photodiode array including a plurality of first photodiodes, each first photodiode including a respective n+ region and a respective n-well region; a guide array disposed over the photodiode array, the guide array including a plurality of guide members separated from one another by a layer of light-blocking material, the guide members being aligned with the n+ regions of the first photodiodes, such that each guide member is disposed over a different respective n+ region, and the layer of light-blocking material being aligned with the n-well regions of the first photodiodes; and a filter array disposed over the guide array, the filter array including a plurality of bandpass filters, each bandpass filter being aligned with a different one of the plurality of guide members, each bandpass filter having a different transmission band.

Abstract: An image sensor includes a substrate including a plurality of pixel regions and having a trench between the pixel regions, a photoelectric conversion part in the substrate of each of the pixel regions, and a device isolation pattern in the trench. The device isolation pattern defines an air gap. The device isolation pattern has an intermediate portion and an upper portion narrower than the intermediate portion.

Abstract: Disclosed is a solid-state imaging device including a plurality of pixels and a plurality of on-chip lenses. The plurality of pixels are arranged in a matrix pattern. Each of the pixels has a photoelectric conversion portion configured to photoelectrically convert light incident from a rear surface side of a semiconductor substrate. The plurality of on-chip lenses are arranged for every other pixel. The on-chip lenses are larger in size than the pixels. Each of color filters at the pixels where the on-chip lenses are present has a cross-sectional shape whose upper side close to the on-chip lens is the same in width as the on-chip lens and whose lower side close to the photoelectric conversion portion is shorter than the upper side.

Abstract: A highly sensitive imaging device that can perform imaging even under a low illuminance condition is provided. One electrode of a photoelectric conversion element is electrically connected to one of a source electrode and a drain electrode of a first transistor and one of a source electrode and a drain electrode of a third transistor. The other of the source electrode and the drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor. The other electrode of the photoelectric conversion element is electrically connected to a first wiring. A gate electrode of the first transistor is electrically connected to a second wiring. When a potential supplied to the first wiring is HVDD, the highest value of a potential supplied to the second wiring is lower than HVDD.

Abstract: Disclosed is a photosensitive module (21), adapted to a camera module, comprising a photosensitive element (211), a light transmitting element (212) and an isolation adhesive layer (213), wherein the photosensitive element has a photosensitive region and a non-photosensitive region, the light transmitting element is arranged in a photosensitive path of the photosensitive element, and wherein the isolation adhesive layer is arranged in the non-photosensitive region and supports the light transmitting element, and the isolation adhesive layer is formed by means of photolithography.

Abstract: A texture recognition assembly, a method of manufacturing the same, and a display apparatus are disclosed. The texture recognition assembly includes a photosensitive sensing layer, a texture contact layer, and a filter film layer disposed at a side of the photosensitive sensing layer proximate to the texture contact layer. The filter film layer is configured to filter visible light with a wavelength greater than or equal to ?. A value of ? is greater than or equal to 600 nm.

Abstract: A semiconductor apparatus according to the present invention includes: a semiconductor component including a cell array and a plurality of wirings; and a semiconductor component including a plurality of pads connected to the semiconductor component including the cell array. A first row pad connected to a row wiring connected to a first cell and a second cell, a second row pad connected to a row wiring connected to a third cell and a fourth cell, and a column pad connected to a column wiring connected to the first cell and the third cell are arranged such that a straight line connecting the first row pad and the column pad crosses a straight line connecting the second row pad and the column pad.

Abstract: There is provided a solid-state imaging device including a first substrate having a pixel circuit including a pixel array unit formed thereon, and a second substrate having a plurality of signal processing circuits formed thereon so as to be arranged through a scribe region. The first substrate and the second substrate are stacked.

Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.

Abstract: A depth sensor includes a first pixel including a plurality of first photo transistors each receiving a first photo gate signal, a second pixel including a plurality of second photo transistors each receiving a second photo gate signal, a third pixel including a plurality of third photo transistors each receiving a third photo gate signal, a fourth pixel including a plurality of fourth photo transistors each receiving a fourth photo gate signal, and a photoelectric conversion element shared by first to fourth photo transistors of the plurality of first to fourth photo transistors.

Abstract: Various embodiments of the present application are directed towards an image sensor including a wavelength tunable narrow band filter, as well as methods for forming the image sensor. In some embodiments, the image sensor includes a substrate, a first photodetector, a second photodetector, and a filter. The first and second photodetectors neighbor in the substrate. The filter overlies the first and second photodetectors and includes a first distributed Bragg reflector (DBR), a second DBR, and a first interlayer between the first and second DBRs. A thickness of the first interlayer has a first thickness value overlying the first photodetector and a second thickness value overlying the second photodetector. In some embodiments, the filter is limited to a single interlayer. In other embodiments the filter further includes a second interlayer defining columnar structures embedded in the first interlayer and having a different refractive index than the first interlayer.

Abstract: A method of fabricating a sensing apparatus is disclosed. The method includes providing a substrate that includes a plurality of image sensors, forming an optical filtering film on the substrate, and forming a collimator on the optical filtering film. The method further includes forming a blocking layer on the collimator and forming an illumination layer on the blocking layer. The illumination layer is configured to illuminate an object placed above the illumination layer. The image sensors are configured to detect a portion of light reflected from the object.

Abstract: An image sensor and a method of manufacturing thereof are provided. The image sensor includes a substrate, a grid structure, and color filters. The substrate includes a pixel separation structure defining pixel regions, and a sub-pixel regions for each pixel region. The grid structure is disposed on the substrate and includes first fence segments provided between the sub-pixel regions, and second fence segments provided between neighboring pixel regions. The grid structure defines openings corresponding respectively to the sub-pixel regions. The color filters are disposed in the openings defined by the grid structure. Each of the color filters has a flat top surface and the flat top surface of each color filter is parallel to a bottom surface thereof.

Abstract: A micro multi-color LED device includes two or more LED structures for emitting a range of colors. The two or more LED structures are vertically stacked to combine light from the two more LED structures. In some embodiments, each LED structure is connected to a pixel driver and a shared P-electrode. The LED structures are bonded together through bonding layers. In some embodiments, reflection layers are implemented in the device to improve the LED emission efficiency. A display panel comprising an array of the micro tri-color LED devices has a high resolution and a high illumination brightness.

Abstract: A component may include a semiconductor body and a converter layer. The converter layer may have phosphor particles and an electrically conductive matrix material where the phosphor particles are embedded in the matrix material. The converter layer may be arranged on the semiconductor body and may have a plurality of sublayers that are spatially set apart from one another and can be electrically contacted individually. The semiconductor body may have an active zone for producing electromagnetic radiation where the sublayers of the converter layer are designed for local electrical contacting of the active zone.

Abstract: One embodiment of the present invention is a display device including a first insulating layer, a second insulating layer, a first transistor, a second transistor, a first light-emitting diode, a second light-emitting diode, and a color conversion layer. The first insulating layer is over the first transistor and the second transistor. The first light-emitting diode and the second light-emitting diode are over the first insulating layer. The color conversion layer is over the second light-emitting diode. The color conversion layer is configured to convert light emitted from the second light-emitting diode into a light having a longer wavelength. The first transistor and the second transistor each include a metal oxide layer and a gate electrode. The metal oxide layer includes a channel formation region. A top surface of the gate electrode is level or substantially level with a top surface of the second insulating layer.

Abstract: A display device includes a substrate; a first electrode and a second electrode arranged to be spaced apart from each other on the substrate; a first insulating layer on the substrate; a light emitting element on the first insulating layer, located between the first electrode and the second electrode, and including a first end portion and a second end portion; a third electrode on the substrate and electrically connected to the first electrode and the first end portion; a fourth electrode on the substrate and electrically connected to the second electrode and the second end portion; a second insulating layer on the substrate and covering the light emitting element, the third electrode, and the fourth electrode; and a light diffusion layer on the second insulating layer and including a light diffusion particle.

Abstract: A display device is provided. The display device includes a first electrode including a first electrode surface extending in a first direction and a second electrode surface connected to one end of the first electrode surface and extending in a second direction that is different from the first direction, a second electrode including a third electrode surface extending in the first direction and spaced apart from the first electrode surface and facing the first electrode surface, and a fourth electrode surface extending in the second direction and spaced apart from the second electrode surface and facing the second electrode surface, and at least one light emitting element between the first electrode and the second electrode and including a first light emitting element between the first electrode surface and the third electrode surface and a second light emitting element between the second electrode surface and the fourth electrode surface.

Abstract: An electrically-powered device, structure and/or component is provided that includes an attached electrical power source in a form of a unique, environmentally-friendly energy harvesting element or component. The energy harvesting component provides a mechanism for generating autonomous renewable energy, or a renewable energy supplement, in the integrated circuit system, structure and/or component. The energy harvesting element includes a first conductor layer, a low work function layer, a dielectric layer, and a second conductor layer that are particularly configured in a manner to promote electron migration from the low work function layer, through the dielectric layer, to the facing surface of the second conductor layer in a manner that develops an electric potential between the first conductor layer and the second conductor layer. The energy harvesting component includes a plurality of energy harvesting elements electrically connected to one another to increase an electrical power output.

Abstract: A method is presented for preventing excessive cap dielectric loss in memory areas and logic areas of a device. The method includes forming a first conductive line with top via and a conductive pad over a dielectric layer, wherein the conductive pad includes a microstud, depositing a dielectric cap in direct contact with the first conductive line and the conductive pad, and constructing a top electrode, a magnetic tunnel junction (MTJ) stack, and a bottom electrode in vertical alignment with the microstud of the conductive pad.

Abstract: A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.

Abstract: A method for fabricating stacked resistive memory with individual switch control is provided. The method includes forming a first random access memory (ReRAM) device. The method further includes forming a second ReRAM device in a stacked nanosheet configuration on the first ReRAM device. The method also includes forming separate gate contacts for the first ReRAM device and the second ReRAM device.

Abstract: According to one embodiment, a memory device includes a memory cell and a first select transistor. The memory cell includes: a variable resistance memory region; a first semiconductor layer being in contact with the variable resistance memory region; a first insulating layer being in contact with the first semiconductor layer; and a first voltage application electrode being in contact with the first insulating layer. The first select transistor includes: a second semiconductor layer; a second insulating layer being in contact with the second semiconductor layer; and a second voltage application electrode extending in the second direction and being in contact with the second insulating layer.

Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.