Abstract: A method for manufacturing a vertical field effect transistor (VFET) device may include: providing an intermediate VFET structure including a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region; forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other; filling the shallow trench and a space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface to be at or above a level of the top surface of the doped layer is formed in the shallow trench; forming a plurality of gate structures on the fin structures, respectively; and forming a top S/

Abstract: A semiconductor device includes a substrate, a circuit element disposed on or above the upper surface of the substrate, an electrode disposed on or above the upper surface of the substrate and connected to the circuit element, and a conductor pillar bump for external connection which is disposed on the substrate and electrically connected to the electrode or the circuit element. The substrate includes a first base and a second base disposed on the first base. The circuit element and the electrode are disposed on the second base. The first base has lower thermal resistance than the second base.

Abstract: A semiconductor device includes a collector layer of a first conductive type, a drift layer of a second conductive type, an accumulation region of the second conductive type, a base region of the first conductive type, emitter regions of the second conductive type, a first gate electrode in contact with the emitter regions via first gate insulating film, a second gate electrode facing the first gate electrode via the base region, and being in contact with the emitter regions via second gate insulating film, a first resistive section electrically connected to the first gate electrode, a second resistive section having a larger resistance than does the first resistive section, and electrically connected to the second gate electrode, and a gate electrode pad electrically connected to the first and second resistive sections.

Abstract: A semiconductor structure includes a substrate having an active region and an isolation region, an insulating layer disposed on the substrate, a seed layer disposed on the insulating layer, a compound semiconductor layer disposed on the seed layer, a gate structure in the active region disposed on the compound semiconductor layer, an isolation structure in the isolation region disposed on the substrate, a pair of through-substrate vias in the isolation region disposed on the opposite sides of the gate structure, and a source structure and a drain structure disposed on the substrate and on the opposite sides of the gate structure. The pair of through-substrate vias pass through the isolation structure and contact the seed layer. The source structure and the drain structure electrically connect the seed layer by the pair of through-substrate vias.

Abstract: A gate-sinking pseudomorphic high electron mobility transistor comprises a compound semiconductor substrate overlaid with an epitaxial structure which includes sequentially a buffer layer, a channel layer, a Schottky layer, and a first cap layer. The Schottky layer comprises from bottom to top at least two stacked regions of semiconductor material. Each of the two adjacent stacked regions differs in material from the other and provides a stacked region contact interface therebetween. In any two adjacent stacked regions of the Schottky layer, one stacked region composed of AlGaAs-based semiconductor material alternates with the other stacked region composed of InGaP-based semiconductor material. A gate-sinking region is beneath the first gate metal layer of the gate electrode, and the bottom boundary of the gate-sinking region is located at the one of the at least one stacked region contact interface of the Schottky layer.

Abstract: A gate stack structure is disclosed for inhibiting charge leakage in III-V transistor devices. The techniques are particularly well-suited for use in enhancement-mode MOSHEMTs but can also be used in other transistor designs susceptible to charge spillover and unintended channel formation in the gate stack. In an example embodiment, the techniques are realized in a transistor having a III-N gate stack over a gallium nitride (GaN) channel layer. The gate stack is configured with a relatively thick barrier structure and wide bandgap III-N materials to prevent or otherwise reduce channel charge spillover resulting from tunneling or thermionic processes at high gate voltages. The barrier structure is configured to manage lattice mismatch conditions, so as to provide a robust high-performance transistor design. In some cases, the gate stack is used in conjunction with an access region polarization layer to induce two-dimensional electron gas (2DEG) in the channel layer.

Abstract: Apparatus and method are provided. The apparatus includes at least one field effect transistor (FET), wherein the at least one FET comprises at least one gate overlaying at least one non-linear fin, wherein the non-linear fin is formed via modulating a mandrel by producing cut-outs in the mandrel via optical proximity correction (OPC). The method includes receiving a semiconductor wafer, forming source and drain areas for each of at least one FET on the semiconductor wafer; and forming at least one gate overlaying at least one non-linear fin in each of the at least one FET, wherein the non-linear fin is formed via modulating a mandrel by producing cut-outs in the mandrel via OPC.

Abstract: A semiconductor device includes a semiconductor substrate, a gate stack, an air spacer, a first spacer, a second spacer, a sacrificial layer, and a contact plug. The gate stack is on the semiconductor substrate. The air spacer is around the gate stack. The first spacer is around the air spacer. The second spacer is on the air spacer and the first spacer. The sacrificial layer is on the gate stack, and an etching selectivity between the second spacer and the sacrificial layer is in a range from about 10 to about 30. The contact plug lands on the second spacer and the gate stack.

Abstract: A method for forming a multi-gate semiconductor device includes forming a fin structure including alternating stacked first semiconductor layers and second semiconductor layers over a substrate, forming a dummy gate structure across the fin structure, forming a first spacer alongside the dummy gate structure, removing a first portion of the first spacer to expose the dummy gate structure, forming a second spacer between a second portion of first spacer and the dummy gate structure after removing the first portion of the first spacer, removing the dummy gate structure to expose a sidewall of the second spacer, removing the first semiconductor layers of the fin structure to form a plurality of nanostructures from the second semiconductor layers of the fin structure, and forming a gate conductive structure to wrap around the plurality of nanostructures. The gate conductive structure is in contact with the sidewall of the second spacer.

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface.

Abstract: A method of forming a stacked field effect transistor (FET) circuit is provided. The method includes providing a first wafer and a second wafer, forming a first dielectric layer on a surface of the first wafer, forming a second dielectric layer on a surface of the second wafer, and bonding the first wafer to the second wafer at the first dielectric layer and the second dielectric layer.

Abstract: A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of semiconductor layers on a semiconductor substrate, and forming a plurality of gate structures spaced apart from each other on the semiconductor layers. The semiconductor layers are patterned into a plurality of patterned stacks spaced apart from each other, wherein the plurality of patterned stacks are under the plurality of gate structures. The method also includes forming a plurality of sacrificial spacers on lateral sides of the plurality of gate structures, and growing a plurality of source/drain regions. The source/drain regions are adjacent the patterned stacks and include a plurality of pillar portions formed on lateral sides of the sacrificial spacers. The sacrificial spacers and the plurality of pillar portions are removed.

Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

Abstract: A semiconductor device with high on-state current is provided. The semiconductor device includes a transistor. The transistor includes a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide; a first conductor and a second conductor over the second oxide; a second insulator; a third conductor; a fourth insulator over the first conductor and the second conductor; and a third insulator over the fourth insulator. An opening reaching the second oxide is provided in the third insulator and the fourth insulator. The third oxide is positioned to cover an inner wall of the opening. The second insulator is positioned to cover the inner wall of the opening with the third oxide therebetween. The third conductor is positioned to fill the opening with the third oxide and the second insulator therebetween.

Abstract: Embodiments of the present invention disclose an electrode structure, a method of fabricating the same, a thin film transistor, and an array substrate. An electrode structure is provided that comprises: an electrical conductor (23 or 25) including a protective layer and a conductive layer (10), the protective layer comprising: a first protective layer (11 and 12) disposed on a surface of the conductive layer and a second protective layer (13) disposed on at least a side face of the conductive layer, the second protective layer being configured for isolating the conductive layer from the outside.

Abstract: A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type embedded in the semiconductor layer, a first trench and a second trench formed in the semiconductor layer such that the first trench and the second trench penetrate the second semiconductor layer, a first insulating film formed on at least a side surface of the first trench, a second insulating film formed on at least a side surface of the second trench, a first sinker layer of the second conductivity type formed in a first portion of the semiconductor layer, a second sinker layer of the second conductivity type formed in the first portion of the semiconductor layer, a diode impurity region of the first conductivity type which is formed on the first surface of the semiconductor layer and forms a Zener diode by pn junction between the first sinker layer and the diode impurity region, a first wiring electrically connected to the diode impurity region, and a second wiring

Abstract: A method of forming a semiconductor device includes: depositing a first conductive plate and a second conductive plate adjacent to the first conductive plate; depositing a first insulating plate on the first conductive plate and the second conductive plate; depositing a third conductive plate on the first insulating plate; depositing a second insulating plate on the third conductive plate; forming a fourth conductive plate on the second insulating plate; forming a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate; and forming a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate.

Abstract: A graphene device for filtering color, involving a graphene structure responsive to continuous in-situ electrical gate-tuning of a Fermi level thereof and a plurality of nanoparticles disposed in relation to the graphene structure, each portion of the plurality of nanoparticles having a distinct energy bandgap in relation to another portion of the plurality of nanoparticles, and each portion of the plurality of nanoparticles configured to one of activate and deactivate in relation to the distinct energy bandgap and in response to the in-situ electrical gate-tuning of the Fermi level of the graphene structure.

Abstract: The invention discloses a light emitting array structure.

Abstract: A photoelectric conversion device includes: a substrate; a first photoelectric conversion element including a first substrate electrode, a first photoelectric conversion layer, and a first counter electrode; a second photoelectric conversion element including a second substrate electrode, a second photoelectric conversion layer, and a second counter electrode; and a connection including a groove, a conductive portion and a conductive layer, the conductive portion being provided in the groove and including a part of the first counter electrode, and the conductive portion and the conductive layer electrically connecting the first counter electrode and the second substrate electrode. The conductive layer overlaps the first counter electrode on an edge of the groove, and a total thickness of the conductive portion and the conductive layer is larger than a thickness of the first counter electrode.

Abstract: A layer structure for a photovoltaic device comprising: a transparent conductive oxide layer comprising indium tin oxide (20); a layer of tin dioxide (30) adjacent to the indium tin oxide of the transparent conductive oxide layer; and a layer of zinc magnesium oxide (40) adjacent to the layer of tin dioxide, wherein the layer of zinc magnesium oxide is an alloy of zinc oxide and magnesium oxide. A photovoltaic device comprising: a transparent conductive oxide layer comprising indium tin oxide; a layer of tin dioxide disposed on the indium tin oxide of the transparent conductive oxide layer; a layer of zinc magnesium oxide adjacent to the layer of tin dioxide, wherein the layer of zinc magnesium oxide is an alloy of zinc oxide and magnesium oxide; and an absorber layer disposed on the layer of zinc magnesium oxide, wherein the absorber layer comprises cadmium, tellurium, selenium, or any combination thereof.

Abstract: The present disclosure provides a photovoltaic module comprising a photon absorbing material for absorbing electromagnetic radiation. The photon absorbing material comprises solar cells and a glass material. The photovoltaic module also comprises an anti-reflective coating that has anti-reflective properties in a first wavelength range and reflective properties in a second wavelength range. The anti-reflective coating is positioned over the glass material. The anti-reflective coating comprises a layered structure that has layers that together have an out-of-sequence or non-graded refractive index profile.

Abstract: A method for preparing an ultrathin two-dimensional (2D) monocrystalline nanosheet, the method including: 1) placing BiX3 powder where X=I, Br, or Cl in a crucible, and putting the crucible on a first heating zone of a furnace disposed at a gas inlet of a quartz tube; placing substrates covered with metal sheets on a second heating zone of the furnace disposed at a gas outlet of the quartz tube; 2) vacuumizing the quartz tube; pumping Ar gas into the quartz tube until the air pressure is 101.325 kPa; pumping a carrier gas into the quartz tube; and 3) heating and maintaining the second heating zone; heating the first heating zone for BiX3 evaporation until producing chemical reaction between BiX3 and the metal sheets, and preparing ultrathin 2D nanosheets on the substrates simultaneously; and cooling the substrate naturally to 15-30° C.

Abstract: An apparatus includes a first processing line including a first cleaving unit adapted for separating a first solar cell into solar cell pieces. The apparatus includes a second processing line including a second cleaving unit adapted for separating a second solar cell into solar cell pieces. The apparatus includes a storing unit adapted for storing a plurality of solar cell pieces. The apparatus is adapted for transferring a solar cell piece from a first position on the first processing line to the storing unit. The apparatus is adapted for transferring the solar cell piece from the storing unit to a second position on the second processing line.

Abstract: Multi-operation tools for photovoltaic cell processing are described. In an example, a multi-operation tool includes a conveyor system to move a photovoltaic (PV) cell continuously along a conveyor path through a laser scribing station and an adhesive printing station. Furthermore, the PV cell may be aligned to a laser head of the laser scribing station and a printer head of the adhesive printing station in a single alignment operation prior to being laser scribed and printed with an adhesive in a continuous process.

Abstract: A method for producing a transferable array of light emitting devices includes forming a plurality of light emitting devices on a temporary substrate, forming at least one supporting member that is directly connected to a release layer of at least one of the light emitting devices, connecting a supporting substrate only with the at least one supporting member so that the at least one supporting member extends from the release layer of the at least one of the light emitting devices to the supporting substrate and so that the light emitting devices are spaced apart from the supporting substrate, and removing the temporary substrate. The transferable array produced by the method is also disclosed.

Abstract: [Object] To provide an optical device and a display apparatus capable of decreasing a waveguide loss, inhibiting a laser oscillation, and achieving a high-output. [Solving Means] An optical device includes a first electrode layer, a first conduction type layer, a second conduction type layer, an active layer, and a second electrode layer. The first conduction type layer includes a current injection region formed by the first electrode layer and a current non-injection region. A waveguide structure included in the first conduction type layer, the active layer, and the second conduction type layer includes a first region and a second region. The first region has a first waveguide that is the current injection region and the current non-injection region and having a first refractive index difference. The second region has a second waveguide arranged to be extended from the first waveguide to the first end and has a second refractive index difference greater than the first refractive index difference.

Abstract: A method of fabricating a micro light emitting diode (LED) panel is provided. The method includes forming a semiconductor material substrate, forming a plurality of transistor devices, transferring and bonding the transistor devices onto a circuit substrate, and transferring a plurality of micro LED devices from a micro LED device substrate to the circuit substrate. The semiconductor material substrate includes a carrier, a release layer, an inorganic insulation layer, and a semiconductor material layer. The release layer is located between the carrier and the inorganic insulation layer. The semiconductor material layer is bonded to the release layer through the inorganic insulation layer. Electron mobility of the semiconductor material layer is greater than 20 cm2/V·s. The transistor devices are disposed on the release layer and are electrically connected to the circuit substrate. The micro LED devices are electrically connected to the transistor devices. A micro LED panel is also provided.

Abstract: Disclosed herein are techniques for forming a thin-film circuit layer on an array of light-emitting diodes (LEDs). LEDs in the array of LEDs can be singulated by various processes, such as etching and ion implantation. Singulating LEDs can be performed before or after forming the thin-film circuit layer on the array of LEDs. The array of LEDs can be bonded to a transparent or non-transparent substrate.

Abstract: A display device can include a plurality of semiconductor light emitting diodes; first and second wiring electrodes respectively extending from the plurality of semiconductor light emitting diodes to supply an electrical signal to the plurality of semiconductor light emitting diodes; a plurality of pair electrodes disposed on a substrate and having a first electrode and a second electrode that generate an electric field when a current is supplied thereto; a dielectric layer disposed to cover the plurality of pair electrodes; and a covalent bond layer disposed between the dielectric layer and the plurality of semiconductor light emitting diodes, and forming a covalent bond with the dielectric layer and each of the plurality of semiconductor light emitting diodes, wherein the first wiring electrode and the second wiring electrode are located at opposite sides of the plurality of pair electrodes based on the plurality of semiconductor light emitting diodes.

Abstract: A semiconductor light emitting device includes a light emitting structure having a rod shape with first and second surfaces opposing each other and a side surface connected between the first and second surfaces, and including a first conductivity-type semiconductor providing the first surface, an active layer and a second conductivity-type semiconductor, a first electrode layer on a first region of the first surface of the light emitting structure and connected to the first conductivity-type semiconductor, the first region having a level that is vertically offset from a level of a second region adjacent thereto, and a second electrode layer connected to the second conductivity-type semiconductor.

Abstract: A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions regularly formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions includes a first portion and a second portion formed on the first portion and the first portion is integrated with the base portion; and wherein the base portion includes a first material and the first portion includes the first material.

Abstract: A red-light emitting diode includes an n-doped portion, a p-doped portion, and a light emitting region located between the n-doped portion and a p-doped portion. The light emitting region includes a light-emitting indium gallium nitride layer emitting light at a peak wavelength between 600 and 750 nm under electrical bias thereacross, an aluminum gallium nitride layer located on the light-emitting indium gallium nitride layer. and a GaN barrier layer located on the aluminum gallium nitride layer.

Abstract: This invention provides a nitride semiconductor light emitting device in which current concentration is suppressed without excessively increasing resistance at a low cost without increasing a manufacturing process. The planar shape of a mesa portion configuring a nitride semiconductor light emitting device is a shape containing a convex-shaped tip portion 352b formed by a curved line or a plurality of straight lines and abase portion 352a continuous to the convex-shaped tip portion 352b, in which an obtuse angle is formed by adjacent two straight lines in the convex-shaped tip portion formed by the plurality of straight lines. The first electrode layer 4 has visible outlines 411 and 412 along a visible outline 302 of the mesa portion through a gap 9 in planar view. The relationship between a gap W1 in the convex-shaped tip portion 352b and a gap W2 in the base portion 352a is W1>W2.

Abstract: Various embodiments comprise: a substrate; a plurality of unit electric elements arranged on the substrate at regular intervals; and at least one conductive path electrically connected to each of the plurality of unit electric elements nearby and having an energized inspection area formed at an end thereof. It is possible to determine whether each of the plurality of unit electric elements is electrically good or defective by using an energized inspection area of the conductive path. Other various embodiments may be possible.

Abstract: A light-emitting device includes a light-emitting element having a top surface, a bottom surface opposite to the top surface, and side surfaces connecting the top surface and the bottom surface. An element electrode of the light-emitting element is located on the bottom surface. A phosphor layer is disposed above the top surface of the light-emitting element and having side surfaces. A reflective member covers side surfaces of the light-emitting element and side surfaces of the phosphor layer. A dielectric multilayer film is disposed on at least one of the side surfaces of the light-emitting element and disposed on at least one of the side surfaces of the phosphor layer and not located between the light emitting element and the phosphor layer. The dielectric multilayer film is not provided on an upper surface of the phosphor layer.

Abstract: A small-sized semiconductor device with a structure for stopping and keeping uncured resin or adhesive in a desired region, which is manufactured by employing a process of curing uncured resin or adhesive that is made to wet and spread on a board, is provided. The semiconductor device includes a board mounted with a semiconductor element and includes metal patterns formed on the board. The metal patterns include a first metal pattern, a second metal pattern, and a through electrode. The first metal pattern and the second metal pattern are provided separately from each other on the board. The through electrode is disposed between the first metal pattern and the second metal pattern and penetrates through the board in the thickness direction.

Abstract: A quantum dot structure and a method for producing a quantum dot structure are disclosed. In an embodiment the quantum dot structure includes a core comprising a III-V-compound semiconductor material, an intermediate region comprising a III-V-compound semiconductor material at least partially surrounding the core, a shell comprising a III-V-compound semiconductor material at least partially surrounding the core and the intermediate region and a passivation region comprising a II-VI-compound semiconductor material at least partially surrounding the shell.

Abstract: A light-emitting device includes a substrate, an electrode, a light-emitting element, a variable light absorbing layer, and a sealing body. The electrode is formed on the substrate. The light-emitting element is disposed on the substrate and electrically connected to the electrode. The variable light absorbing layer is formed so as to cover the electrode on the substrate. The variable light absorbing layer contains a plurality of metal oxide particles that change a light absorption property by irradiation with an ultraviolet light. The sealing body is formed on the substrate so as to seal the light-emitting element. The sealing body has translucency to a light emitted from the light-emitting element.

Abstract: An optical isolation material may be applied to walls of a first cavity and a second cavity in a wafer mesh. A wavelength converting layer may be deposited into the first cavity to create a first segment and into the second cavity to create a second segment. The first segment may be attached to a first light emitting device to create a first pixel and the second segment to a second light emitting device to create a second pixel. The wafer mesh may be removed.

Abstract: A display device includes: a base layer; a pixel circuit layer on the base layer; and a display element layer on the pixel circuit layer. The pixel circuit layer includes a lens pattern at a recess between the display element layer and the base layer, the display element layer includes a light emitting element, and at least a portion of the light emitting element overlaps with the lens pattern.

Abstract: A method for transferring electroluminescent structures onto a face, referred to as the accommodating face, of an accommodating substrate. The accommodating face is moreover provided with interconnections intended to individually address each of the structures. The electroluminescent structures are initially formed on a supporting substrate and are separated by tracks. It is then proposed in the present invention to form reflective walls, vertically above the tracks, which comprise a supporting polymer (the second polymer) supporting a metal film on its sides. Such an arrangement of reflective walls makes it possible to reduce the stresses exerted on the electroluminescent structures during the transfer method according to the present invention. Moreover, the reflective walls, within the meaning of the present invention, may be produced on all the electroluminescent structures resting on a supporting substrate.

Abstract: A display device includes a substrate and pixels. The substrate includes: a display area including pixel areas, each including a first area and a second area; and a non-display area enclosing at least one side of the display area. The pixels are disposed on the pixel areas, each pixel including light emitting elements. Each pixel further includes: a pixel circuit part disposed on the first area and including at least one transistor and at least one capacitor; and a display element part disposed on the second area and including an emission area to emit light. Each of the pixel circuit part and the display element part has a multi-layer structure including one or more conductive layers and one or more insulating layers. At least one layer of the pixel circuit part and at least one layer of the display element part are disposed in a same layer.

Abstract: As the pixel density of optoelectronic devices becomes higher, and the size of the optoelectronic devices becomes smaller, the problem of isolating the individual micro devices becomes more difficult. A method of fabricating an optoelectronic device, which includes an array of micro devices, comprises: forming a device layer structure including a monolithic active layer on a substrate; forming an array of first contacts on the device layer structure defining the array of micro devices; mounting the array of first contacts to a backplane comprising a driving circuit which controls the current flowing into the array of micro devices; removing the substrate; and forming an array of second contacts corresponding to the array of first contacts with a barrier between each second contact.

Abstract: A quantum dot LED package is disclosed. The quantum dot LED package includes: a heat dissipating reflector having a through cavity; a quantum dot plate accommodated in the upper portion of the through cavity; an LED chip accommodated in the lower portion of the through cavity and whose top surface is coupled to the lower surface of the quantum dot plate; electrode pads disposed on the lower surface of the LED chip and protruding more downward than the lower surface of the heat dissipating reflector; and a resin part formed in the through cavity to fix between the LED chip and the reflector and between the quantum dot plate and the reflector.

Abstract: The present invention relates to thermoelectric power generating devices using thermoelectric elements and thereby generating electricity realizing direct conversion of heat to electric power due to difference in temperature. The present invention is targeted on improving thermoelectric efficiency of a thermoelectric device. According to the first variant of the present invention, technical result is achieved by that a) in thermoelectric element consisting of p-type leg and n-type leg jointed in serial electrical circuit, p-type leg is made of polycrystalline textured semiconductor Bi2Te3—Sb2Te3 alloy with high thermoelectric efficiency in the operating temperature range T>100° C. and b) in p-type leg, heat flux is directed from the hot end to the cold end parallel the crystallographic axis C.

Abstract: Exemplary thermoelectric devices and methods are disclosed herein. Thermoelectric generator performance is increased by the shaping isothermal fields within the bulk of a thermoelectric pellet, resulting in an increase in power output of a thermoelectric generator module. In one embodiment, a thermoelectric device includes a pellet comprising a semiconductor material, a first metal layer surrounding a first portion of the pellet, and a second metal layer surrounding a second portion of the pellet. The first and second metal layers are configured proximate to one another about a perimeter of the pellet. The pellet is exposed at the perimeter. And the perimeter is configured at a sidewall height about the pellet to provide a non-linear effect on a power output of the thermoelectric device by modifying an isotherm surface curvature within the pellet. The device also includes a metal container thermally and electrically bonded to the pellet.

Abstract: A thermoelectric material element includes: a thermoelectric material portion composed of a thermoelectric material that includes a first crystal phase and a second crystal phase during an operation, the second crystal phase being different from the first crystal phase; a first electrode disposed in contact with the thermoelectric material portion; and a second electrode disposed in contact with the thermoelectric material portion and disposed to be separated from the first electrode. During the operation, the thermoelectric material portion includes a first temperature region having a first temperature, and a second temperature region having a second temperature lower than the first temperature of the first temperature region. A ratio of the first crystal phase to the second crystal phase in the first temperature region is larger than a ratio of the first crystal phase to the second crystal phase in the second temperature region.