Abstract: A method used in forming integrated circuitry comprises forming conductive line structures having conductive vias laterally between and spaced longitudinally along immediately-adjacent of the conductive line structures. First insulating material is formed laterally between immediately-adjacent of the conductive vias. Second insulating material is formed directly above the first insulating material and directly above the conductive vias. The second insulating material comprises silicon, carbon, nitrogen, and hydrogen. A third material is formed directly above the second insulating material. The third material and the second insulating material comprise different compositions relative one another. The third material is removed from being directly above the second insulating material and the thickness of the second insulating material is reduced thereafter. A fourth insulating material is formed directly above the second insulating material of reduced thickness.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a substrate comprising an array area and a peripheral area adjacent to the array area; word line structures positioned in the array area; a word line hard mask layer positioned on the array area; a word line protection layer positioned on the word line hard mask layer; a gate electrode layer positioned on the peripheral area and separated from the word line hard mask layer and the word line protection layer; a peripheral protection layer positioned on the to gate electrode layer; and a first hard mask layer positioned over the array area and the peripheral area. A horizontal distance between the word line protection layer and the gate electrode layer is greater than or equal to three times of a thickness of the first hard mask layer.

Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate comprising a memory region and a logic region; forming a memory gate in or on the memory region; forming a plurality of first poly-silicon gates on the memory region and surrounding the memory gate; and forming a plurality of second poly-silicon gates on the logic region simultaneously with the formation of the first poly-silicon gates.

Abstract: The semiconductor memory device includes a stack structure including first material films stacked, but spaced apart from each other, in a slimming region, the first material films being stacked in a step structure in the slimming region, a contact hole exposing a portion of the first material films formed in different layers in the slimming region, and a plurality of material films that are applied and etched to electrically connect one of the material layers to a peripheral circuit.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel openings extend through the first tiers and the second tiers in the memory-block regions. Channel material of channel-material strings is formed in the channel openings and the channel material is formed in the horizontally-elongated trenches. The channel material is removed from the horizontally-elongated trenches and the channel material of the channel-material strings is left in the channel openings. After removing the channel material from the horizontally-elongated trenches, intervening material is formed in the horizontally-elongated trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.

Abstract: Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

Abstract: A NOR flash memory comprising a memory cell having a three-dimensional structure for saving power consumption is provided. The flash memory of the present invention includes a pillar part, a charge accumulating part, an insulating part, a control gate and a selecting gate. The pillar part extends in a vertical direction from a surface of a substrate and includes a conductive semiconductor material. The charge accumulating part is formed by surrounding the pillar part. The insulating part is formed by surrounding the pillar part. The control gate is formed by surrounding the charge accumulating part. The selecting gate is formed by surrounding the insulating part. One end of the pillar part is electrically connected to a bit line via a contact hole and another one end of the pillar part is electrically connected to a conductive region formed on the surface of the substrate.

Abstract: A semiconductor memory structure and method of manufacturing a semiconductor memory structure are provided. The semiconductor memory structure includes alternatively arranged stacking portions and cell regions. Each cell region includes two ferroelectric layers formed along the adjacent stacking portions; and at least one central portion disposed between the ferroelectric layers and including a first conductive structure and a second conductive structure separated by a channel isolation structure as well as two semiconductor layers formed along the ferroelectric layers. The first conductive structure includes a contact portion and an extension portion. The contact portion is disposed between the semiconductor layers. The extension portion extends from the contact portion to the channel isolation structure and is separated from the semiconductor layers through dielectric layers.

Abstract: Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

Abstract: A magnetic field controlled transistor circuit includes a first electrode, a second electrode, and a channel including a magneto-resistive material. The channel is arranged between the first and second electrodes and electrically coupled to the first and second electrodes. The transistor circuit further includes a third electrode, a fourth electrode, and a control layer including an electrically conductive material. The control layer is arranged between the third and fourth electrodes and electrically coupled to the third and fourth electrodes. In addition, an insulating layer including an insulating material is provided. The insulating layer is arranged between the channel and the control layer and configured to electrically insulate the channel from the control layer. A related method for operating a transistor circuit and a corresponding design structure are also provided.

Abstract: A memory apparatus includes a first electrode having a spin orbit material. The memory apparatus further includes a first memory device on a portion of the first electrode and a first dielectric adjacent to a sidewall of the first memory device. The memory apparatus further includes a second memory device on a portion of the first electrode and a second dielectric adjacent to a sidewall of the second memory device. A second electrode is on and in contact with a portion of the first electrode, where the second electrode is between the first memory device and the second memory device. The second electrode has a lower electrical resistance than an electrical resistance of the first electrode. The memory apparatus further includes a first interconnect structure and a second interconnect, each coupled with the first electrode.

Abstract: A variable resistance memory device and a method of manufacturing the same, the variable resistance memory device including a substrate including a first memory region and a second memory region; a plurality of first memory cells on the first memory region; and a plurality of second memory cells on the second memory region, wherein each of the first memory cells includes a first resistance element and a selection element, each of the second memory cells includes a second resistance element, and a maximum value of a variable resistance of the second resistance element is less than a maximum value of a variable resistance of the first resistance element.

Abstract: A semiconductor structure may include two vertical transport field effect transistors comprising a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory between the two vertical transport field effect transistors, the resistive random access memory may include an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer may contact the top source drain of the two vertical field effect transistor. The top source drain may function as the bottom electrode of the resistive random access memory. The semiconductor structure may include a shallow trench isolation between the two vertical transport field effect transistors, the shallow trench isolation may be embedded in a first spacer, a doped source, and a portion of a substrate.

Abstract: A memory device according to an embodiment of the present disclosure includes: a logic circuit in which a plurality of wiring layers including layers that are different in wiring pitches is stacked; and a memory element that is provided between the plurality of wiring layers.

Abstract: A memory device including a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.

Abstract: A laminate which allows to obtain an organic thin-film solar cell having excellent output characteristics and transparency is provided. The laminate as above has a titanium oxide layer that is disposed on the member serving as a light-transmissive electrode layer and serves as an electron transport layer. The titanium oxide layer has a thickness of not less than 1.0 nm and not more than 200.0 nm. The titanium oxide layer contains indium oxide and metallic indium, InOx/Ti is not less than 0.50 and not more than 20.00 in atomic ratio, and InM/Ti is less than 0.100 in atomic ratio, where an elemental titanium content is represented by Ti, an indium oxide content is represented by InOx, and a metallic indium content is represented by InM.

Abstract: A display device is provided. The display device includes a substrate, a driving transistor, a first insulation layer, a first electrode and a second insulation layer. The driving transistor is disposed on the substrate and includes a gate electrode, and the gate electrode projects a first projection profile on the substrate. The first insulation layer is disposed on the driving transistor. The first electrode is disposed on the first insulation layer, and projects a second projection profile on the substrate. The second insulation layer is disposed on the first electrode and the first insulation layer. The second insulation layer has an opening, the opening exposes a portion of the first electrode, and the opening projects a third projection profile on the substrate.

Abstract: A transparent display device includes a substrate in which a sub-pixel having an organic light emitting diode and an auxiliary sub-pixel adjacent to the sub-pixel and having an auxiliary organic light emitting diode are placed, wherein the organic light emitting diode includes a 1-1 electrode in which a transparent conductive layer and a reflective layer are laminated, and the auxiliary organic light emitting diode includes a 1-2 electrode in which the transparent conductive layer is extended and provided.

Abstract: An organic light emitting display device may include a substrate, a first pixel electrode on the substrate, a pixel defining layer on the substrate, the pixel defining layer having an opening exposing a portion of the first pixel electrode, a second pixel electrode on the portion of the first pixel electrode exposed by the opening, a hole injection layer on the second pixel electrode, the hole injection layer including a metal oxide, an organic light emitting layer on the hole injection layer; and a common electrode on the organic light emitting layer.

Abstract: An organic EL element includes a pixel electrode, a light emitting function layer that is formed on the pixel electrode, an electron injection layer formed on the light emitting function layer, and a counter electrode that is formed on the electron injection layer and that has semi-transmissive reflectivity, in which the counter electrode contains a reductive material that reduces material of the electron injection layer and Ag with atomic ratio of 75% or more, and an adsorption layer is formed on the counter electrode.

Abstract: A flexible cover window includes a lower glass substrate including a first lower glass substrate; a second lower glass substrate, the first lower glass substrate and the second lower glass substrate being spaced apart from each other; an upper glass substrate that is disposed above the lower glass substrate and is thinner than the lower glass substrate; and an adhesive member disposed between the lower glass substrate and the upper glass substrate and extending between the first lower glass substrate and the second lower glass substrate.

Abstract: A display panel and an electronic device are provided. The display panel includes: an opening area; a display area surrounding the opening area; at least one isolation ring, wherein at least a part of the at least one isolation ring is located between the display area and the opening area, and the at least one isolation ring surrounds the opening area; and a drainage structure extending from a sidewall of an isolation ring in the at least one isolation ring along a straight line passing through a center of the isolation ring.

Abstract: A display panel is provided, the display panel including: a substrate including: a front display area; a first side display area; a second side display area; a corner display area between the first side display area and the second side display area; and an intermediate display area between the front display area and the corner display area; an intermediate display element including a pixel electrode in the intermediate display area; a lower layer between the substrate and the pixel electrode, the lower layer including a groove; and a dam portion on the lower layer and extending to define a boundary between the intermediate display area and the corner display area, wherein the groove includes a first groove and a second groove, the first groove extending in parallel with the dam portion, and the second groove extending in a direction crossing a direction in which the dam portion.

Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided.

Abstract: A display, a jig and a method for making the display, and a terminal equipment are provided. The display includes a display body. Further, at least one side wall of the display body is provided with a waterproof coating.

Abstract: A display apparatus includes a flexible substrate and a first insulation layer disposed on the flexible substrate. The flexible substrate includes a bending area. The first insulation layer includes a first unevenness disposed over the bending area. The first unevenness includes two or more steps in at least a portion of the first unevenness.

Abstract: Provided are a light absorber represented by Formula 1 and an organic electroluminescence device including a light absorption layer including the light absorber: In Formula 1, X1 is O or S.

Abstract: A display device includes a display panel that displays an image and including a first display area, in which a plurality of first pixels is disposed, and a second display area which is adjacent to the first display area and in which a plurality of second pixels is disposed and a gate driving block which overlaps the second display area and transmits driving signals to the plurality of first pixels and the plurality of second pixels. Each of the plurality of first pixels includes a first shielding layer. Each of the plurality of second pixels includes a second shielding layer. A first common voltage is applied to the first shielding layer, and a second common voltage having a voltage level different from a voltage level of the first common voltage is applied to the second shielding layer.

Abstract: A display panel and a display device are provided, and the display panel includes an array substrate. The array substrate includes a plurality of pixel circuits, a plurality of reference signal lines and a plurality of pixel connecting semiconductor portions. The plurality of pixel circuits is arranged in an array in a row direction and a column direction, each pixel circuit includes a pixel driving semiconductor portion which includes two fixed potential nodes, and the row direction intersects the column direction. The fixed potential nodes are electrically connected to at least one of the plurality of reference signal lines. Two fixed potential nodes adjacent in a first direction are electrically connected by one of the plurality of the pixel connecting semiconductor portions, and the first direction is parallel to a plane where the array substrate is located.

Abstract: A display device includes: a substrate; a polycrystalline semiconductor layer which includes a first electrode, a channel, and a second electrode of a driving transistor disposed on the substrate; a first gate insulating layer disposed on the polycrystalline semiconductor layer; a gate electrode of the driving transistor which is disposed on the first gate insulating layer and overlaps the channel; a lower first scan line disposed on the first gate insulating layer; a second gate insulating layer disposed on the gate electrode and on the lower first scan line; a first lower boost electrode disposed on the second gate insulating layer; a first interlayer-insulating layer disposed on the first lower boost electrode; an oxide semiconductor layer disposed on the first interlayer-insulating layer and including a first upper boost electrode overlapping the first lower boost electrode; and a first connection electrode connecting the gate electrode and the first upper boost electrode.

Abstract: A display apparatus includes a thin film transistor disposed in a display area of a substrate and a display device in the display area that is electrically connected to the thin film transistor, an encapsulation layer that protects the display device, at least one through portion formed in the display area that vertically penetrates the substrate and a plurality of layers stacked on the substrate, and a first groove and a second groove that are spaced apart from each other and that surround the at least one through portion. A flow-restriction portion is disposed in a region between the first groove and the second groove that protrudes upwards from the substrate and confines an organic encapsulation layer of the encapsulation layer.

Abstract: A transparent display device may optimize arrangement areas of a plurality of signal lines and circuit areas, and may prevent a luminance difference from occurring between subpixels for emitting light of the same color. The transparent display device comprises a substrate provided with transmissive areas, a first non-transmissive area provided between the transmissive areas in a first direction, and a second non-transmissive area provided between the transmissive areas in a second direction, first signal lines provided along the first non-transmissive area in the first non-transmissive area and extended from an overlapping area, in which the first non-transmissive area and the second non-transmissive area cross each other, in a direction crossing the first direction, and second signal lines provided along the second non-transmissive area in the second non-transmissive area and extended from the overlapping area in a direction crossing the second direction.

Abstract: A display device includes: a base layer including an active area and a non-active area adjacent to the active area; a display circuit layer including a pixel circuit at the active area of the base layer, and a driving circuit at the non-active area, the driving circuit to supply a driving signal to the pixel circuit; and a display element layer on the display circuit layer and including light emitting elements to emit light. The non-active area includes a valley area formed by removing a portion of an organic insulation layer at the display circuit layer, the driving circuit includes a buffer transistor to output the driving signal, and the buffer transistor includes a control electrode and a semiconductor layer overlapping the valley area in a plan view.

Abstract: An anisotropic conductive film includes a conductive layer; a first resin insulating layer over a first surface of the conductive layer; and a second resin insulating layer over a second surface of the conductive layer, wherein the conductive layer comprises a plurality of conductive particles and a nano fiber connecting the plurality of conductive particles to each other, each of the plurality of conductive particles comprising a plurality of needle-shaped protrusions having a conical shape, and wherein the first resin insulating layer and the second resin insulating layer comprise a same material and have different thicknesses.

Abstract: An organic light emitting diode display includes a substrate, a semiconductor pattern disposed on the substrate, a first conductive layer disposed on the semiconductor pattern and including a first gate electrode having an island-shaped structure, a second gate electrode having an island-shaped structure, and a third gate electrode having an island-shaped structure, and a second conductive layer disposed on the first conductive layer and including a first initialization voltage line overlapping the first gate electrode, a scan line overlapping the second gate electrode, and a control signal line overlapping the third gate electrode, where the control signal line is electrically connected to the third gate electrode, the scan line is electrically connected to the second gate electrode, and the first initialization voltage line, the scan line, and the control signal line extend in a first direction.

Abstract: A display device includes: a substrate comprising a display area and a peripheral area outside the display area; a first connection line in the display area, the first connection line comprising a first portion extending along a first column of the display area and in the first column, a third portion extending along a second column of the display area and in the second column, and a second portion connecting the first portion to the third portion; and a second connection line in the peripheral area and connected to the third portion of the first connection line and a data line in a third column of the display area.

Abstract: A capacitor includes an active layer, a gate insulation layer on the active layer, a gate electrode on the gate insulation layer, an interlayer insulating layer on the gate electrode, and a first electrode on the interlayer insulating layer and connected to the active layer through at least one contact hole.

Abstract: Provided is a tiled display device including a first sub-display panel on which a plurality of unit pixels is formed, and a second sub-display panel on which a plurality of unit pixels is formed, and located adjacent to the first sub-display panel, wherein each of the unit pixels includes a display element for emitting colored light, and a plurality of sub-pixels having a pixel circuit for driving the display element, and wherein an arrangement order of sub-pixels in the unit pixels corresponding to a current row, and an arrangement order of the sub-pixels in the unit pixels corresponding to a previous row or a next row, are different from each other.

Abstract: A diode display includes a substrate having a first island and a second island spaced apart from each other, a first pixel disposed on the first island, and a second pixel disposed on the second island. The first pixel includes a first base layer, a first transistor on the first base layer, a first light emitting element electrically connected to the first transistor, and a first encapsulation layer covering the first light emitting element. The second pixel includes a second base layer, a second transistor on the second base layer, a second light emitting element connected to the second transistor, and a second encapsulation layer covering the second light emitting element.

Abstract: An electronic apparatus has a through module hole defined in an active area and includes a first sensing pattern and a second sensing pattern spaced apart from each other in one direction with the module hole disposed therebetween. A third sensing pattern and a fourth sensing pattern are spaced apart from each other in a direction crossing the one direction with the module hole disposed therebetween. A first connection line extends along a portion of the module hole and connects the first sensing pattern acid the second sensing pattern to each other. A second connection line extends along a portion of the module hole and connects the third sensing pattern and the fourth sensing pattern to each other. The first connection line and the second connection line are disposed on the same layer and are spaced apart from each other.

Abstract: A display device includes a display panel including a hole area, a display area around the hole area, and a non-display area around the display area, a first-first insulating layer disposed in the hole area, sensing electrodes disposed on the display area, a crack detection pattern disposed on the first-first insulating layer in the hole area, a crack detection line disposed on the non-display area, and a connection pattern disposed in a first sensing electrode of the sensing electrodes disposed on the display area to be insulated from the sensing electrodes, and connected to the crack detection pattern and the crack detection line, the first sensing electrode being disposed between the hole area and the non-display area. An edge of the first-first insulating layer disposed at a boundary between the display area and the hole area has a step structure of at least two steps.

Abstract: An OLED display panel may include a substrate, an OLED light emitter on the substrate and configured to emit light, and a visible light sensor on the substrate and configured to detect at least a portion of the emitted light based on reflection of the portion of the emitted light from a recognition target. The visible light sensor is in a non-light emitting region adjacent to the OLED light emitter so as to be horizontally aligned with the OLED light emitter in a horizontal direction extending parallel to an upper surface of the substrate, or between the substrate and a non-light emitting region adjacent to the OLED light emitter such that the visible light sensor is vertically aligned with the non-light emitting region in a vertical direction extending perpendicular to the upper surface of the substrate.

Abstract: The present disclosure discloses a method for manufacturing a light-emitting device using laser etching including: a first light-emitting layer forming step for depositing a first light-emitting layer on an surface of a hole transport layer deposited on an upper surface of an anode substrate; a first light-emitting device forming step for etching the first light-emitting layer to form a first light-emitting device; a second light-emitting layer depositing step for depositing a second light-emitting layer on a region including the upper surface of the hole transport layer; a second light-emitting device forming step for etching the second light-emitting layer to form a second light-emitting device; a third light-emitting layer depositing step for depositing a third light-emitting layer on a region including the upper surface of the hole transport layer; and a third light-emitting device forming step for etching the third light-emitting layer to form a third light-emitting device.

Abstract: Embodiments of the disclosed subject matter provide a device including a carrier plate, and a die including a mating surface with a patterned thin film of metal or metal oxide surface bonded to the carrier plate using a solder preform with voids that overlay the patterned thin film on the die, where the oxide surface is disposed opposite a moat in a mating surface of the carrier plate, and where the voided regions remain free of solder when the solder is reflowed.

Abstract: An etchant composition includes an inorganic acid compound of about 8 wt % to about 15 wt %, a sulfonic acid compound of about 2.5 wt % to about 8 wt %, a sulfate compound of about 6 wt % to about 14 wt %, an organic acid compound of about 40 wt % to about 55 wt %, a metal or metal salt of about 0.01 wt % to about 0.06 wt %, and water.

Abstract: A display apparatus includes a base layer including device counterparts and bridges, the bridges being located around the device counterparts and connecting the device counterparts to each other, an inorganic insulating layer located over the base layer and having openings exposing at least a portion of at least one of the bridges, organic layers filling the openings, wires located over the organic layers, display devices located over the device counterparts, and encapsulation films each of which has a form of an island to correspond to a corresponding one of the device counterparts, each of the encapsulation films including a first inorganic encapsulation film covering a corresponding one of the display devices, an organic encapsulation film located over the first inorganic encapsulation film, and a second inorganic encapsulation film covering the organic encapsulation film and contacting the first inorganic encapsulation film outside of the organic encapsulation film.

Abstract: A substrate including a self-supporting tri-layer stack is described. The tri-layer stack includes first and second outer layers and a biaxially oriented layer disposed between and in direct contact with the first and second outer layers. The biaxially oriented layer may include a first polyester having greater than 45 mole percent naphthalate units and greater than 45 mole percent ethylene units. Each of the first and second outer layers includes a second polyester which may include 40 to 50 mole percent naphthalate units, at least 25 mole percent ethylene units, and 10 to 25 mole percent of branched or cyclic C4-C10 alkyl units.

Abstract: An organic molecule having a structure of Formula I for the application in optoelectronic devices: wherein m is an integer from 1 to 2; n is an integer from 0 to 4; o is an integer from 0 to 2; with the sum (m+n+o) being an integer from 1 to 5; and X is selected from the group consisting of hydrogen, CN and CF3.