Patents Issued in June 20, 2023
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Patent number: 11683979Abstract: There is disclosed a compound Formula I In Formula I: Z is CR4R5, C?CR4R5, SiR4R5, GeR4R5, NR4a, PR4a, P(O)R4a, O, S, SO, SO2, Se; SeO, SeO2, Te, TeO, or TeO2; R1-R3 are the same or different at each occurrence and are D, aryl, heteroaryl, alkyl, amino, silyl, germyl, deuterated aryl, deuterated heteroaryl, deuterated alkyl, deuterated amino, deuterated silyl, or deuterated germyl, where two groups selected from R1, R2, and R3 can be joined together to form a fused ring; R4-R5 are the same or different at each occurrence and are H, D, aryl, heteroaryl, alkyl, amino, silyl, germyl, deuterated aryl, deuterated heteroaryl, deuterated alkyl, deuterated amino, deuterated silyl, or deuterated germyl; R4ais alkyl, silyl, germyl, aryl, or a deuterated analog thereof; a is an integer from 0-4; b and c are the same or different and are an integer from 0-3.Type: GrantFiled: January 20, 2016Date of Patent: June 20, 2023Inventors: Viacheslav V. Diev, John David Allen, Kerwin D. Dobbs, Weiying Gao, Michael Henry Howard, Jr., Michael R. Moseley, Weishi Wu
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Patent number: 11683980Abstract: The present invention relates to a condensed fluorene derivative comprising a hetero ring, and, more specifically, relates to an intermediate for producing a hetero-ring compound able to exhibit the outstanding element characteristic of a long life and outstanding luminance and light-emission efficiency when used as an organic light-emitting material.Type: GrantFiled: June 10, 2015Date of Patent: June 20, 2023Assignee: SFC CO., LTD.Inventors: Soon-Wook Cha, Ju-man Song, Yu-rim Lee, Sang-Woo Park, Hee-Dae Kim, Seok-Bae Park
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Patent number: 11683981Abstract: A compound comprising a ligand LA, having a structure of Formula I, is provided. In Formula I, A1 to A8 are each independently CR or N; at least two adjacent ones of A1 to A8 are CR and the Rs are joined together to form a six-membered ring fused to ring A or ring C; X is O, S, or Se; each R and RB is independently hydrogen or a substituent; any adjacent substituents are optionally joined or fused into a ring; the ligand LA is coordinated to a metal M; the metal M is bonded to ring A through a M-C bond; the metal M can be coordinated to other ligands; and the ligand LA is optionally linked with other ligands. Formulations, OLEDs, and consumer products containing such compounds are also disclosed.Type: GrantFiled: August 5, 2021Date of Patent: June 20, 2023Assignee: UNIVERSAL DISPLAY CORPORATIONInventors: Mingjuan Su, Walter Yeager, Alan Deangelis, Bin Ma, Jui-Yi Tsai, Lichang Zeng, Chuanjun Xia
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Patent number: 11683982Abstract: An organic compound including a carbazolyl moiety having a p-type property, a dibenzofuranyl or dibenzothiophenyl moiety having an n-type property and further substituted with a dibenzofuranyl or dibenzothiophenyl moiety is disclosed. An organic light emitting diode and an organic light emitting device including the organic compound are also disclosed. The organic compound has excellent thermal resistance and a high energy level due to the combination of fused hetero aromatic rings. Therefore, the organic light emitting diode and the organic light emitting device including the organic compound show excellent luminous efficiency and an improved luminous lifetime.Type: GrantFiled: December 11, 2019Date of Patent: June 20, 2023Assignees: LG DISPLAY CO., LTD., LG CHEM, LTD.Inventors: Jun-Yun Kim, Tae-Ryang Hong, Joong-Hwan Yang, Wan-Pyo Hong, Jin-Joo Kim, Hong-Sik Yoon
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Patent number: 11683983Abstract: An organic light emitting diode includes a first electrode; a second electrode facing the first electrode; and an emitting material layer including a first compound and a second compound and positioned between the first and second electrodes. An energy level of the first compound and an energy level of the second compound satisfy a pre-determined condition. Further, an organic light emitting device may include the organic light emitting diode.Type: GrantFiled: September 28, 2020Date of Patent: June 20, 2023Assignee: LG Display Co., Ltd.Inventors: Bo-Min Seo, Hyong-Jong Choi, Jun-Yun Kim
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Patent number: 11683984Abstract: A heat conversion device according to an embodiment of the present invention comprises: a frame comprising multiple unit modules arranged in a first direction and in a second direction intersecting with the first direction, respectively, and a first cooling water inflow tube and a first cooling water discharge tube formed along the first direction so as to support the multiple unit modules; multiple second cooling water inflow tubes connected to the first cooling water inflow tube and arranged on one side of the multiple unit modules along the second direction; and multiple second cooling water discharge tubes connected to the first cooling water discharge tube and arranged on the other side of the multiple unit modules along the second direction. Each unit module comprises a cooling water passage chamber, a first thermoelectric module arranged on a first surface of the cooling water passage chamber, and a second thermoelectric module arranged on a second surface of the cooling water passage chamber.Type: GrantFiled: July 4, 2019Date of Patent: June 20, 2023Assignee: LG INNOTEK CO., LTD.Inventors: Un Hak Lee, Jong Hyun Kang
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Patent number: 11683985Abstract: A thermoelectric conversion element is made of a material with a band structure having Weyl points in the vicinity of Fermi energy. The thermoelectric conversion element has a thermoelectric mechanism for generating electromotive force by the anomalous Nernst effect. A thermoelectric conversion device includes a substrate; and a power generator provided on the substrate and including a plurality of thermoelectric conversion elements. Each of the plurality of thermoelectric conversion elements has a shape extending in one direction, and is made of a material identical to that of the above-mentioned thermoelectric conversion element. The plurality of thermoelectric conversion elements is arranged in parallel to one another in a direction perpendicular to the one direction and electrically connected in series to one another in a serpentine shape.Type: GrantFiled: July 3, 2018Date of Patent: June 20, 2023Assignee: THE UNIVERSITY OF TOKYOInventors: Satoru Nakatsuji, Akito Sakai
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Patent number: 11683986Abstract: A thermoelectric conversion device includes: a thermoelectric module layer, in which a thermoelectric conversion chip is surrounded by a thermal insulation rubber containing a rubber component and a hollow filler forming a plurality of air gaps that are independent from one another; an insulation base layer and an insulation intermediate layer, which are thermal-conductive insulation sheets and sandwiches the thermoelectric module layer; a heat diffusion layer, which has a higher thermal conductance than those of the insulation base layer and the insulation intermediate layer and is stacked on the insulation intermediate layer; and a thermal radiation layer, which has thermal conductivity and is stacked on the heat diffusion layer. And at least one pair among the adjacent layers is bonded through chemical bonds.Type: GrantFiled: November 13, 2017Date of Patent: June 20, 2023Assignee: ASAHI FR R&D CO., LTD.Inventors: Syuhei Toyoshima, Syo Mihara, Koichi Abe
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Patent number: 11683987Abstract: An electrocaloric element for a heat transfer system includes an electrocaloric material of a copolymer of (i) vinylidene fluoride, and (ii) an addition polymerization monomer that is larger than vinylidene fluoride and includes a substituent more electronegative than chlorine. Electrodes are disposed on opposite surfaces of the electrocaloric material, and an electric power source is configured to provide voltage to the electrodes. The system also includes a first thermal flow path between the electrocaloric material and a heat sink, and a second thermal flow path between the electrocaloric material and a heat source.Type: GrantFiled: June 18, 2018Date of Patent: June 20, 2023Assignee: CARRIER CORPORATIONInventors: Scott Alan Eastman, Sergei F. Burlatsky, Joseph V. Mantese, Wei Xie
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Patent number: 11683988Abstract: A device includes a conductive feature, a dielectric layer, a bottom electrode via, and a liner layer. The dielectric layer is over the conductive feature. The bottom electrode via is in the dielectric layer and over the conductive feature. A topmost surface of the bottom electrode via is substantially flat. A liner layer cups an underside of the bottom electrode via. The liner layer has a topmost end substantially level with the topmost surface of the bottom electrode via.Type: GrantFiled: April 2, 2021Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Sheng-Chih Lai, Han-Ting Tsai, Chung-Te Lin
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Patent number: 11683989Abstract: A method of manufacturing a data storage device may include forming a magnetic tunnel junction layer on a substrate, irradiating a first ion beam on the magnetic tunnel junction layer to form magnetic tunnel junction patterns separated from each other, irradiating a second ion beam on the magnetic tunnel junction layer, and irradiating a third ion beam on the magnetic tunnel junction layer. The first ion beam may be irradiated at a first incident angle. The second ion beam may be irradiated at a second incident angle that may be smaller than the first incident angle. The third ion beam may be irradiated to form sidewall insulating patterns on sidewalls of the magnetic tunnel junction patterns based on re-depositing materials separated by the third ion beam on the sidewalls of the magnetic tunnel junction patterns.Type: GrantFiled: February 8, 2021Date of Patent: June 20, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jongchul Park, Sang-Kuk Kim
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Patent number: 11683990Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A dielectric layer is disposed over an upper surface of the bottom electrode. A top electrode is disposed over an upper surface of the dielectric layer and is in direct electrical contact with a lower surface of the upper metal layer.Type: GrantFiled: December 17, 2019Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Chern-Yow Hsu, Shih-Chang Liu
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Patent number: 11683991Abstract: The present disclosure provides a method for manufacturing semiconductor structure, including forming an insulation layer, forming a first via trench in the insulation layer, forming a barrier layer in the first via trench, forming a bottom electrode via in the first via trench, forming a magnetic tunneling junction (MTJ) layer above the bottom electrode via, and performing an ion beam etching operation, including patterning the MTJ layer to form an MTJ and removing a portion of the insulation layer from a top surface.Type: GrantFiled: November 24, 2020Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Patent number: 11683992Abstract: A magnetic memory device may include an interlayer insulating layer on a substrate, a bottom electrode contact disposed in the interlayer insulating layer, and a magnetic tunnel junction pattern on the bottom electrode contact. The bottom electrode contact may include a second region and a first region, which are sequentially disposed in a first direction perpendicular to a top surface of the substrate so that the second region is between the first region and the top surface of the substrate. A first width of the first region may be smaller than a second width of the second region, when measured in a second direction parallel to the top surface of the substrate.Type: GrantFiled: December 27, 2020Date of Patent: June 20, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyungjong Jeong, Ki Woong Kim, Younghyun Kim, Junghwan Park, Byoungjae Bae, Se Chung Oh, Jungmin Lee, Kyungil Hong
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Patent number: 11683993Abstract: Aspects of the present disclosure generally relate to a spintronic device for use in a magnetic media drive, a magnetoresistive random access memory device, a magnetic sensor, or a magnetic recording write head. The spintronic device comprises a multilayer structure having a negative anisotropic field and a negative spin polarization. The multilayer structure comprises a plurality of layers, each layer of the plurality of layers comprising a first sublayer comprising Fe and a second sublayer comprising Co. At least one of the first sublayer and the second sublayer comprises one or more of Cr, V, and Ti. The first and second sublayers are alternating. The negative anisotropic field of the multilayer structure is between about ?0.5 T to about ?0.8 T, and an effective magnetization of the multilayer structure is between about 2.4 T to about 2.8 T.Type: GrantFiled: March 23, 2021Date of Patent: June 20, 2023Assignee: Western Digital Technologies, Inc.Inventors: Susumu Okamura, Christian Kaiser, James Mac Freitag
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Patent number: 11683994Abstract: A perpendicular magnetic tunnel junction is disclosed wherein a metal insertion (MIS) layer is formed within a free layer (FL), a partially oxidized Hk enhancing layer is on the FL, and a nitride capping layer having a buffer layer/nitride layer (NL) is on the Hk enhancing layer to provide an improved coercivity (Hc)/switching current (Jc) ratio for spintronic applications. Magnetoresistive ratio is maintained above 100%, resistance×area (RA) product is below 5 ohm/?m2, and thermal stability to 400° C. is realized. The FL comprises two or more sub-layers, and the MIS layer may be formed within at least one sub-layer or between sub-layers. The buffer layer is used to prevent oxygen diffusion to the NL, and nitrogen diffusion from the NL to the FL. FL thickness is from 11 Angstroms to 25 Angstroms while MIS layer thickness is preferably from 0.5 Angstroms to 4 Angstroms.Type: GrantFiled: January 24, 2022Date of Patent: June 20, 2023Assignee: Headway Technologies, Inc.Inventors: Santiago Serrano Guisan, Luc Thomas, Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong
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Patent number: 11683995Abstract: Techniques regarding lithographic processes for fabricating Josephson junctions are provided. For example, one or more embodiments described herein can comprise a method that can include depositing a first resist layer onto a second resist layer. The first resist layer can include a bridge portion that defines an opening for forming a Josephson junction. The method can also comprise depositing a third resist layer onto the bridge portion. The third resist layer can shield the opening from an angled deposition of a superconducting material during fabrication of the Josephson junction.Type: GrantFiled: August 3, 2020Date of Patent: June 20, 2023Assignee: International Business Machines CorporationInventors: Kenneth P. Rodbell, Leonidas Ernesto Ocola, Charles Thomas Rettner, Mary E Rothwell, Elbert Emin Huang
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Patent number: 11683996Abstract: A superconducting coupling device includes a resonator structure. The resonator structure has a first end configured to be coupled to a first device and a second end configured to be coupled to a second device. The device further includes an electron system coupled to the resonator structure, and a gate positioned proximal to a portion of the electron system. The electron system and the gate are configured to interrupt the resonator structure at one or more predetermined locations forming a switch. The gate is configured to receive a gate voltage and vary an inductance of the electron system based upon the gate voltage. The varying of the inductance induces the resonator structure to vary a strength of coupling between the first device and the second device.Type: GrantFiled: October 1, 2020Date of Patent: June 20, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sean Hart, Jay M. Gambetta, Patryk Gumann
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Patent number: 11683997Abstract: A superconducting article includes a substrate and a superconducting metal oxide film formed on the substrate. The metal oxide film including ions of an alkali metal, ions of a transition metal, and ions of an alkaline earth metal or a rare earth metal. For instance, the metal oxide film can include Rb ions, La ions, and Cu ions. The superconducting metal oxide film can have a critical temperature for onset of superconductivity of greater than 250 K, e.g., greater than room temperature.Type: GrantFiled: December 12, 2018Date of Patent: June 20, 2023Assignee: Quantum Designed Materials Ltd.Inventor: Refael Gatt
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Patent number: 11683998Abstract: A semiconductor structure for a vertical phase change memory cell that includes a bottom electrode on a portion of a semiconductor substrate and a pair of vertical phase change bridge elements that are each on a portion of the bottom electrode. The semiconductor structure for the vertical phase change memory cell includes a dielectric material separating the pair of vertical phase change bridge elements and a top electrode over the pair of vertical phase change bridge elements.Type: GrantFiled: March 22, 2021Date of Patent: June 20, 2023Assignee: International Business Machines CorporationInventors: Juntao Li, Kangguo Cheng, Carl Radens, Ruilong Xie
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Patent number: 11683999Abstract: The present disclosure relates to a memory device. The memory device includes an access device arranged on or within a substrate and coupled to a word-line and a source line. A plurality of lower interconnects are disposed within a lower dielectric structure over the substrate. A first electrode is coupled to the plurality of lower interconnects. The plurality of lower interconnects couple the access device to the first electrode. A second electrode is over the first electrode. One or more upper interconnects are disposed within an upper dielectric structure laterally surrounding the second electrode. The one or more upper interconnects couple the second electrode to a bit-line. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes one or more metals having non-zero concentrations that change as a distance from the substrate varies.Type: GrantFiled: June 7, 2022Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hai-Dang Trinh, Cheng-Yuan Tsai, Hsing-Lien Lin, Wen-Ting Chu