Abstract: According to one embodiment, a position measuring apparatus includes a substrate holding part, a projection part, a liquid supply part, an imaging part, a position measuring part, and a control unit. The substrate holding part is configured to hold a substrate including at least part of a circuit pattern. The projection part is configured to irradiate the substrate held on the substrate holding part with illumination light, and to transmit reflected light from the substrate, of the illumination light radiated on the substrate. The liquid supply part is configured to supply a liquid into a space between the substrate held on the substrate holding part and the projection part. The imaging part is configured to receive the reflected light transmitted through the projection part, and to generate an image signal based on the reflected light. The position measuring part is configured to obtain positional information on a position of the substrate holding part.

Abstract: A composite sintered body includes a base material (i.e., a main body) using ceramics as a main material and an electrode disposed inside the main body or on a surface thereof. The electrode contains WC and TiN. It is thereby possible to reduce the difference in thermal expansion coefficient between the electrode and the main body while suppressing an increase in the resistivity of the electrode. As a result, it is possible to suppress any damage such as a crack, a breakage, or the like of the main body, which is caused by the difference in the thermal expansion coefficient.

Abstract: Embodiments of the present disclosure are related to carrier assemblies that can clamp more than one optical device substrates and methods for forming the carrier assemblies. The carrier assembly includes a carrier, one or more substrates, and a mask. The carrier is magnetically coupled to the mask to retain the one or more substrates. The carrier assembly is used for supporting and transporting the one or more substrates during processing. The carrier assembly is also used for masking the one or more substrates during PVD processing. Methods for assembling the carrier assembly in a build chamber are described herein.

Abstract: A bonding apparatus includes a first holder, a first transforming device, a second holder, a second transforming device, a suction device and a control device. The first holder attracts and holds a first substrate from above. The first transforming device transforms the first substrate held by the first holder such that a central portion of the first substrate is protruded downwards. The second holder is provided under the first holder, and attracts and holds a second substrate, which is to be bonded to the first substrate, from below. The second transforming device transforms the second substrate held by the second holder such that a central portion of the second substrate is protruded upwards. The suction device generates different attracting forces in multiple division regions included in an attraction region of the second substrate. The control device controls the suction device.

Abstract: A holding mechanism includes a wafer holding section that holds a wafer under suction, and a frame support section that is disposed on the outer circumference of the wafer holding section and that supports a frame. The frame support section includes a permanent magnet.

Abstract: A height adjustable semiconductor wafer support is provided. The height adjustable semiconductor wafer support includes a chuck for supporting a semiconductor wafer, an adjustment mechanism having a top surface for supporting the chuck, and a stage coupled to the adjustment mechanism such that movement of the top surface of the adjustment mechanism relative to the stage changes a distance between the top surface of the adjustment mechanism and a top surface of the stage.

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.

Abstract: Process chamber lid assemblies and process chambers comprising same are described. The lid assembly has a housing with a gas dispersion channel in fluid communication with a lid plate. A contoured bottom surface of the lid plate defines a gap to a top surface of a gas distribution plate. A pumping channel is formed between an upper outer peripheral contour of the gas distribution plate and the lid plate.

Abstract: The present disclosure relates to a semiconductor module. The semiconductor module includes an excitable element located on a first side of a substrate. A first ground structure is disposed between the first side of the substrate and the excitable element. The first ground structure includes a conductive via extending through the substrate and an interconnect disposed over a topmost surface of the conductive via facing away from the substrate. A second ground structure is located on a second side of the substrate, opposing the first side, and electrically coupled to the first ground structure.

Abstract: A method of manufacturing a through silicon via (TSV) is provided in the present invention, including steps of forming a TSV sacrificial structure in a substrate, wherein the TSV sacrificial structure contacts a metal interconnect on the front side of the substrate, performing a backside thinning process to expose the TSV sacrificial structure from the back side of the substrate, removing the TSV sacrificial structure to form a through silicon hole, and filling the through silicon hole with conductive material to form a TSV.

Abstract: A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.

Abstract: A film forming system for forming a magnetic film is provided. The film forming system includes a processing module configured to form the magnetic film on a substrate, a magnetization characteristic measuring device configured to measure magnetization characteristics of the magnetic film formed on the substrate in the processing module, and a transfer unit configured to transfer the substrate between the processing module and the magnetization characteristic measuring device. The magnetization characteristic measuring device includes a magnetic field applying mechanism having a permanent magnet magnetic circuit configured to apply a magnetic field to the substrate and adjust the magnetic field to be applied to the substrate, and a detector configured to detect magnetization characteristics of the substrate.

Abstract: A method of detecting a polishing endpoint includes storing a plurality of library spectra, measuring a sequence of spectra from the substrate in-situ during polishing, and for each measured spectrum of the sequence of spectra, finding a best matching library spectrum from the plurality of library spectra to generate a sequence of best matching library spectra. Each library spectrum has a stored associated value representing a degree of progress through a polishing process, and the stored associated value for the best matching library spectrum is determined for each best matching library spectrum to generate a sequence of values representing a progression of polishing of the substrate. The sequence of values is compared to a target value, and a polishing endpoint is triggered when the sequence of values reaches the target value.

Abstract: The present invention provides a glass substrate in which in a step of sticking a glass substrate and a silicon-containing substrate to each other, bubbles hardly intrude therebetween. The present invention relates to a glass substrate for forming a laminated substrate by lamination with a silicon-containing substrate, having a warpage of 2 ?m to 300 ?m, and an inclination angle due to the warpage of 0.0004° to 0.12°.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having an upper surface and a recessed surface extending in a closed loop around the upper surface. The recessed surface is vertically between the upper surface and a lower surface of the first substrate opposing the upper surface. A first plurality of interconnects are disposed within a first dielectric structure on the upper surface. A dielectric protection layer is over the recessed surface, along a sidewall of the first dielectric structure, and along a sidewall of the first substrate. The first substrate extends from directly below the dielectric protection layer to laterally outside of the dielectric protection layer.

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.

Abstract: A packaged electronic device includes a substrate comprising a die pad and a lead spaced apart from the die. An electronic device is attached to the die pad top side. A conductive clip is connected to the substrate and the electronic device, and the conductive clip comprises a plate portion attached to the device top side with a conductive material, a clip connecting portion connected to the plate portion and the lead, and channels disposed to extend inward from a lower side of the plate portion above the device top side. The conductive material is disposed within the channels. In another example, the plate portion comprises a lower side having a first sloped profile in a first cross-sectional view such that an outer section of the first sloped profile towards a first edge portion of the plate portion is spaced away from the electronic device further than an inner section of the first sloped profile towards a central portion of the plate portion. Other examples and related methods are also disclosed herein.

Abstract: A semiconductor device includes a substrate that includes an opening extending through a thickness of the substrate, a frame that includes an integrated circuit (IC) die pad in the opening and a plurality of arms extending outwardly from the IC die pad, an IC mounted on the IC die pad, a plurality of bonding elements electrically coupling the substrate with the IC without the frame being an intermediary coupling element, and an encapsulant surrounding the IC, the plurality of bonding elements, and the plurality of arms. The substrate has a first major surface and a second major surface. Each arm is devoid of a contact pad. Each arm has a distal end coupled to the first major surface of the substrate, and each arm has a proximal end disposed over the first major surface of the substrate.

Abstract: In some examples, a semiconductor package comprises a die pad, a semiconductor die on the die pad, and a mold compound covering the die pad and the semiconductor die. The semiconductor package includes a conductive component including a roughened surface, the roughened surface having a roughness ranging from an arithmetic mean surface height (SA) of 1.4 to 3.2. The mold compound is coupled to the roughened surface. The semiconductor package includes a bond wire coupling the semiconductor die to the roughened surface. The bond wire is directly coupled to the roughened surface without a precious metal positioned therebetween.

Abstract: A semiconductor package includes a substrate, a set of terminals protruding from a first surface of the substrate, a power stage physically and thermally coupled to the first surface of the substrate, and a flexible circuit including at least one circuit layer forming power stage conductors and control circuit conductors disposed on a flexible insulating substrate layer. The power stage is between the flexible circuit and the substrate and is mounted on a first surface of the flexible circuit such that the power stage is electrically connected to the power stage conductors. The package includes a die mounted on a second surface of the flexible circuit opposite the power stage. An output of the die is electrically connected to an input of the power stage via the control circuit conductors.

Abstract: A printed circuit board includes a first insulating layer; a first wiring layer buried in the first insulating layer, exposed to one surface of the first insulating layer, and including a plurality of first wiring patterns; a second wiring layer including a plurality of second wiring patterns spaced apart from the plurality of first wiring patterns on the one surface of the first insulating layer; and a second insulating layer disposed on the one surface of the first insulating layer and covering the plurality of second wiring layers. At least a portion of the plurality of second wiring patterns on the one surface of the first insulating layer is disposed in regions between adjacent first wiring patterns among the plurality of first wiring patterns.

Abstract: A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

Abstract: Disclosed is a strip substrate including a dielectric layer that has a plurality of unit regions spaced apart from each other in a first direction and a saw line region between the unit regions, a plurality of conductive dummy patterns on corresponding unit regions of the dielectric layer, a plurality of saw line patterns on the saw line region of the dielectric layer and extending in a second direction that intersects the first direction, and a protection pattern that covers the dielectric layer. Ends of the conductive dummy patterns are spaced apart from each other in a direction parallel to the first direction. Ends of the saw line patterns are spaced apart from each other in a direction parallel to the second direction. The protection pattern is between the ends of the conductive dummy patterns and between the ends of the saw line patterns.

Abstract: A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure comprising insulative structures and electrically conductive structures vertically alternating with the insulative structures, pillar structures extending vertically through the stack structure, an etch stop material vertically overlaying the stack structure, and a first dielectric material vertically overlying the etch stop material. The method further includes removing portions of the first dielectric material, the etch stop material, and an upper region of the stack structure to form a trench interposed between horizontally neighboring groups of the pillar structures, forming a liner material within the trench, and substantially filling a remaining portion of the trench with a second dielectric material to form a dielectric barrier structure.

Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

Abstract: A planarization dielectric layer is formed over the semiconductor device on a semiconductor substrate. A device contact via structure is formed through the planarization dielectric layer. A planar dielectric spacer liner is formed over the planarization dielectric layer, and is patterned to provide an opening over the device contact via structure. An etch stop dielectric liner and a via-level dielectric layer are formed over the planar dielectric spacer liner. An interconnect via cavity may be formed through the via-level dielectric layer by a first anisotropic etch process that may be selective to the etch stop dielectric liner, and may be subsequently extended by a second anisotropic etch process that etches the etch stop dielectric liner. An interconnect via structure may be formed in the interconnect via cavity. A bottom periphery of the interconnect via structure may be self-aligned to the opening in the planar dielectric spacer liner.

Abstract: A package substrate has a dielectric layer and a redistribution metal layer. The dielectric layer has a first dielectric material and a second dielectric material. The first dielectric material is different than the second dielectric material. The second dielectric material may have a dielectric constant that is either greater than or less than the dielectric constant of the first dielectric material. The second dielectric may be selected based on a specific target application such as single-ended signal routing or serializer/deserializer (SERDES) routing.

Abstract: A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.

Abstract: The present disclosure relates to a semiconductor device including a conductive contact having a tapering profile and a method for preparing the semiconductor device. The semiconductor device includes a conductive layer disposed over a semiconductor substrate, and a conductive contact disposed over the conductive layer. The semiconductor device also includes a conductive line disposed over the conductive contact. An upper portion of the conductive contact has a tapering profile in a first cross-sectional view along a longitudinal axis of the conductive line, and the upper portion of the conductive contact has a non-tapering profile in a second cross-sectional view along a line orthogonal to the longitudinal axis of the conductive line.

Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and conductive rails laterally adjacent to the conductive structures of the stack structure. The conductive rails comprise a material composition that is different than a material composition of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

Abstract: Embodiments may relate to a semiconductor package that includes a package substrate coupled with a die. The package may further include a waveguide coupled with the first package substrate. The waveguide may include two or more layers of a dielectric material with a waveguide channel positioned between two layers of the two or more layers of the dielectric material. The waveguide channel may convey an electromagnetic signal with a frequency greater than 30 gigahertz (GHz). Other embodiments may be described or claimed.

Abstract: A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

Abstract: Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via.

Abstract: A semiconductor package may include a lower package including a first substrate, a first semiconductor chip on the first substrate, and a first molding portion on the first substrate to cover the first semiconductor chip, an interposer substrate on the first semiconductor chip, a supporting portion between the interposer substrate and the first substrate to support the interposer substrate, a connection terminal connecting the interposer substrate to the first substrate, and an upper package on the interposer substrate. The upper package may include a second substrate, a second semiconductor chip on the second substrate, and a second molding portion on the second substrate to cover the second semiconductor chip.

Abstract: A wiring substrate includes a core substrate, and a build-up part formed on the core substrate and including insulating layers and conductor layers. The conductor layers include one or more conductor layers each having a first wiring and a second wiring such that the second wiring has a conductor thickness smaller than a conductor thickness of the first wiring and that a minimum value of a line width of a wiring pattern of the second wiring is smaller than a minimum value of a line width of a wiring pattern of the first wiring.

Abstract: In one example, a semiconductor device, comprises a first redistribution layer (RDL) substrate comprising a first dielectric structure and a first conductive structure through the first dielectric structure and comprising one or more first conductive redistribution layers, an electronic component over the first RDL substrate, wherein the electronic component is coupled with the first conductive structure, a body over a top side of the first RDL substrate, wherein the electronic component is in the body, a second RDL substrate comprising a second dielectric structure over the body, and a second conductive structure through the second dielectric structure and comprising one or more second conductive redistribution layers, and an internal interconnect coupled between the first conductive structure and the second conductive structure. Other examples and related methods are also disclosed herein.

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Abstract: According to one embodiment, a semiconductor device includes a wiring board that has a first surface and a second surface opposed to the first surface, a semiconductor chip provided on the first surface, external connection terminals provided on the second surface, a sealing resin layer provided on the first surface, and a conductive shield layer that covers at least a portion of a side surface of the wiring board and the sealing resin layer. The wiring board includes a first ground wire that is electrically connected to the conductive shield layer, and a second ground wire that is electrically connected to the conductive shield layer and is electrically insulated from the first ground wire.

Abstract: In some embodiments, the present application provides a method for manufacture a memory device. The method includes forming a multilayer stack including a first magnetic layer and a first dielectric layer and forming another magnetic layer. The multilayer stack and the another magnetic layer are tailored to meet dimensions of a package structure. The package structure includes a chip having a memory cell and an insulating material enveloping the chip, where an outer surface of the package structure comprises the insulating material. The tailored multilayer stack and the tailored another magnetic layer are attached to the outer surface of the package structure.

Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.

Abstract: Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

Abstract: The present application discloses a semiconductor chip, a semiconductor device and an electrostatic discharge (ESD) protection method for a semiconductor device. The semiconductor chip includes an electrical contact, an application circuit, and an ESD protection unit. The application circuit performs operations according to a one signal received by the electrical contact. The ESD protection unit is coupled to the electrical contact. The capacitance of the ESD protection unit is adjustable.

Abstract: Described examples include an apparatus including a package substrate having a die attach pad and a first semiconductor die on the die attach pad, the first semiconductor die including a transmitter. The apparatus also includes an assembly having a first plate coupled to the transmitter, a second plate separated from the first plate by a dielectric and a second semiconductor die on the die attach pad, the second semiconductor die including a receiver coupled to the second plate.

Abstract: A semiconductor package includes a substrate and a semiconductor chip disposed over the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper ground electrode plate disposed over the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface which is surrounded by the upper ground electrode plate and is spaced apart from the upper ground electrode plate with an insulating material between the dummy power pattern and the upper ground electrode plate. A ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.

Abstract: A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

Abstract: A method of treatment of an electronic circuit including at a location at least one electrically-conductive test pad having a first exposed surface. The method includes the at least partial etching of the test pad from the first surface, and the forming on the electronic circuit of an interconnection level covering said location and including, on the side opposite to said location, a second planar surface adapted for the performing of a hybrid molecular bonding.