Abstract: A semiconductor device includes a first semiconductor fin, a first epitaxial layer, a first alloy layer and a contact plug. The first semiconductor fin is on a substrate. The first epitaxial layer is on the first semiconductor fin. The first alloy layer is on the first epitaxial layer. The first alloy layer is made of one or more Group IV elements and one or more metal elements, and the first alloy layer comprises a first sidewall and a second sidewall extending downwardly from a bottom of the first sidewall along a direction non-parallel to the first sidewall. The contact plug is in contact with the first and second sidewalls of the first alloy layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate, a source/drain contact disposed over the substrate, a first dielectric layer disposed on the source drain contact, an etch stop layer disposed on the first dielectric layer, and a source/drain conductive layer disposed in the etch stop layer and the first dielectric layer. The structure further includes a spacer structure disposed in the etch stop layer and the first dielectric layer. The spacer structure surrounds a sidewall of the source/drain conductive layer and includes a first spacer layer having a first portion and a second spacer layer adjacent the first portion of the first spacer layer. The first portion of the first spacer layer and the second spacer layer are separated by an air gap. The structure further includes a seal layer.

Abstract: A method of manufacturing a channel all-around semiconductor device includes: forming a plurality of gate structures having the same extension direction, and forming a multi-connected channel layer on a substrate. Each of the gate structures has opposite first end and second end, and the gate structures are all surrounded by the formed multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the extension direction of the gate structures, so that channels of the gate structures are connected to each other.

Abstract: A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.

Abstract: A silicon carbide semiconductor device includes a metal plate having a first main surface and a second main surface, the second main surface being opposite to the first main surface, an insulating film provided on a portion of the first main surface of the metal plate, a first conductive layer provided on the insulating film, and a silicon carbide semiconductor chip. The silicon carbide semiconductor chip includes a first electrode and a second electrode on a first surface and a third electrode on a second surface, the second surface being opposite to the first surface. The first surface of the silicon carbide semiconductor chip faces the first main surface of the metal plate, the first electrode is bonded to the first conductive layer with a first bonding material, and the second electrode is bonded to the first main surface of the metal plate with a second bonding material.

Abstract: A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.

Abstract: An electronic device includes a solid body of SiC having a surface and having a first conductivity type. A first implanted region and a second implanted region have a second conductivity type and extend into the solid body in a direction starting from the surface and delimit between them a surface portion of the solid body. A Schottky contact is on the surface and in direct contact with the surface portion. Ohmic contacts are on the surface and in direct contact with the first and second implanted regions. The solid body includes an epitaxial layer including the surface portion and a bulk portion. The surface portion houses a plurality of doped sub-regions which extend in succession one after another in the direction, are of the first conductivity type, and have a respective conductivity level higher than that of the bulk portion.

Abstract: The current disclosure describes semiconductor devices, e.g., transistors including a thin semimetal layer as a channel region over a substrate, which includes bandgap opening and exhibits semiconductor properties. Described semiconductor devices include source/drain regions that include a thicker semimetal layer over the thin semimetal layer serving as the channel region, this thicker semimetal layer exhibiting metal properties. The semimetal used for the source/drain regions include a same or similar semimetal material as the semimetal of the channel region.

Abstract: Provided is a semiconductor device comprising a semiconductor substrate, wherein the semiconductor substrate includes a hydrogen containing region including hydrogen, and the hydrogen containing region includes a high concentration region with a higher carrier concentration than a virtual carrier concentration determined based on a concentration of hydrogen included and an activation ratio of hydrogen. The semiconductor substrate includes an N type drift region, an N type emitter region that has a higher carrier concentration than that in the drift region, a P type base region, a P type collector region provided to be in contact with a lower surface of the semiconductor substrate, and an N type buffer region that is provided between the collector region and the drift region, and has a higher carrier concentration than that in the drift region, and the hydrogen containing region is included in the buffer region.

Abstract: A nanoelectric field effect sensor uses the field created by the surface charge profile of biomolecular binding to modulate the current flowing between a source and a drain. We have shown that a patterned side or top gate can be used to calibrate the biomolecular field modulation. This approach provides an electrical sensitivity characterization of the sensor before exposing it to sample fluid. Furthermore, a side gate or a top gate voltage with the right sign can be used to control the binding event during functionalization or sensing. For instance, a negative gate voltage can prevent binding of negatively charged proteins on a sensor. This approach of electric-field control of binding can be used in a differential sensor configuration as well. For instance, in a two-sensor single-bridge technique, one of the sensors can be exposed to a local electric field to prevent binding events, which can then be used for background cancellation in a second sensor, not exposed to the electric field.

Abstract: A semiconductor device includes first to fourth electrodes, a semiconductor portion, and first and second insulating films. The semiconductor portion includes first to third semiconductor layers. The second electrode is in contact with the third semiconductor layer and is spaced from the second semiconductor layer, the third semiconductor layer, and the second electrode. The first insulating film covers the third electrode. The fourth electrode is connected to the second electrode, and is spaced from the first semiconductor layer and the third electrode. The second insulating film is provided on a side surface of the fourth electrode, faces the first semiconductor layer through an air gap, and increases in thickness toward the first direction.

Abstract: A vertical gallium oxide (Ga2O3) device having a substrate, an n-type Ga2O3 drift layer on the substrate, an, n-type semiconducting channel extending from the n-type Ga2O3 drift layer, the channel being one of fin-shaped or nanowire shaped, an n-type source layer disposed on the channel; the source layer has a higher doping concentration than the channel, a first dielectric layer on the n-type Ga2O3 drift layer and on sidewalls of the n-type semiconducting channel, a conductive gate layer deposited on the first dielectric layer and insulated from the n-type source layer, n-type semiconducting channel as well as n-type Ga2O3 drift layer, a second dielectric layer deposited over the conductive gate layer, covering completely the conductive gate layer on channel sidewalls and an ohmic source contact deposited over the n-type source layer and over at least a part of the second dielectric layer; the source contact being configured not to be in electrical contact with the conductive gate layer.

Abstract: Self-aligned gate endcap architectures with gate-all-around devices having epitaxial source or drain structures are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. A gate endcap isolation structure is between the first and second gate stacks, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires and have an uppermost surface below an uppermost surface of the gate endcap isolation structure. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires and have an uppermost surface below the uppermost surface of the gate endcap isolation structure.

Abstract: According to an embodiment a semiconductor device includes a semiconductor layer including first trenches and second trenches, a first gate electrode in the first trench, a second gate electrode in the second trench, a first gate electrode pad, a second gate electrode pad, a first wiring connecting the first gate electrode pad and the first gate electrode, and a second wiring connecting the second gate electrode pad and the second gate electrode. The semiconductor layer includes a first connection trench. Two first trenches adjacent to each other are connected to each other at end portions by the first connection trench. At least one of the second trenches is provided between the two first trenches. The second gate electrode in the at least one second trench is electrically connected to the second wiring between the two first trenches.

Abstract: A semiconductor device including source/drain contacts extending into source/drain regions, below topmost surfaces of the source/drain regions, and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region.

Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, and first, second, and third semiconductor regions. The third electrode is between the first electrode and the second electrodes. The first semiconductor region includes Alx1Ga1-x1N and includes first to seventh partial regions. The fourth partial region is between the first partial region and the third partial region. The fifth partial region is between the third partial region and the second partial region. The second semiconductor region includes Alx2Ga1-x2N and includes first and second semiconductor portions. The sixth partial region is between the fourth partial region and the first semiconductor portion. The seventh partial region is between the fifth partial region and the second semiconductor portion. The third semiconductor region includes Alx3Ga1-x3N and includes a first semiconductor film part. The first semiconductor film part is between the sixth partial region and the third electrode.

Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

Abstract: Processing methods may be performed to form an airgap in a semiconductor structure. The methods may include forming a high-k material on a floor of a trench. The trench may be defined on a semiconductor substrate between sidewalls of a first material and a spacer material. The methods may include forming a gate structure on the high-k material. The gate structure may contact the first material along each sidewall of the trench. The methods may also include etching the first material. The etching may form an airgap adjacent the gate structure.

Abstract: A semiconductor device includes a substrate, two source/drain (S/D) regions over the substrate, a channel region between the two S/D regions and including a semiconductor material, a deposited capacitor material (DCM) layer over the channel region a dielectric layer over the DCM layer and a metallic gate electrode layer over the dielectric layer.

Abstract: A method for manufacturing a three-dimensional semiconductor diode device comprises providing a substrate comprising a silicon substrate and a first oxide layer formed on the silicon substrate; depositing a plurality of stacked structures on the substrate, each of the stacked structures comprising a dielectric layer and a conductive layer; etching the stacked structures through a photoresist layer which is patterned to form at least one trench in the stacked structures, a bottom of the trench exposing the first oxide layer; depositing a second oxide layer on the stacked structures and the trench; depositing a high-resistance layer on the second oxide layer, the high-resistance layer comprising a first polycrystalline silicon layer and a first conductive compound layer; and depositing a low-resistance layer on the high-resistance layer, the low-resistance layer comprising a second polycrystalline silicon layer and a second conductive compound layer.

Abstract: In accordance with an embodiment of the present invention, a method and semiconductor device is described, including forming a plurality of gaps of variable size between device features, each of the gaps including vertical sidewalls perpendicular to a substrate surface and a horizontal surface parallel to the substrate surface. Spacer material is directionally deposited concurrently on the horizontal surface in each gap and in a flat area using a total flow rate of gaseous precursors that minimizes gap-loading in a smallest gap compared to the flat area such that the spacer material is deposited on the substrate surface in each gap and in the flat area to a uniform thickness.

Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.

Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.

Abstract: An integrated circuit device includes: a fin-type active area including a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface; a nanosheet stack facing the fin top surface, the nanosheet stack including a plurality of nanosheets having vertical distances different from each other from the fin top surface; a gate structure surrounding each of the plurality of nanosheets; a source/drain region having a side wall facing at least one of the plurality of nanosheets; and an anti-punch-through semiconductor layer including a first portion filling the anti-punch-through recess, and a second portion being in contact with a side wall of a first nanosheet most adjacent to the fin-type active area among the plurality of nanosheets, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

Abstract: At least one transistor is arranged on a substrate. A collector layer and a base layer of the transistor compose a collector mesa having a substantially mesa shape and the collector mesa has side faces tilting with respect to the substrate so that the dimension of a top face in a first direction of a plane of the substrate is smaller than the dimension of a bottom face therein. A first insulating film covering the transistor is arranged on the substrate. A first-layer emitter line that extends from an area overlapped with the top face of the collector mesa to areas overlapped with at least part of the tilting side faces of the collector mesa in a plan view is arranged on the first insulating film. A second-layer emitter line and an emitter bump are arranged on the first-layer emitter line.

Abstract: A transistor and a diode are formed on a common semiconductor substrate; the semiconductor substrate has a transistor region and an outer peripheral region surrounding it; the transistor region is divided into a plurality of channel regions and a plurality of non-channel regions by a plurality of gate electrodes each having a stripe shape; each of the plurality of non-channel regions has a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fifth semiconductor layer, a first electrode, and a second electrode; the third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via a contact hole; and the fifth semiconductor layer is selectively provided not to be in contact with an impurity layer of a first conductivity type that is provided in the outer peripheral region and defines a boundary with a cell region.

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned. In some embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included in a gate stack of the transistor. In other embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included between a gate stack and a III-N channel stack of the transistor. Including doped semiconductor or fixed charge materials either in the gate stack or between the gate stack and the III-N channel stack of III-N transistors adds charges, which affects the amount of 2DEG and, therefore, affects the threshold voltages of these transistors.

Abstract: A semiconductor-on-insulator (SOI) substrate with a compliant substrate layer advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N devices (e.g., III-N HFETs) may be formed. The compliant layer may be (111) silicon, for example. The SOI substrate may further include another layer that may have one or more of lower electrical resistivity, greater thickness, or a different crystal orientation relative to the compliant substrate layer. A SOI substrate may include a (100) silicon layer advantageous for integrating Group IV devices (e.g., Si FETs), for example. To reduce parasitic coupling between an HFET and a substrate layer of relatively low electrical resistivity, one or more layers of the substrate may be removed within a region below the HFETs. Once removed, the resulting void may be backfilled with another material, or the void may be sealed, for example during back-end-of-line processing.

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

Abstract: A semiconductor device includes a semiconductor part, an first electrode, a control electrode and second electrodes. The control electrode and the second electrodes are provided between the semiconductor part and the first electrode, and provided inside trenches, respectively. The second electrodes include first to third ones. The first and second ones of the second electrodes are adjacent to each other with a portion of the semiconductor part interposed. The second electrodes each are electrically isolated from the semiconductor part by a insulating film including first and second insulating portions adjacent to each other. The first insulating portion has a first thickness. The second insulating portion has a second thickness thinner than the first thickness. The first insulating portion is provided between the first and second ones of the second electrodes. The second insulating portion is provided between the first and third ones of the second electrodes.

Abstract: Semiconductor devices include a channel fin having a top surface. A top semiconductor structure, in contact with the entire top surface of the channel fin and having a top portion and a bottom portion, with the top portion of the top semiconductor structure being narrower than the bottom portion. A restraint structure being formed over the bottom portion of the semiconductor structure.

Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.

Abstract: A high frequency transistor includes a first semiconductor layer, a first insulating film and a control electrode. The first semiconductor layer on the first insulating film extends in a first direction along an upper surface of the first insulating film. The first semiconductor layer has a first layer thickness in a second direction perpendicular to the upper surface, and a first width in a third direction orthogonal to the first direction. The first width is greater than the first layer thickness. The control electrode covers upper and side surfaces of the first semiconductor layer. The first semiconductor layer includes a first region of a first conductivity type, second and third regions of a second conductivity type. The first to third regions are arranged in the first direction. The first region is provided between the second and third region. The control electrode covers the first region.

Abstract: Some embodiments include a ferroelectric transistor having a first electrode and a second electrode. The second electrode is offset from the first electrode by an active region. A transistor gate is along a portion of the active region. The active region includes a first source/drain region adjacent the first electrode, a second source/drain region adjacent the second electrode, and a body region between the first and second source/drain regions. The body region includes a gated channel region adjacent the transistor gate. The active region includes at least one barrier between the second electrode and the gated channel region which is permeable to electrons but not to holes. Ferroelectric material is between the transistor gate and the gated channel region.

Abstract: An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.

Abstract: Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.

Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.

Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.

Abstract: A SiC Schottky rectifier with surge current ruggedness is described. The Schottky rectifier includes one or more multi-layer bodies that provide multiple types of surge current protection.

Abstract: A thin-film solar module with a substrate and a layer structure applied thereon, which comprises a rear electrode layer, a front electrode layer, and an absorber layer arranged between the rear electrode layer and the front electrode layer, wherein serially connected solar cells are formed in the layer structure by patterning zones, wherein at least one solar cell has one or more optically transparent zones that are in each case rear-electrode-layer-free, wherein the one or more optically transparent zones are implemented such that the rear electrode layer of the solar cell is continuous.

Abstract: A solar module and a method for fabricating a solar module comprising a plurality of rear contact solar cells are described. Rear contact solar cells (1) are provided with a large size of e.g. 156×156 mm2. Soldering pad arrangements (13, 15) applied on emitter contacts (5) and base contacts (7) are provided with one or more soldering pads (9, 11) arranged linearly. The soldering pad arrangements (13, 15) are arranged asymmetrically with respect to a longitudinal axis (17). Each solar cell (1) is then separated into first and second cell portions (19, 21) along a line (23) perpendicular to the longitudinal axis (17).

Abstract: A multijunction solar cell including an upper first solar subcell having a first band gap and positioned for receiving an incoming light beam; a second solar subcell disposed below and adjacent to and lattice matched with said upper first solar subcell, and having a second band gap smaller than said first band gap; wherein at least one of the solar subcells has a graded band gap throughout the thickness of at least a portion of the active layer.

Abstract: Provided is an infrared detecting device with a high SNR. The infrared detecting device includes: a semiconductor substrate 10; a first layer 21 having a first conductivity type on the semiconductor substrate; a light receiving layer 22 on the first layer; and a second layer 23 having a second conductivity type on the light receiving layer. A part of the first layer, the light receiving layer, and the second layer form a mesa structure, the light receiving layer contains AlxIn1-xSb (0.05<x<0.18), and at least a part of side surfaces of the mesa structure are covered with a protective layer, and part of the protective layer that is in contact with side surfaces of the light receiving layer is made of silicon nitride.

Abstract: Shockley-Read-Hall (SRH) generation and/or recombination in heterojunction devices is suppressed by unconventional doping at or near the heterointerface. The effect of this doping is to shift SRH generation and/or recombination preferentially into the wider band gap material of the heterojunction. This reduces total SRH generation and/or recombination in the device by decreasing the intrinsic carrier concentration ni at locations where most of the SRH generation and/or recombination occurs. The physical basis for this effect is that the SRH generation and/or recombination rate tends to decrease as ni around the depletion region decreases, so decreasing the effective ni in this manner is a way to decrease SRH recombination.

Abstract: A display may include a color filter layer, a liquid crystal layer, and a thin-film transistor layer. A camera window may be formed in the display to accommodate a camera. The camera window may be formed by creating a notch in the thin-film transistor layer that extends inwardly from the edge of the thin-film transistor layer. The notch may be formed by scribing the thin-film transistor layer around the notch location and breaking away a portion of the thin-film transistor layer. A camera window may also be formed by grinding a hole in the display. The hole may penetrate partway into the thin-film transistor layer, may penetrate through the transistor layer but not into the color filter layer, or may pass through the thin-film transistor layer and partly into the color filter layer.

Abstract: A light emitting diode (LED) transfer system includes an alignment apparatus configured to align a plurality of target substrates; a handling robot configured to transport the plurality of target substrates; a transfer stage configured to hold the plurality of target substrates and move the plurality of target substrates; a substrate stage configured to move a relay substrate having a plurality of LEDs with respect to the transfer stage while the plurality of LEDs are facing the transfer stage; a laser configured to emit a laser beam toward the plurality of LEDs of the relay substrate so that the plurality of LEDs are transferred from the relay substrate to the plurality of target substrates; and a processor configured to control the alignment apparatus, the handling robot, the transfer stage, the substrate stage, and the laser to transfer the plurality of LEDs of the relay substrate to the plurality of target substrates.

Abstract: A display device includes a plurality of semiconductor light emitting diodes, first and second electrodes respectively extending from the plurality of semiconductor light emitting diodes to supply an electrical signal to the plurality of semiconductor light emitting diodes, a plurality of pair electrodes disposed on a substrate and having a first electrode and a second electrode, a dielectric layer disposed on the plurality of pair electrodes, and a chemical bond layer disposed between the dielectric layer and the plurality of semiconductor light emitting diodes and forming a covalent bond with the dielectric layer and each of the plurality of semiconductor light emitting diodes. The chemical bond layer bonds the semiconductor light emitting diodes to the dielectric layer when a voltage applied to the plurality of pair electrodes is cut off after the plurality of semiconductor light emitting diodes are assembled on the dielectric layer.