Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a word line (WL) structure, wherein the substrate includes trenches arranged in parallel intervals; the WL structure is located in the trenches, and includes a dielectric layer and a conductive layer; the dielectric layer covers a bottom surface and a sidewall of the conductive layer; the conductive layer includes a first conductive layer and a second conductive layer; and a first component is doped in the second conductive layer.

Abstract: A semiconductor device includes: a trench formed in a substrate; a gate dielectric layer covering sidewalls and a bottom surface of the trench; a first gate electrode gap-filling a bottom portion of the trench over the gate dielectric layer; a second gate electrode including a metal nitride which is the same as the first gate electrode over the first gate electrode and doped with a low work function adjusting element; a buffer layer covering a top surface of the second gate electrode and the gate dielectric layer exposed over second gate electrode; and a capping layer gap-filling the other portion of the trench over the buffer layer.

Abstract: An embodiment of the present invention provides a semiconductor device capable of improving gate induced drain leakage and a method for fabricating the same, According to an embodiment of the present invention, a semiconductor device comprises a substrate including a trench; a gate insulating layer covering a bottom surface and a sidewall of the trench; and a gate electrode structure and a capping layer sequentially stacked on the gate insulating layer and filling the trench, wherein the gate electrode structure includes: a first gate electrode including a metal nitride; a second gate electrode formed over the first gate electrode, having the same metal nitride as the first gate electrode, and having a lower work function than that of the first gate electrode; and a third gate electrode formed over the second gate electrode, having a thickness smaller than that of the second gate electrode, and including a non-metal material.

Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.

Abstract: A manufacturing method of a semiconductor structure includes: forming a semiconductor layer between bit lines; patterning the semiconductor layer to form a plurality of cell contacts and trenches, wherein two of the cell contacts are separated by one of the trenches; and forming an isolation layer in the trenches. The semiconductor layer is formed between the bit lines such that no sacrificial layer is formed between the bit lines. A process of forming the sacrificial layer may be omitted.

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

Abstract: A semiconductor memory device including an array region and a peripheral region surrounding the array region. The array region includes a plurality of active regions and a first insulating layer disposed between the active regions. The peripheral region includes a peripheral structure, a second insulating layer surrounding the peripheral structure, and a third insulating layer surrounding the second insulating layer. At least a buried word line extends through the array region and the peripheral region, wherein a portion of the buried word line through the second insulating layer comprises a neck profile from a plan view.

Abstract: Provided herein may be a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a peripheral circuit structure formed on a substrate including a cell region and a contact region, a cell stacked body formed over the peripheral circuit structure to overlap the cell region, a dummy stacked body formed over the peripheral circuit structure to overlap the contact region, a pillar structure configured to penetrate the cell stacked body, an etch stop layer located over the peripheral circuit structure and overlapping with a bottom surface of the pillar structure, a cutting structure penetrating the pillar structure in a vertical direction and contacting the etch stop layer, and a contact plug penetrating the dummy stacked body and extending to the peripheral circuit structure.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a source stack, a capacitor electrode including a metal layer buried in the source stack, a stack including first insulating layers and second insulating layers alternately stacked on the source stack, and a contact plug passing through the stack and extending to be connected to the metal layer.

Abstract: A semiconductor device includes a substrate and a transistor. The transistor has a first diffusion region and a second diffusion region provided in the substrate, a gate insulating film provided over the substrate between the first diffusion region and the second diffusion region, and a gate electrode positioned on the gate insulating film. The semiconductor device further includes an internal layer positioned in the substrate, wherein the internal layer has a first concentration of germanium and carbon higher than a second concentration of germanium and carbon of a region between the first diffusion region and the second diffusion region.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a first circuit that includes a level shift transistor, a transmission line through which the signal output from the first circuit propagates, a second circuit that is connected the transmission line to receive the signal propagating through the transmission line, and a third circuit that is connected to the transmission line. The first circuit is connected to a power supply line to which a first voltage is supplied, and outputs, to the transmission line, a signal having an amplitude lower than the first voltage by a threshold voltage of the level shift transistor. The third circuit allows a current to flow from the transmission line when a voltage of the transmission line exceeds a set voltage.

Abstract: A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first film including electrode layers and insulating layers alternately stacked on the substrate, and a plurality of insulating films in the first film. The insulating films extend in a first direction parallel to a surface of the substrate and spaced from one another in a second direction parallel to the surface of the substrate. The semiconductor device further includes a semiconductor layer provided in at least one of the insulating films and first and second charge accumulation units between the semiconductor layer and one of the electrode layers. The insulating films include a first insulating film having a first width in the second direction and a second insulating film having a second width in the second direction that is greater than the first width.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of insulating layers, the electrode layers and the insulating layers being alternately stacked, and a memory film extending in a stacking direction in the stacked body. The memory film includes an oxide film facing the insulating layers, a block insulating film facing the electrode layers and the oxide film, and a charge storage film facing the block insulating film. The block insulating film has a larger thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers, and the charge storage film has a smaller thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers.

Abstract: There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes a stack structure including a contact region with a stepped structure, a stepped groove having a sidewall formed of the stepped structure of the stack structure, a barrier insulating layer extending along a surface of the stepped structure, a filling insulating layer formed on the barrier insulating layer inside the stepped groove, and a conductive gate contact penetrating the stepped structure of the stack structure while penetrating the filling insulating layer and the barrier insulating layer.

Abstract: A three dimensional semiconductor device includes first, second, third and fourth source/drain patterns sequentially stacked on a substrate, a contact structure on the first to fourth source/drain patterns and a contact line on the contact structure. The contact structure includes a first active contact on the first source/drain pattern, a second active contact on the second source/drain pattern, a third active contact on the third source/drain pattern, and a fourth active contact on the fourth source/drain pattern. A first vertical extension part of the first active contact is adjacent to one side of the contact structure, and a second vertical extension part of the second active contact is adjacent to the other side of the contact structure. A third vertical extension part of the third active contact is disposed between the first and second vertical extension parts and is closer to the first vertical extension part.

Abstract: A method of manufacturing a semiconductor device includes forming a molded structure by stacking interlayer insulating layers alternately with sacrificial layers on a plate layer, forming channel holes passing through the molded structure, forming channel layers doped with non-conductive impurities in the channel holes, forming a metal layer above the channel holes, forming metal silicide layers on upper ends of the channel layers using the metal layer, crystallizing the channel layers using the metal silicide layers by performing a heat treatment process at a temperature of 800 degrees or more, forming openings penetrating through the molded structure and extending in one direction, removing the sacrificial layers exposed through the openings, and forming gate electrodes, by filling regions from which the sacrificial layers have been removed, with a conductive material. After the crystallizing, the metal silicide layers are located lower than a lowermost gate electrode among the gate electrodes.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

Abstract: A three-dimensional (3D) memory device includes a memory stack including interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack, a memory block including a plurality of channel structures extending vertically through the memory stack, a plurality of source structures extending vertically and laterally in the memory stack and being in contact with the memory block, and a plurality of conductor portions and a plurality of insulating portions being interleaved and locating between two adjacent source structures along a direction which the source structure extends. The interleaved plurality of conductor portions and plurality of insulating portions are each in contact with corresponding conductor layers and corresponding insulating layers of the same level from adjacent memory blocks.

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.

Abstract: A method for fabricating a semiconductor device includes: forming a first multi-layer stack including liner layers and a source sacrificial layer over a lower structure; forming a second multi-layer stack including dielectric layers and sacrificial layers over the first multi-layer stack; forming a vertical contact recess extending through the second multi-layer stack and the source sacrificial layer; replacing the source sacrificial layer with a source contact layer; forming a carbon-containing spacer on sidewall of the vertical contact recess; replacing the sacrificial layers with conductive layers; and forming a source contact plug in the vertical contact recess.

Abstract: A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.

Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.

Abstract: A manufacturing method for a nonvolatile charge-trapping memory apparatus is provided. During the manufacturing process of the nonvolatile memory apparatus, a blocking layer of a storage device is effectively protected. Consequently, the blocking layer is not contaminated or thinned. Moreover, since the well regions of the logic device area and the memory device area are not simultaneously fabricated, it is feasible to fabricate small-sized nonvolatile memory cell in the memory device area and precisely control the threshold voltage of the charge trapping transistor.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of conductive layers, each of the plurality of conductive layers including a first portion, and a second portion that is thicker than the first portion, a first insulator portion that contacts the second portion of a first conductive layer and the second portion of a second conductive layer, and a second insulator portion that contacts the second portion of a third conductive layer, wherein the second portion of the second conductive layer includes a first sub portion arranged with the second portion of the first conductive layer, and a second sub portion provided between the second portion of the first conductive layer and the second portion of the third conductive layer.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a stacked film alternately including first layers and second layers in a first direction, forming a hole extending in the first direction in the stacked film, and forming a first insulator on a side face of the stacked film in the hole. The method further includes removing the first insulator in the hole to expose a first part of the side face of the stacked film at a predetermined height in the first direction of the hole and to expose a side face of the first insulator remaining on a second part of the side face of the stacked film at the predetermined height. The method further includes forming a second insulator on the first part of the side face of the stacked film and the side face of the remaining first insulator in the hole.

Abstract: A semiconductor storage device includes a semiconductor substrate including a first region, a second region, and a third region, located apart from each other in such an order in a first direction in an element region. Each of the first to third regions including a source and/or drain region. The semiconductor storage device further includes a first conductor layer provided above the element region and having a first opening; a second conductor layer provided above the element region, having a second opening, and located apart from the first conductor layer in the first direction; a first contact, in the first opening, that is connected to the first region; a second contact, in the second opening, that is connected to the third region; a first memory cell connected to the first contact; and a second memory cell connected to the second contact.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first transistor, a second transistor, a first insulating portion, and a second insulating portion. The first transistor includes a first diffusion region and a second diffusion region, a first gate insulating film, and a first gate electrode. The second transistor includes a third diffusion region and a fourth diffusion region, a second gate insulating film, and a second gate electrode. The first insulating portion is positioned between the first gate electrode and the second gate electrode. The second insulating portion covers the first transistor, the second transistor, and the first insulating portion from a side opposite to the substrate. The first insulating portion and the second insulating portion are formed of different materials.

Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit and a first bonding pad, the first bonding pad connected to the peripheral circuit, a cell structure on the peripheral circuit structure, the cell structure including a second bonding pad bonded to the first bonding pad, and a pad structure on the cell structure. The cell structure includes a cell substrate having a first face, a second face opposite to the first face, a first contact plug extending through the cell substrate and connected to an electrode layer, and a second contact plug extending through the cell substrate and connected to the cell substrate. Each of the first contact plug and the second contact plug is connected to the pad structure, and a bypass via is in contact with the pad structure on the second face.

Abstract: A three-dimensional non-volatile memory device includes a memory cell array including a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction on a substrate. The first lateral direction and the second lateral direction are parallel to a main surface of the substrate and perpendicular to each other, and the vertical direction is perpendicular to the main surface of the substrate. The memory cell array includes a plurality of horizontal channel regions and a vertical word line. The plurality of horizontal channel regions extend in the first lateral direction on the substrate. The plurality of horizontal channel regions overlap each other and are apart from each other in the vertical direction. The vertical word line passes through the plurality of horizontal channel regions in the vertical direction.

Abstract: Disclosed is a three-dimensional flash memory using a ferroelectric layer on the basis of a back gate structure.

Abstract: The present disclosure relates to an integrated chip including a ferroelectric layer. The ferroelectric layer includes a ferroelectric material. A first relaxation layer including a first material, different from the ferroelectric material, is on a first side of the ferroelectric layer. A second relaxation layer including a second material, different from the ferroelectric material, is on a second side of the ferroelectric layer, opposite the first side. A Young’s modulus of the first relaxation layer is less than a Young’s modulus of the ferroelectric layer.

Abstract: A device structure according to the present disclosure includes a conductive feature disposed in a first dielectric layer, a ferroelectric tunnel junction (FTJ) stack disposed over the conductive feature, a spacer disposed along sidewalls of the FTJ stack, a second dielectric layer disposed over the spacer and the FTJ stack, a second dielectric layer disposed over the spacer and the FTJ stack, and a contact via extending through the second dielectric layer. The FTJ stack includes a bottom electrode layer electrically coupled to the conductive feature, a ferroelectric layer over the bottom electrode layer, and a top electrode layer on the ferroelectric layer. The top electrode layer is formed of a conductive metal oxide.

Abstract: A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.

Abstract: Methods, systems, and devices for deck selection layouts in a memory device are described. In some implementations, a tile of a memory array may be associated with a level above a substrate, and may include a set of memory cells, a set of digit lines, and a set of word lines. Selection transistors associated with a tile of memory cells may be operable for coupling digit lines of the tile with circuitry outside the tile, and may be activated by various configurations of one or more access lines, where the various configurations may be implemented to trade off or otherwise support design and performance characteristics such as power consumption, layout complexity, operational complexity, and other characteristics. Such techniques may be implemented for other aspects of tile operations, including memory cell shunting or equalization, tile selection using transistors of a different level, or signal development, or various combinations thereof.

Abstract: Selector material layers are formed over the first electrically conductive lines, and magnetic tunnel junction material layers are formed over the selector material layers. The magnetic tunnel junction material layers are patterned into a two-dimensional array of magnetic tunnel junction (MTJ) pillar structures. A dielectric spacer material layer is deposited over the two-dimensional array of MTJ pillar structures. The dielectric spacer material layer and the selector material layers are anisotropically etched. Patterned portions of the selector material layers include a two-dimensional array of selector-containing pillar structures. Second electrically conductive lines are formed over the two-dimensional array of MTJ pillar structures.

Abstract: According to one embodiment, a magnetic memory device includes a plurality of memory cells each including a magnetoresistance effect element and a switching element provided on a lower layer side of the magnetoresistance effect element and connected in series to the magnetoresistance effect element. The switching element includes a bottom electrode, a top electrode and a switching material layer provided between the bottom electrode and the top electrode, and the top electrode includes a first portion formed of a first material and a second portion provided on a lower layer side of the first portion and formed of a second material different from the first material.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing the semiconductor structure provided by the present disclosure includes: providing a substrate; forming a base pattern on the substrate, where the base pattern includes a plurality of bit lines arranged in parallel, and an isolation structure is disposed between adjacent two of the bit lines; forming a plurality of semiconductor pillars arranged in a direction of the bit line on a surface of each of the bit lines, where the bit line is electrically connected to the semiconductor pillar; forming a gate-all-around structure on a surface of the semiconductor pillar, where the gate-all-around structure includes a first insulating layer, a gate structure layer, and a second insulating layer that are sequentially disposed on a side surface of the semiconductor pillar.

Abstract: A memory device includes two word-line electrodes, two source-line electrodes, and two data storage features for use by four memory cells, which are referred to as first, second, third and fourth memory cells. One word-line electrode is common to the first and second memory cells, and the other word-line electrode is common to the third and fourth memory cells. One source-line electrode is common to the first and second memory cells, and the other source-line electrode is common to the third and fourth memory cells. One data storage feature is common to the first and third memory cells, and the other data storage feature is common to the second and fourth memory cells.

Abstract: A semiconductor device according to an embodiment of the present disclosure includes a substrate, a gate electrode layer disposed over the substrate, a gate dielectric layer disposed on the gate electrode layer, a channel electrode layer disposed on the gate dielectric layer, a threshold switching layer disposed on the channel electrode layer, and a source electrode layer and a drain electrode layer that are disposed on the threshold switching layer to be spaced apart from each other.

Abstract: A high efficiency embedded-artificial synaptic element includes a semiconductor substrate, a select transistor, a metal layer, a first memory transistor and a second memory transistor. The select transistor is disposed on the semiconductor substrate and includes a select gate structure, a drain region and a source region. The metal layer is connected to the drain region. The first memory transistor includes a first gate structure, a first electrode region and a first memristor. The second memory transistor includes a second gate structure, a second electrode region and a second memristor. The second electrode region and the first electrode region are connected to each other and form a connection region, which is connected to the metal layer. The first memristor is formed between the first gate structure and the connection region, and the second memristor is formed between the second gate structure and the connection region.

Abstract: Heat resistance is improved. A photoelectric conversion element 10 includes an anode 12, a cathode 16, and an active layer 14 provided between the anode and the cathode, in which the active layer contains at least one p-type semiconductor material and at least two n-type semiconductor materials, and a dispersive energy Hansen solubility parameter ?D(P) of the at least one p-type semiconductor material and a first dispersive energy Hansen solubility parameter ?D(Ni) and a second dispersive energy Hansen solubility parameter ?D(Nii) of the at least two n-type semiconductor materials satisfy the following requirements (i) and (ii): 2.1 MPa0.5<|?D(P)??D(Ni)|+|?D(Ni)??D(Nii)|<4.0 MPa0.5??Requirement (i): 0.8 MPa0.5<|?D(P)??D(Ni)| and 0.2 MPa0.

Abstract: According to one embodiment, a detector includes an element portion. The element portion includes a first detection portion and a wiring portion. The first detection portion includes a first electrode, a first counter electrode, and a first organic semiconductor layer. At least a part of the first organic semiconductor layer is between the first electrode and the first counter electrode. The wiring part includes a first electrode layer electrically connected with the first electrode, a first counter electrode layer electrically connected with the first counter electrode, and a first conductive layer. The first counter electrode layer is between the first electrode layer and the first detection portion in a first direction from the first electrode layer to the first counter electrode layer. The first conductive layer is between the first electrode layer and the first counter electrode layer in the first direction.

Abstract: A solid-state imaging apparatus includes a pixel array part in which a plurality of pixels are two-dimensionally arranged, in which each pixel has a first photoelectric conversion region formed above a semiconductor layer, a second photoelectric conversion region formed in the semiconductor layer, a first filter configured to transmit a light in a predetermined wavelength region corresponding to a color component, and a second filter having different transmission characteristics from the first filter, one photoelectric conversion region out of the first photoelectric conversion region and the second photoelectric conversion region photoelectrically converts a light in a visible light region, the other photoelectric conversion region photoelectrically converts a light in an infrared region, the first filter is formed above the first photoelectric conversion region, and the second filter has transmission characteristics of making wavelengths of lights in an infrared region absorbed in the other photoelectric co

Abstract: A light-emitting device that emits green light includes a first electrode and a second electrode that are arranged in sequence, and a light-emitting layer disposed between the first electrode and the second electrode, the light-emitting layer includes a first host material and a second host material; the first host material and the second host material form an exciplex, a difference between a lowest unoccupied molecular orbital (LUMO) energy level of the first host material and a LUMO energy level of the second host material is greater than or equal to 0.5 eV, under a same test condition, a difference between an order of magnitude of a hole mobility of the first host material and an order of magnitude of an electron mobility of the second host material is greater than or equal to 1.

Abstract: A light-emitting element according to an aspect of the disclosure, comprising: a first electrode; a second electrode; a light-emitting layer disposed between the first electrode and the second electrode: and a charge transport layer disposed between the first electrode and the light-emitting layer. The charge transport layer includes a first layer and a second layer closer to the first electrode relative to the first laver. The first layer and the second layer include nanoparticles containing an identical semiconductor A particle size of the nanoparticle of the second layer is larger than a particle size of the nanoparticle of the first layer.

Abstract: High performance OLED that includes deuterated compounds in the emissive layer are disclosed. The OLED includes an anode; a cathode; and an emissive layer, disposed between the anode and the cathode. In the OLED, the emissive layer includes a first phosphorescent emitter and a first host; the first phosphorescent emitter is a metal complex; the first host is partially or fully deuterated; and at least one additional condition is true.

Abstract: A light-emitting element includes the following: a cathode; an anode; a light-emitting layer provided between the cathode and the anode; an electron transport layer provided between the cathode and the light-emitting layer; and a potential well provided between the cathode and the light-emitting layer, and being a region having a larger electron affinity than a surrounding region.

Abstract: An electron transport layer of a display device includes a mixture in which a first material and a second material are mixed, an electron affinity of a first light-emitting layer is equal to or smaller than an electron affinity of the first material, an electron affinity of the second material is smaller than the electron affinity of the first material, and an electron affinity of a second light-emitting layer is equal to or smaller than the electron affinity of the second material.

Abstract: A method of increasing light emission efficiency in an organic light emitting diode (OLED) eliminates or reduces at least one waveguide mode selected from the group consisting of: transverse electric (TE0) mode, transverse magnetic (TM1) mode, and combinations thereof by disposing an ultrathin electrically conductive transparent metallic electrode having a first polarity within the OLED. The OLED has a transparent substrate on which the ultrathin electrically conductive transparent metallic electrode is disposed. It also has an emissive active assembly for generating photons defining first and second opposite sides. A conductive transparent metallic electrode is disposed along the first side. A second transparent electrode having a second polarity opposite to the first polarity disposed adjacent to the second side of emissive active assembly. The methods include increasing an external quantum efficiency of the organic light emitting diode to ?about 20%. OLEDs with such a design are also contemplated.