Patents Issued in February 20, 2024
  • Patent number: 11908484
    Abstract: An apparatus for generating an enhanced signal from an input signal, wherein the enhanced signal has spectral values for an enhancement spectral region, the spectral values for the enhancement spectral regions not being contained in the input signal, includes a mapper for mapping a source spectral region of the input signal to a target region in the enhancement spectral region, the source spectral region including a noise-filling region; and a noise filler configured for generating first noise values for the noise-filling region in the source spectral region of the input signal and for generating second noise values for a noise region in the target region, wherein the second noise values are decorrelated from the first noise values or for generating second noise values for a noise region in the target region, wherein the second noise values are decorrelated from first noise values in the source region.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: February 20, 2024
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Sascha Disch, Ralf Geiger, Andreas Niedermeier, Matthias Neusinger, Konstantin Schmidt, Stephan Wilde, Benjamin Schubert, Christian Neukam
  • Patent number: 11908485
    Abstract: An apparatus for selecting one of a first encoding algorithm having a first characteristic and a second encoding algorithm having a second characteristic for encoding a portion of an audio signal to obtain an encoded version of the portion of the audio signal has a first estimator for estimating a first quality measure for the portion of the audio signal, which is associated with the first encoding algorithm, without actually encoding and decoding the portion of the audio signal using the first encoding algorithm. A second estimator is provided for estimating a second quality measure for the portion of the audio signal, which is associated with the second encoding algorithm, without actually encoding and decoding the portion of the audio signal using the second encoding algorithm. The apparatus has a controller for selecting the first or second encoding algorithms based on a comparison between the first and second quality measures.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: February 20, 2024
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Emmanuel Ravelli, Stefan Doehla, Guillaume Fuchs, Eleni Fotopoulou, Christian Helmrich
  • Patent number: 11908486
    Abstract: A method for decoding an encoded audio bitstream is disclosed. The method includes receiving the encoded audio bitstream and decoding the audio data to generate a decoded lowband audio signal. The method further includes extracting high frequency reconstruction metadata and filtering the decoded lowband audio signal with an analysis filterbank to generate a filtered lowband audio signal. The method also includes extracting a flag indicating whether either spectral translation or harmonic transposition is to be performed on the audio data and regenerating a highband portion of the audio signal using the filtered lowband audio signal and the high frequency reconstruction metadata in accordance with the flag. The high frequency regeneration is performed as a post-processing operation with a delay of 3010 samples per audio channel.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: February 20, 2024
    Assignee: DOLBY INTERNATIONAL AB
    Inventors: Kristofer Kjoerling, Lars Villemoes, Heiko Purnhagen, Per Ekstrand
  • Patent number: 11908487
    Abstract: A signal processing apparatus according an embodiment includes an acquisition unit and an application unit. The acquisition unit acquires M detection signals output from M detector devices having N-fold symmetry (M is an integer equal to or greater than 2, and N is an integer equal to or greater than 2). Each of the M detector devices detects original signals generated from K signal sources (K is an integer equal to or greater than 2) having the N-fold symmetry. The application unit applies a trained neural network to M input vectors corresponding to the M detection signals and outputs K output vectors. The same parameter is set to, of multiple weights included in a weight matrix of the trained neural network, weights that are commutative based on the N-fold symmetry.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 20, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takehiko Kagoshima, Daichi Hayakawa
  • Patent number: 11908488
    Abstract: A computing device translates a spoken word into a corresponding ordered set of spoken phonemes and analyzes correctness of the spoken word relative to a target word. The analyzing includes attempting to locate each of the spoken phonemes in an ordered set of grapheme-phoneme correspondences (GPCs) describing the target word, and determining whether or not the ordered set of spoken phonemes comprises a same number of phonemes as in the ordered set of GPCs. The analyzing also includes comparing the order of the ordered set of spoken phonemes against the order of the ordered set of GPCs. The computing device generates a report, based on the analyzing, that identifies at least one of the GPCs in the ordered set of GPCs as having been incorrectly applied in decoding the target word.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 20, 2024
    Assignee: METAMETRICS, INC.
    Inventor: Neena Marie Saha
  • Patent number: 11908489
    Abstract: Systems and methods are provided for advancing through video content. The systems and methods include generating playback of a video associated with subtitles comprising a sequence of subtitle segments; receiving a user request to advance playback of the video from a first video play position corresponding to a first subtitle segment of the sequence of subtitle segments; identifying a second subtitle segment of the sequence of subtitle segments that is adjacent to the first subtitle segment in the sequence of subtitle segments; and in response to receiving the user request to advance playback of the video, advancing playback of the video from the first video play position to a second video play position based on a subtitle segment play position associated with the second subtitle segment.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: February 20, 2024
    Assignee: Snap Inc.
    Inventor: David Paliwoda
  • Patent number: 11908490
    Abstract: A video recording method and device, an electronic device and a storage medium are provided. The method includes: acquiring speed varying information of a speed-varied video, where the speed varying information is used to represent a playing speed change of the speed-varied video; performing reverse speed-varying processing on the speed-varied video according to the speed varying information to obtain an original speed video; displaying the original speed video, and synchronously performing video shooting to generate an original speed target video; and performing speed varying processing on the original speed target video according to the speed varying information to obtain a target speed-varied video.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: February 20, 2024
    Assignee: BEIJING BYTEDANCE NETWORK TECHNOLOGY CO., LTD.
    Inventor: Siyu He
  • Patent number: 11908491
    Abstract: Aspects of the present application correspond to generation of supplemental content based on processing information associated with content to be rendered. More specifically, aspects of the present application correspond to the generation of audio track information, such as music tracks, that are created for playback during the presentation of video content. Illustratively, one or more frames of the video content are processed by machine learned algorithm(s) to generate processing results indicative of one or more attributes characterizing individual frames of video content. A selection system can then identify potential music track or other audio data in view of the processing results.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: February 20, 2024
    Assignee: XDMIND INC.
    Inventors: Linda Bernardi, Ara Bernardi
  • Patent number: 11908492
    Abstract: A decoding method of a video stream, which is encoded video information. The video stream includes a base video stream, and an enhanced video stream, which is a video stream to enhance luminance of the base video stream, and a describer that contains the combination information of the base video stream and the enhanced video stream. The decoding method includes acquiring the describer, and identifying the combination of the base video steam and the enhanced video stream. The decoding method also includes generating base video information by decoding the base video stream, generating enhanced video information by decoding the enhanced video stream, generating decoded video information based on the base video stream and the enhanced video stream, and outputting the decoded video information.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: February 20, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Hiroshi Yahata, Tadamasa Toma, Tomoki Ogawa
  • Patent number: 11908493
    Abstract: An example system may provide a graphical user interface displaying a timeline graphical element, where the timeline graphical element represents a timeline of a media clip, and a graphical current point indicator indicating a selected point on the timeline. The system may provide a marking graphical element that is selectable to record a start point or an end point of a segment of the certain media clip. The system may receive a first user input scrubbing the timeline graphical element horizontally, and it may receive a second user input indicating a user interaction with the marking graphical element. The system may determine a start point and an end point of each of a plurality of segments of the timeline graphical element corresponding to the certain media clip based on the second user input and update the graphical user interface based on the determination.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: February 20, 2024
    Assignee: Instasize, In
    Inventors: Hector Raul Lopez, John William Fabela
  • Patent number: 11908494
    Abstract: An apparatus comprises at least one processing device comprising a processor coupled to a memory and a drive bay enclosure of a storage system comprising a housing with one or more drive bays, the housing of the drive bay enclosure comprising one or more status indicators proximate an opening for at least a given one of the one or more drive bays. The at least one processing device is configured to perform steps of determining status information for the given drive bay, and controlling the one or more status indicators proximate the opening for the given drive bay based at least in part on the determined status information.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: February 20, 2024
    Assignee: Dell Products L.P.
    Inventors: Zhuo Zhang, Xiangdong Huang, Changlin Li, Yan Sun
  • Patent number: 11908495
    Abstract: Disclosed herein is an electronic device that includes a pedestal that extends from a mounting surface of a base of the electronic device. The electronic device also includes a thermal interface material that is interposed between an interface surface of the pedestal and a data processing component, is in direct contact with the data processing component, and is in direct contact with a first portion and a second portion of the interface surface. The first portion of the interface surface of the pedestal has a first height, relative to the mounting surface of the base, and the second portion of the interface surface of the pedestal has a second height, relative to the mounting surface of the base and different than the first height.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: February 20, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Bo Yang, Yuhang Yang, Ning Ye
  • Patent number: 11908496
    Abstract: The present disclosure generally relate to spin-orbit torque (SOT) devices comprising a topological insulator (TI) modulation layer. The TI modulation layer comprises a plurality of bismuth or bismuth-rich composition modulation layers, a plurality of TI lamellae layers comprising BiSb having a (012) crystal orientation, and a plurality of texturing layers. The TI lamellae layers comprise dopants or clusters of atoms, the clusters of atoms comprising a carbide, a nitride, an oxide, or a composite ceramic material. The clusters of atoms are configured to have a grain boundary glass forming temperature of less than about 400° C. Doping the TI lamellae layers comprising BiSb having a (012) crystal orientation with clusters of atoms comprising a carbide, a nitride, an oxide, or a composite ceramic material enable the SOT MTJ device to operate at higher temperatures while inhibiting migration of Sb from the BiSb of the TI lamellae layers.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Quang Le, Brian R. York, Cherngye Hwang, Susumu Okamura, Xiaoyong Liu, Kuok San Ho, Hisashi Takano
  • Patent number: 11908497
    Abstract: A hard disk drive flexure assembly includes a base layer, a conductive layer, a plurality of electrical pads over the conductive layer, and a sidewall layer including sidewalls on each side of and extending higher than a corresponding electrical pad. Pre-solder bumps are formed between the sidewalls and over each pad. Use of sidewalls prevents the pre-solder bumps from undesirably bridging to an adjacent electrical pad and forming a short circuit, which might otherwise cause head-gimbal assembly (HGA) manufacturing failures and consequent increased cost. These techniques are especially relevant with narrow, high-density, small pitch electrical pads.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Irizo Naniwa, Kenichi Murata
  • Patent number: 11908498
    Abstract: A first straight line region and a second straight line region of the straight line region pair are inclined in opposite directions with respect to a first imaginary straight line. The first straight line region has a steeper inclined angle with respect to the first imaginary straight line than the second straight line region. Positions of both ends of the first straight line region and positions of both ends of the second straight line region are aligned in a direction corresponding to a width direction of a magnetic tape. A plurality of gap patterns deviate from each other by a predetermined interval in a direction corresponding to a longitudinal direction of the magnetic tape, between the gap patterns adjacent to each other along the direction corresponding to the width direction of the magnetic tape. A substrate is inclined with respect to the first imaginary straight line.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: February 20, 2024
    Assignee: FUJIFILM CORPORATION
    Inventors: Toru Nakao, Tetsuya Kaneko, Yoichi Akano
  • Patent number: 11908499
    Abstract: A heat-assisted magnetic recording head includes a laser, a near-field transducer, a primary waveguide, a secondary waveguide, and a photodiode. The laser is configured to emit electromagnetic radiation. The near-field transducer is configured to focus and emit an optical near-field. The primary waveguide configured to receive the electromagnetic radiation and propagate the electromagnetic radiation toward and proximal to the near-field transducer. The secondary waveguide configured to receive a portion of the electromagnetic radiation from the primary waveguide. The photodiode configured to receive the portion of the electromagnetic radiation from the secondary waveguide and emit a signal that represents a magnitude of the electromagnetic radiation that the laser emits.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: February 20, 2024
    Inventors: Mark Gubbins, Christopher Neil Harvey, Aidan Goggin, Fadi El Hallak, Reshma Anamari Mohandas, Bryn John Howells, Scott Eugene Olson
  • Patent number: 11908500
    Abstract: A multilayer exchange spring recording media consists of a magnetically hard magnetic storage layer strongly exchange coupled to a softer nucleation host. The strong exchange coupling can be through a coupling layer or direct. The hard magnetic storage layer has a strong perpendicular anisotropy. The nucleation host consists of one or more ferromagnetic coupled layers. For a multilayer nucleation host the anisotropy increases from layer to layer. The anisotropy in the softest layer of the nucleation host can be two times smaller than that of the hard magnetic storage layer. The lateral exchange between the grains is small. The nucleation host decreases the coercive field significantly while keeping the energy barrier of the hard layer almost unchanged. The coercive field of the total structure depends on one over number of layers in the nucleation host. The invention proposes a recording media that overcomes the writeability problem of perpendicular recording media.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: February 20, 2024
    Inventor: Dieter Suess
  • Patent number: 11908501
    Abstract: A storage device includes a first interconnection, a second interconnection, a memory cell connected between the first and second interconnections and including a variable resistance element and a switching element that is connected in series to the variable resistance element, and a control circuit configured to exercise control of a read operation to read data stored in the memory cell. The control circuit exercises control in such a manner as to set the first interconnection which has been charged with a first voltage and the second interconnection which has been charged with a second voltage into floating states, to set the switching element into an on-state by discharging the second interconnection set into the floating state to thereby increase a voltage applied to the memory cell, and to read the data stored in the memory cell in a state in which the switching element is set into the on-state.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventors: Akira Katayama, Kosuke Hatsuda
  • Patent number: 11908502
    Abstract: A method for reducing noise in a read signal due attributable to read element asymmetry provides for transmitting a write signal through a write precompensation circuit that shifts rising edges and falling edges of each of pulse in the write signal by a select magnitude and in opposite directions. After the write signal is encoded on a media, a corresponding read signal is read, with a read element, from the media. The method further provides for transmitting the read signal through a magnetoresistive asymmetry compensation (MRAC) block that is tuned to correct second-order non-linearities characterized by a particular set of distortion signatures. The select magnitude of the waveform shift applied by the write precompensation circuit introduces a non-linear signal characteristic that combines with non-linear signal characteristics introduced by the read element to generate one of the particular distortion signatures that is correctable by the MRAC block.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: February 20, 2024
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Walter R. Eppler, Drew Michael Mader
  • Patent number: 11908503
    Abstract: A nonvolatile memory device includes an array of magnetic memory cells, and control logic circuit having a voltage generator therein, which is configured to generate a gate voltage. A row decoder is provided, which is connected by word lines to the array of magnetic memory cells, and has a word line driver driven therein, which is responsive to the gate voltage. A column decoder is provided, which is connected by bit lines and source lines to the array of magnetic memory cells. A write driver is provided, which has a write voltage generating circuit therein that is configured to output a write voltage, in response to: (i) a reference voltage generated using a replica magnetic memory cell, and (ii) a feedback voltage generated using a magnetic memory cell in which a write operation is to be performed.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyuseong Kang, Antonyan Artur, Hyuntaek Jung
  • Patent number: 11908504
    Abstract: A memory device formed of ferroelectric field effect transistors (FeFETs). The memory device can be used as a front end buffer, such as in a data storage device having a non-volatile memory (NVM). A controller can be configured to transfer user data between the NVM and an external client (host) via the buffer. The FeFETs can be arranged in a two-dimensional (2D) or a three-dimensional (3D) array. A monitor circuit can be used to monitor operation of the FeFETs. An optimization controller can be used to adjust at least one operational parameter associated with the FeFETs responsive to the monitored operation by the monitor circuit. The FeFETs may require a refresh operation after each read operation. A power down sequence can involve a read operation without a subsequent refresh operation to wipe the FeFETs, the read operation jettisoning the data read from the buffer memory.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: February 20, 2024
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jon D. Trantham, Praveen Viraraghavan, John W. Dykes, Ian J. Gilbert, Sangita Shreedharan Kalarickal, Matthew J. Totin, Mohamad El-Batal, Darshana H. Mehta
  • Patent number: 11908505
    Abstract: An efficient FeFET-based CAM is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. More specifically, a Ferroelectric FET Based Ternary Content Addressable Memory is disclosed. The design in some examples utilizes two FeFETs and four MOSFETs per cell. The CAM can be written in columns through multi-phase writes. It can be used a normal memory with indexing read. It also has the ability for ternary content-based search. The don't-care values can be either the input or the stored data.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11908506
    Abstract: Methods, systems, and devices for memory cell biasing techniques are described. A memory cell may be accessed during an access phase of an access operation. A pre-charge phase of the access phase may be initiated. The memory cell may be biased to a voltage (e.g., a non-zero voltage) after the pre-charge phase. In some examples, the memory cell may be biased to the voltage when a word line is unbiased and the memory cell is isolated from the digit line.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Angelo Visconti, Giorgio Servalli, Andrea Locatelli
  • Patent number: 11908507
    Abstract: A semiconductor memory device includes a command and address generator configured to decode a command to generate an active command, and generate an address applied with the active command as a row address, a control signal generator configured to generate sequence data changing with a random sequence in response to the active command, and generate a random pick signal when the sequence data is equal to previously stored comparison data, and a memory cell array comprising an odd page memory cell array including a plurality of first memory cells and an even page memory cell array including a plurality of second memory cells, and configured to simultaneously perform the active operation and a hidden hammer refresh operation on the selected first and second memory cells in response to the row address when the random pick signal is activated in response to the active command.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongmin Bang, Seungki Hong
  • Patent number: 11908508
    Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: February 20, 2024
    Inventors: Dale H. Hiscock, Debra M. Bell, Michael Kaminski, Joshua E. Alzheimer, Anthony D. Veches, James S. Rehmeyer
  • Patent number: 11908509
    Abstract: Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John E. Riley, Scott E. Smith, Jennifer E. Taylor, Gary L. Howe
  • Patent number: 11908510
    Abstract: The fuse device includes a plurality of fuse circuits, a global latch circuit and a plurality of local latch circuits. The global latch circuit is coupled to the fuse circuits. The global latch circuit is used to sense the blown states of the fuse circuits at different times, so as to output the fuse information of the fuse circuits at the different times. The local latch circuits are coupled to the global latch circuits. Each of these local latch circuits latches the fuse information output by the global latch circuit at the different times.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: February 20, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chao-Yu Chiang, Chih-Hsuan Chen
  • Patent number: 11908511
    Abstract: A semiconductor memory device includes a memory string, first wirings electrically connected to the memory string, second wirings electrically connected to the first wirings, transistors electrically connected between the first wirings and the second wirings, and a third wiring connected to gate electrodes of the transistors in common. The memory string includes memory transistors connected in series. Gate electrodes of the memory transistors are connected to the first wirings. The semiconductor memory device executes a first read operation in response to an input of a first command set, and executes a second read operation in response to an input of a second command set. A first voltage that turns the transistors ON is applied to the third wiring from an end of the first read operation to a start of the second read operation.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: February 20, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Koji Kato
  • Patent number: 11908512
    Abstract: A microelectronic device comprises local digit line structures, global digit line structures, source line structures, sense transistors, read transistors, and write transistors. The local digit line structures are coupled to strings of memory cells. The global digit line structures overlie the local digit line structures. The source line structures are interposed between the local digit line structures and the global digit line structures. The sense transistors are interposed between the source line structures and the global digit line structures, and are coupled to the local digit line structures and the source line structures. The read transistors are interposed between and are coupled to the sense transistors and the global digit line structures. The write transistors are interposed between and are coupled to the global digit line structures and the local digit line structures. Additional microelectronic devices, memory devices, and electronic systems are also described.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc .
    Inventors: Tomoharu Tanaka, Yoshiaki Fukuzumi
  • Patent number: 11908513
    Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W? values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)?(W?).
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: February 20, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Vipin Tiwari
  • Patent number: 11908514
    Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage config
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: February 20, 2024
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SAS
    Inventors: Antonino Conte, Alin Razafindraibe, Francesco Tomaiuolo, Thibault Mortier
  • Patent number: 11908515
    Abstract: Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: February 20, 2024
    Assignee: Hefei Reliance Memory Limited
    Inventors: Deepak Chandra Sekar, Wayne Frederick Ellis, Brent Steven Haukness, Gary Bela Bronner, Thomas Vogelsang
  • Patent number: 11908516
    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 20, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
  • Patent number: 11908517
    Abstract: A memory device includes a first chip, a second chip and a processor. The second chip is coupled to the first chip at a first node. The second chip includes a first capacitor and a first variable resistor. The first capacitor is coupled to the first node. The first variable resistor is coupled in series with the first capacitor. The processor is coupled to the first node, and is configured to perform a first read operation to the first chip via the first node. A method for operating a memory device is also disclosed herein.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: February 20, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Chiang Hung
  • Patent number: 11908518
    Abstract: A memory system according to an embodiment includes a first wiring, a second wiring, a memory cell between the first wiring and the second wiring and a controller. The memory cell includes a variable resistance element and a switching element. The variable resistance element is switchable between a first low-resistance state and a first high-resistance state. The switching element is switchable between a second low-resistance state and a second high-resistance state in accordance with a supplied voltage. The controller is configured to supply the first wiring with a first voltage switching the switching element to the second low-resistance state, supply the first wiring with a second voltage switching the switching element from the second low-resistance state to the second high-resistance state after the first voltage is supplied, and detect a first target voltage of the second wiring after the second voltage is supplied.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventor: Akira Katayama
  • Patent number: 11908519
    Abstract: Pre-comparing data in a dual compare content compact, low-leakage multi-bit content-addressable memory (CAM) cell is provided. A first compare input and a second compare input of a column in a dual compare content addressable memory (“CAM”) device. A pre-compare signal is generated based on comparing the first compare input and the second compare input. A first polarity of the first compare input is compared with a first polarity a storage node data. A compare output of the first compare input is generated based on a logic state of the pre-compare signal. A first compare match is generated based on the compare output and a second compare match is generated based on the pre-compare signal.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 20, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hema Ramamurthy, Michael Lee
  • Patent number: 11908520
    Abstract: According to one embodiment, a memory device includes a first chip and a second chip provided over the first chip. The first chip includes a first substrate, a first electrode, and a first memory cell array provided between the first substrate and the first electrode. The second chip includes a second substrate, a second electrode in contact with the first electrode, and a second memory cell array provided between the second substrate and the second electrode.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 20, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Hideto Takekida
  • Patent number: 11908521
    Abstract: A non-volatile memory includes memory cells, word lines connected to the memory cells, and a set of regular control gate drivers connected to the word lines. The control gate drivers include different subsets of control gate drivers that receive different sources of voltage and provide different output voltages. A redundant control gate driver, that receives the different sources of voltage and provides the different output voltages, is included that can replace any of the regular control gate drivers.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Liang Li, Qin Zhen
  • Patent number: 11908522
    Abstract: In certain aspects, a memory device includes memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is configured to initiate a program operation on a selected memory cell of the memory cells, obtain a number of occurrences of one or more suspensions during the program operation, and determine a program pulse limit for the program operation based on the number of occurrences of the suspensions.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: February 20, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Huangpeng Zhang, Zhichao Du, Ke Jiang, Cong Luo, Daesik Song
  • Patent number: 11908523
    Abstract: Control logic in a memory device initiates an express programming operation to program the set of memory cells to a target programming level of a set of programming levels. A set of data associated with the express programming operation is stored in a cache register. At a first time during the execution of the express programming operation, a prediction operation is executed to determine a prediction result corresponding to a programming status of the set of memory cells. The prediction result is compared to a threshold level to determine whether a condition is satisfied. The release of the set of data from the cache register is caused in response to satisfying the condition.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Walter Di Francesco, Violante Moschiano, Umberto Siciliani
  • Patent number: 11908524
    Abstract: An apparatus is provided that includes a memory die having a first memory cell, and a controller connected to the memory die. The controller is configured to apply a plurality of programming pulses to the first memory cell, apply a plurality of first verify pulses to the first memory cell, determine from the first verify pulses that the first memory cell has been programmed to a first programmed memory state, apply a single second verify pulse to the first memory cell after determining that the first memory cell has been programmed to the first programmed memory state, determine from the single second verify pulse that the first memory cell is no longer programmed to the first programmed memory state, and apply an additional programming pulse to the first memory cell.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ming Wang, Liang Li, Ke Zhang
  • Patent number: 11908525
    Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventor: Takashi Maeda
  • Patent number: 11908526
    Abstract: According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventors: Naoto Kumano, Kenji Sakurada
  • Patent number: 11908527
    Abstract: The present technology relates to an electronic device. According to the present technology, a memory device may include memory cells respectively connected to a plurality of word lines, a peripheral circuit configured to perform a read operation of reading data stored in selected memory cells connected to a selected word line among the memory cells, and a read operation controller configured to control the peripheral circuit to apply a pass voltage to adjacent word lines adjacent to the selected word line during the read operation, discharge the pass voltage to a target pass voltage less than the pass voltage after a predetermined time elapses, and obtain data stored in the selected memory cells through bit lines connected to the selected memory cells after a target read time elapses, after a voltage applied to the adjacent word lines is discharged to the target pass voltage.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 20, 2024
    Assignee: SK hynix Inc.
    Inventors: Dong Jae Jung, Sung Won Bae
  • Patent number: 11908528
    Abstract: An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: February 20, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Vikas Rana, Arpit Vijayvergia
  • Patent number: 11908529
    Abstract: A data storage device includes a power supply circuit configured to supply power to the data storage device. The power supply circuit includes a voltage clamp configured to operate in a conduction state in response to an over-voltage condition of the power supply circuit. The power supply circuit also includes a fuse in series with the voltage clamp. The fuse is configured to open in response to a current flow through the fuse and the voltage clamp exceeding a threshold value. The power supply circuit also includes a switching device that is configured to latch in a forward conduction mode in response to the voltage clamp operating in the conduction state. The switching device couples power from a positive voltage bus to the voltage clamp when the switching device is in the forward conduction mode.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel J. Linnen, Kirubakaran Periyannan, Khanfer A. Kukkady
  • Patent number: 11908530
    Abstract: A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than that of the first capacitor. The pulse generator is coupled with the ADC and generates pulses. The pulses cause the first capacitor to connect to the second capacitor and equalize charge between the first capacitor and the second capacitor. An inverted signal of the pulses causes the second capacitor to be coupled with the voltage reference node to pre-charge the first capacitor.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Macerola, Gianni Rea
  • Patent number: 11908531
    Abstract: A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages. A controller of the non-volatile memory issues a command to perform a programming pass for a physical page among the multiple physical pages. The controller determines whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received. Based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detects an under-programming error and performs mitigation for the detected under-programming error.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Roman Alexander Pletka, Radu Ioan Stoica, Nikolas Ioannou, Charalampos Pozidis, Timothy J. Fisher, Aaron Daniel Fry
  • Patent number: 11908532
    Abstract: Provided herein is a memory device and a method of operating the memory device. The memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation for storing data in selected memory cells among the plurality of memory cells, and a control logic circuit configured to control the peripheral circuit to form threshold voltage distributions corresponding to target program states corresponding to the data to be stored in the selected memory cells, respectively, wherein the control logic controls the peripheral circuit to perform a main verify operation for any one of the target program states of the selected memory cells when a pre-verify operation for the any one of the target program states has passed.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 20, 2024
    Assignee: SK hynix Inc.
    Inventors: Jong Woo Kim, Young Cheol Shin
  • Patent number: 11908533
    Abstract: Disclosed is an operation method of a memory device which includes floating a first driving line corresponding to a first word line from the first word line and precharging the first driving line with a first voltage, floating the first driving line from the first voltage to sense a first voltage variation of the first driving line, storing the first voltage variation in a first capacitor, electrically connecting the first driving line to the first word line and precharging the first driving line and the first word line with the first voltage, floating the first driving line and the first word line from the first voltage to sense a second voltage variation of the first driving line and the first word line, and outputting a first detection signal corresponding to a first leakage current through the first word line based on the first voltage variation and the second voltage variation.
    Type: Grant
    Filed: April 24, 2022
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyunkook Park