Patents Issued in February 20, 2024
  • Patent number: 11908686
    Abstract: The present application provides methods for manufacturing a vertical device. To begin with, a GaN-based semiconductor substrate is etched from a front surface to form a trench. Then, a P-type semiconductor layer and an N-type semiconductor layer are sequentially formed on a bottom wall and side walls of the trench and the front surface of the semiconductor substrate. The trench is partially filled with the P-type semiconductor layer. Thereafter, the N-type semiconductor layer and the P-type semiconductor layer are planarized, and the P-type semiconductor layer and the N-type semiconductor layer in the trench are retained. Next, a gate structure is formed at a gate area of the front surface of the semiconductor substrate, a source electrode is formed on two sides of the gate structure, and a drain electrode is formed on a rear surface of the semiconductor substrate respectively.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: February 20, 2024
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 11908687
    Abstract: A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Anup Pancholi, John Heck, Thomas Sounart, Harel Frish, Sansaptak Dasgupta
  • Patent number: 11908688
    Abstract: A method for manufacturing a nitride semiconductor substrate, including: a step of preparing a base substrate; a step of forming a mask layer having a plurality of openings on the main surface of the base substrate; a first step of growing a first layer whose surface is composed only of inclined interfaces; and a second step of epitaxially growing a single crystal of a group III nitride semiconductor on the first layer, making the inclined interfaces disappear, and growing a second layer having a mirror surface, wherein in the first step, at least one valley and a plurality of tops are formed at an upper side of each of the plurality of openings of the mask layer by forming a plurality of concaves on a top surface of the single crystal and making the (0001) plane disappear.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: February 20, 2024
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Takehiro Yoshida
  • Patent number: 11908689
    Abstract: The present application discloses a method, a system, a device, and a storage medium for fabricating a GaN chip. The method includes: growing a Nb2N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb2N sacrificial layer; growing a Ta2N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta2N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb2N sacrificial layer and the Ta2N sacrificial layer; and transferring remaining material after removal of the Nb2N sacrificial layer and the Ta2N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 20, 2024
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Fen Guo, Kang Su, Lang Zhou, Tuo Li, Hongtao Man
  • Patent number: 11908690
    Abstract: In certain examples, methods and semiconductor structures are directed to multilayered structures including TMD (transition metal dichalcogenide material or TMD-like material and a polymer-based layer which is characterized as exhibiting flexibility. A first layer including a TMD-based material (e.g., an atomic-thick layer including TMD) or TMD-like material is provided or grown on a surface which in certain instances may be a rigid platform or substrate. A plurality of electrodes are provided on or as part of the first layer, and another layer or film including polymer is applied to cover the first layer and the electrodes. The other layer is integrated with the TMD material or TMD-like material and the first layer, and the other layer provides a flexible substrate such as when released from the exemplary rigid platform or substrate.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: February 20, 2024
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Alwin S. Daus, Sam Vaziri, Eric Pop
  • Patent number: 11908691
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: February 20, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Patent number: 11908692
    Abstract: A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Tzuan-Horng Liu, Ying-Ju Chen
  • Patent number: 11908693
    Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first mask patterns over the target layer. The method also includes forming a lining layer conformally covering the first mask patterns and the target layer. A first opening is formed over the lining layer and between the first mask patterns. The method further includes filling the first opening with a second mask pattern, and performing an etching process on the lining layer and the target layer using the first mask patterns and the second mask pattern as a mask such that a plurality of second openings are formed in the target layer.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: February 20, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ping Hsu
  • Patent number: 11908694
    Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 20, 2024
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Michael Hell, Caspar Leendertz, Kristijan Luka Mletschnig, Hans-Joachim Schulze
  • Patent number: 11908695
    Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Ta-Hsiang Kung, Xiong-Fei Yu, Chi On Chui
  • Patent number: 11908696
    Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: February 20, 2024
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Hao Jiang, Mehul Naik, Wenting Hou, Jianxin Lei, Chen Gong, Yong Cao
  • Patent number: 11908697
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 11908698
    Abstract: The invention relates to a method for plating a recess in a substrate, a device for plating a recess in a substrate and a system for plating a recess in a substrate comprising the device. The method for plating a recess in a substrate comprises the following steps: Providing a substrate with a substrate surface comprising at least one recess, applying a replacement gas to the recess to replace an amount of ambient gas in the recess to at least partially clear the recess from the ambient gas, applying a processing fluid to the recess, wherein the replacement gas dissolves in the processing fluid to at least partially clear the recess from the replacement gas, and plating the recess.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: February 20, 2024
    Assignee: SEMSYSCO GMBH
    Inventors: Franz Markut, Thomas Wirnsberger, Oliver Knoll, Andreas Gleissner, Harald Okorn-Schmidt, Philipp Engesser
  • Patent number: 11908699
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: February 20, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
  • Patent number: 11908700
    Abstract: In some embodiments of the present disclosure, a method of manufacturing a semiconductor structure includes the following operations. A substrate including a first atom and a second atom is provided. An etchant is dispatched from an ionizer. A compound is formed over the substrate by bonding the first atom with the etchant. A particle is released from an implanter. The compound is removed by bombarding the compound with the particle having an energy smaller than a bonding energy between the first atom and the second atom, wherein the particle is different from the etchant.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Nai-Han Cheng, Chi-Ming Yang
  • Patent number: 11908701
    Abstract: A patterning method includes at least the following steps. A first material layer is provided. A second material layer is provided over the first material layer. The second material layer partially exposes the first material layer. A passivation layer is formed over the first material layer and the second material layer. A growth rate of the passivation layer on the second material layer is greater than a growth rate of the passivation layer on the first material layer. A first etching process is performed to remove a portion of the passivation layer and a portion of the first material layer.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Christine Y Ouyang, Li-Te Lin
  • Patent number: 11908702
    Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Pi Chang, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Huang-Lin Chao
  • Patent number: 11908703
    Abstract: Heating treatment is performed on multiple dummy wafers to preheat in-chamber structures including a susceptor and the like prior to the treatment of a semiconductor wafer to be treated. The first few ones of the multiple dummy wafers are heated to a first heating temperature by light irradiation from halogen lamps, and are thereafter irradiated with a flash of light. The subsequent few ones of the multiple dummy wafers are heated to a second heating temperature lower than the first heating temperature by light irradiation from the halogen lamps, and are thereafter irradiated with a flash of light. This stabilizes the temperature of the in-chamber structures in a shorter time with fewer dummy wafers because the dummy wafers are heated to the high temperature and thereafter heated to the low temperature.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 20, 2024
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Mao Omori, Kazuhiko Fuse
  • Patent number: 11908704
    Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: February 20, 2024
    Assignee: KEPLER COMPUTING INC.
    Inventors: Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren, Fnu Atiquzzaman, Gabriel Antonio Paulius Velarde, Noriyuki Sato, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh, Sasikanth Manipatruni
  • Patent number: 11908705
    Abstract: A method for aligning interconnects that includes trimming and forming a frame of strips of interconnects. The frame of strips of interconnects includes interdigitated pins. The method also includes removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects. The method includes aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects. A strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects. The method further includes singulating the aligned array of strips of interconnects.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: February 20, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Chih-Chien Ho
  • Patent number: 11908706
    Abstract: A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Tin-Hao Kuo
  • Patent number: 11908708
    Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
  • Patent number: 11908709
    Abstract: A container for containing a raw material of a chemical liquid and a method of preparing a container are provided. The container at least includes an inner wall and solvent-treated surface of the inner wall. The method of preparing a container includes treating a surface of the inner wall with water and treating the surface the inner wall with an organic solvent.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: February 20, 2024
    Assignee: FUJIFILM Electronic Materials U.S.A., Inc.
    Inventors: Marcia Cole-Yocom, Bryan Hinzie
  • Patent number: 11908710
    Abstract: A substrate processing apparatus includes a substrate cleaning unit cleaning a substrate, a substrate drying unit drying the substrate, and a transfer robot transferring the substrate between the substrate cleaning unit and the substrate drying unit. The substrate drying unit includes a substrate processing container having a substrate processing space accommodating the substrate, and the transfer robot includes a surface temperature measurement sensor measuring a surface temperature of the substrate processing container.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: February 20, 2024
    Assignee: SEMES CO., LTD.
    Inventors: Jin Woo Jung, Do Hyeon Yoon, Yong Hee Lee
  • Patent number: 11908711
    Abstract: A method of planarizing a substrate comprises dispensing formable material onto a substrate, contacting, at a planarizing station at a first location, a superstrate held by a superstrate chuck with the formable material on the substrate, thereby forming a multilayer structure including the superstrate, a film of the formable material, and the substrate, releasing the superstrate from the superstrate chuck, moving the multilayer structure from the first location to a curing station located at a second location away from the first location, the curing station including an array of light-emitting diodes, and curing the film of the multilayer structure by exposing the film to light emitted from the array of light-emitting diodes.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 20, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Steven C. Shackleton, Seth J. Bamesberger, Masaki Saito
  • Patent number: 11908712
    Abstract: A semiconductor manufacturing apparatus including a plurality of process modules for performing desired processes on a plurality of substrates and a plurality of transfer modules for serially transferring the plurality of substrates to the plurality of process modules is provided. The semiconductor manufacturing apparatus comprises a scheduler for calculating a cycle time so that a difference in time required for each of the desired processes is within an allowable time range and generating a transfer plan for the plurality of substrates based on the cycle time, and a transfer controller for controlling the plurality of transfer modules so that the plurality of substrates are serially transferred to the process modules according to the generated transfer plan.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: February 20, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Toshiharu Hirata, Takafumi Matsuhashi, Kunio Takano, Minoru Nagasawa
  • Patent number: 11908713
    Abstract: A semiconductor substrate treatment system includes: a chamber having an internal space defined by a first surface and a second surface of the chamber opposing each other, and a third surface of the chamber connected the first surface and the second surface; a transfer device in a central region of the internal space for transferring a semiconductor substrate; an ionizing device including first and second discharge devices on the second surface for emitting ions having a first polarity and a second polarity, respectively, to charge particles in the internal space with the first and second polarities, and a third discharge device disposed above the transfer device, and configured to emit ions having the first and second polarities together; and first and second dust collecting assemblies on the third surface, facing each other, and configured to collect charged particles by generating electric fields having different polarities.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daesung Jung, Kwangil Kim
  • Patent number: 11908714
    Abstract: A transfer robot assembly arranged within an ATV transfer module includes a transfer robot that includes an end effector and one or more arm segments connected between the end effector and a transfer robot platform. A first robot alignment arm is connected to the transfer robot platform. A second robot alignment arm is connected to the first robot alignment arm and to a mounting chassis of the ATV transfer module. The transfer robot assembly is configured to actuate the first robot alignment arm and the second robot alignment arm to raise and lower the transfer robot to adjust a position of the transfer robot in a vertical direction and in a horizontal direction. The transfer robot is configured to fold into a folded configuration having a narrow profile occupying less than 50% of an overall depth of the ATV transfer module.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: February 20, 2024
    Assignee: Lam Research Corporation
    Inventors: Richard H. Gould, Richard Blank
  • Patent number: 11908715
    Abstract: A temperature-controlled substrate support for a substrate processing system includes a substrate support located in the processing chamber. The substrate support includes N zones and N resistive heaters, respectively, where N is an integer greater than one. A temperature sensor is located in one of the N zones. A controller is configured to calculate N resistances of the N resistive heaters during operation and to adjust power to N?1 of the N resistive heaters during operation of the substrate processing system in response to the temperature measured in the one of the N zones by the temperature sensor, the N resistances of the N resistive heaters, and N?1 resistance ratios.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: February 20, 2024
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Sairam Sundaram, Aaron Durbin, Ramesh Chandrasekharan
  • Patent number: 11908716
    Abstract: Methods and systems for monitoring etch or deposition processes using image-based in-situ process monitoring techniques include illuminating a measurement area on a sample disposed in a process chamber. The measurement area is illuminated using an input beam generated remote from the process chamber and transmitted to a first viewing window of the process chamber by a first optical fiber. Portions of the first input beam reflected from the measurement area are transmitted from the first viewing window to an imaging sensor by a second optical fiber. A sequence of images is obtained at the imaging sensor, and a change in reflectance of pixels within each of the images is determined. The etch or deposition process is monitored based on the change in reflectance.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: February 20, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Guoheng Zhao, Venkatakaushik Voleti, Todd Egan, Kyle R. Tantiwong, Andreas Schulze, Niranjan Ramchandra Khasgiwale, Mehdi Vaez-Iravani
  • Patent number: 11908717
    Abstract: A transfer method transfers a substrate between a transfer unit configured to hold and transfer the substrate and a substrate stage serving as a transfer destination or a transfer source of the substrate. The transfer method includes: acquiring positional information of the transfer unit and positional information of the substrate stage; determining whether or not there is a risk for the substrate to contact with the substrate stage, based on the acquired positional information of the transfer unit and positional information of the substrate stage; and when determined that there is a risk for the substrate to contact with the substrate stage, notifying the risk according to the determination at the determining.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: February 20, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masakazu Yamamoto, Tadashi Enomoto
  • Patent number: 11908718
    Abstract: Methods and apparatus for the in-situ measurement of metrology parameters are disclosed herein. Some embodiments of the disclosure further provide for the real-time adjustment of process parameters based on the measure metrology parameters. Some embodiments of the disclosure provide for a multi-stage processing chamber top plate with one or more sensors between process stations.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: February 20, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Ramesh Krishnamurthy, Lakshmanan Karuppiah
  • Patent number: 11908719
    Abstract: In an embodiment, a system includes: a base; and a rod set comprising multiple rods connected to the base, wherein each rod of the rod set comprises multiple fingers disposed in a vertically-stacked relationship to each other and separated respectively from each other by respective slots, wherein each slot is configured to receive a bevel of a wafer, and wherein each of the multiple fingers comprises a rounded end at a furthest extension.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Wen Cheng, Xin-Kai Huang, Kuei-Hsiung Cho
  • Patent number: 11908720
    Abstract: Disclosed are a CMP wafer cleaning apparatus, and a wafer transfer manipulator and a wafer overturn method for same. The wafer transfer manipulator includes: a transverse transfer shaft, with same only being located at a side of a cleaning unit; a transverse transfer carriage provided on the transverse transfer shaft, and capable of transversely moving along the transverse transfer shaft; a first vertical lifting shaft provided on the transverse transfer carriage, and capable of vertically moving on the transverse transfer carriage; a rotary table provided on the first vertical lifting shaft; and a first claw clamping arm connected to the rotary table, and driven by the rotary table to move in a rotational manner. The CMP wafer cleaning apparatus is provided, and when the CMP wafer cleaning apparatus fails, safe storage of a polished wafer can be realized.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 20, 2024
    Assignee: HANGZHOU SIZONE ELECTRONIC TECHNOLOGY INC.
    Inventors: Linghan Shen, EdwardLiCang Lee
  • Patent number: 11908721
    Abstract: A substrate transport apparatus auto-teach system for auto-teaching a substrate station location, the system including a frame, a substrate transport connected to the frame, the substrate transport having an end effector configured to support a substrate, and a controller configured to move the substrate transport so that the substrate transport biases the substrate supported on the end effector against a substrate station feature causing a change in eccentricity between the substrate and the end effector, determine the change in eccentricity, and determine the substrate station location based on at least the change in eccentricity between the substrate and the end effector.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: February 20, 2024
    Assignee: Brooks Automation US, LLC
    Inventors: Jairo T. Moura, Aaron Gawlik, Reza Saeidpourazar
  • Patent number: 11908722
    Abstract: A teaching substrate is loaded into a load port of an equipment front-end module (EFEM) of a fabrication or inspection tool. The EFEM includes a substrate-handling robot. The teaching substrate includes a plurality of sensors and one or more wireless transceivers. The tool includes a plurality of stations. With the teaching substrate in the EFEM, the substrate-handling robot moves along an initial route and sensor data are wirelessly received from the teaching substrate. Based at least in part on the sensor data, a modified route distinct from the initial route is determined. The substrate-handling robot moves along the modified route, handling the teaching substrate. Based at least in part on the sensor data, positions of the plurality of stations are determined.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: February 20, 2024
    Assignee: KLA Corporation
    Inventors: Avner Safrani, Shai Mark, Amir Aizen, Maor Arbit
  • Patent number: 11908723
    Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: February 20, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Akihiro Horibe, Qianwen Chen, Risa Miyazawa, Michael P. Belyansky, John Knickerbocker, Takashi Hisada
  • Patent number: 11908724
    Abstract: Embodiments disclosed herein include a method of determining the position of a sensor wafer relative to a pedestal. In an embodiment, the method comprises placing a sensor wafer onto the pedestal, wherein the sensor wafer comprises a first surface that is supported by the pedestal, a second surface opposite the first surface, and an edge surface connecting the first surface to the second surface, wherein a plurality of sensor regions are formed on the edge surface, and wherein the pedestal comprises a major surface and an annular wall surrounding the sensor wafer. In an embodiment, the method further comprises determining a gap distance between each of the plurality of sensor regions and the annular wall. In an embodiment, the method may further comprise determining a center-point offset of a center-point of the sensor wafer relative to a center point of the annular wall from the gap distances.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: February 20, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Charles G. Potter, Anthony D. Vaughan
  • Patent number: 11908725
    Abstract: The present invention relates to an electrostatic chuck heater having a bipolar structure, the electrostatic chuck heater comprising: a heater body having an internal electrode and an external electrode for selectively performing any one of an RF grounding function and an electrostatic chuck function according to a semiconductor process mode; and a heater support mounted below the heater body so as to support the heater body.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: February 20, 2024
    Assignee: MICO CERAMICS LTD.
    Inventors: Jin Young Choi, Jun Won Seo, Ju Sung Lee
  • Patent number: 11908726
    Abstract: This application relates to a method of manufacturing an electrostatic chuck having good characteristics in heat dissipation, thermal shock resistance, and lightness. In one aspect, the method includes preparing a composite powder by ball-milling (i) aluminum or aluminum alloy powder and (ii) carbon-based nanomaterial powder. The method may also include preparing an electrode layer by sintering the composite powder through spark plasma sintering (SPS), and forming a dielectric layer on the electrode layer.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: February 20, 2024
    Assignee: Pukyong National University Industry-University Cooperation Foundation
    Inventor: Hansang Kwon
  • Patent number: 11908727
    Abstract: Disclosed are support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same. The support substrate comprises a main body, and a plurality of first protrusions finely protruding from an upper surface of the main body. The main body and the first protrusions include the same material and are formed as a unitary structure. The first protrusions are spaced apart from each other in first and second directions intersecting each other, when viewed in plan.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kunsil Lee, Seung Hwan Lee
  • Patent number: 11908728
    Abstract: Techniques herein include a process chamber for depositing thin films to backside surfaces of wafers to reduce wafer bowing and distortion. A substrate support provides an annular perimeter seal around the bottom and/or side of the wafer which allows the majority of the substrate backside to be exposed to a process environment. A supported wafer separates the chamber into lower and upper chambers that provide different process environments. The lower section of the processing chamber includes deposition hardware configured to apply and remove thin films. The upper section can remain a chemically inert environment, protecting the existing features on the top surface of the wafer. Multiple exhausts and differential pressures are used to prevent deposition gasses from accessing the working surface of a wafer.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: February 20, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Ronald Nasman, Gerrit J. Leusink, Rodney L. Robison, Hoyoung Kang, Daniel Fulford
  • Patent number: 11908729
    Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: February 20, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
  • Patent number: 11908730
    Abstract: A method for fabricating a semiconductor device includes preparing a substrate including a first region and a second region, forming a lower alternating stack on the substrate; etching the lower alternating stack to form a lower opening in the second region, forming an upper alternating stack on the lower opening and the lower alternating stack to form recess portion caused by filling the lower opening in the second region, forming a mask layer on the upper alternating stack using the recess portion as an alignment key, and etching the upper alternating stack by using the mask layer as a barrier to form a pattern in the first region.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: February 20, 2024
    Assignee: SK hynix Inc.
    Inventor: Jong-Hoon Kim
  • Patent number: 11908731
    Abstract: A structure includes a dielectric layer, and a metal line in the dielectric layer. The metal line has a first straight edge and a second straight edge extending in a lengthwise direction of the metal line. The first straight edge and the second straight edge are parallel to each other. A via is underlying and joined to the metal line. The via has a third straight edge underlying and vertically aligned to the first straight edge, and a first curved edge and a second curved edge connecting to opposite ends of the third straight edge.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Tse Lai, Ya Hui Chang
  • Patent number: 11908732
    Abstract: A method of forming a pitch pattern is provided. The method includes forming two adjacent mandrels separated by a first distance, D1, on a substrate, and forming a first set of alternating sidewall spacers between the two adjacent mandrels. The method further includes removing the two adjacent mandrels, and forming a second set of alternating sidewall spacers and a third set of alternating sidewall spacers on opposite sides of the first set of sidewall spacers.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: February 20, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, Chanro Park, Koichi Motoyama
  • Patent number: 11908733
    Abstract: Provided are a substrate processing method and a device manufactured by using the same, which may improve etch selectivity of an insulating layer deposited on a stepped structure. The substrate processing method includes: forming a first layer on a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface; weakening at least a portion of the first layer; forming a second layer on the first layer; and performing an isotropic etching process on the first layer and the second layer.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: February 20, 2024
    Assignee: ASM IP Holding B.V.
    Inventor: Yoon Ki Min
  • Patent number: 11908734
    Abstract: A semiconductor fabrication method that uses a graphene etch stop is disclosed. The method comprises forming a first set of trenches and a second set of trenches in a substrate. The first set of trenches are narrower than the second set of trenches. The method further comprises forming a graphene layer in the first and second sets of trenches. The method further comprises depositing a first conductor in the first and second sets of trenches. The method further comprises removing the first conductor from the second set of trenches using an etching process. The graphene layer acts as an etch stop for the etching process. The method further comprises depositing a second conductor in the second set of trenches. The second conductor is different than the first conductor.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Takeshi Nogami, Son Nguyen, Balasubramanian Pranatharthiharan
  • Patent number: 11908735
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Chang, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Patent number: 11908736
    Abstract: Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process are disclosed. The methods may include: providing a substrate comprising a dielectric surface into a reaction chamber; depositing a nucleation film directly on the dielectric surface; and depositing a molybdenum metal film directly on the nucleation film, wherein depositing the molybdenum metal film includes: contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor; and contacting the substrate with a second vapor phase reactant comprising a reducing agent precursor. Semiconductor device structures including a molybdenum metal film disposed over a surface of a dielectric material with an intermediate nucleation film are also disclosed.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: February 20, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Bhushan Zope, Kiran Shrestha, Shankar Swaminathan, Chiyu Zhu, Henri Jussila, Qi Xie