Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.

Abstract: A FET including a hybrid gate spacer separating a gate electrode from at least one of a source, a drain, or source/drain contact metallization. The hybrid spacer may include a low-k dielectric material for a reduction in parasitic capacitance. The hybrid spacer may further include one or more other dielectric materials of greater relative permittivity that may protect one or more surfaces of the low-k dielectric material from damage by subsequent transistor fabrication operations. The hybrid spacer may include a low-k dielectric material separating a lower portion of a gate electrode sidewall from the source/drain terminal, and a dielectric spacer cap separating to an upper portion of the gate electrode sidewall from the source/drain terminal. The hybrid spacer may have a lower total capacitance than conventional spacers while still remaining robust to downstream fabrication processes. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

Abstract: A vertical field effect transistor includes a top source/drain region in contact with a top portion of a channel fin extending perpendicularly from a semiconductor substrate, a bottom source/drain region is disposed above the semiconductor substrate and on opposite sidewalls of a bottom portion of the channel fin, a metal gate surrounding the channel fin is separated from the top source/drain region by a top spacer and from the bottom source/drain region by a bottom spacer, the metal gate and the top spacer are in contact with an adjacent first interlevel dielectric layer. A silicide layer is directly above an uppermost surface of the top source/drain region, and a nitride layer is directly above an uppermost surface of the silicide layer. A top source/drain contact, having a size that is substantially less than a length of the channel fin, extends until an uppermost surface of the nitride layer.

Abstract: A coating liquid for forming an n-type oxide semiconductor film, the coating liquid including: a Group A element, which is at least one selected from the group consisting of Sc, Y, Ln, B, Al, and Ga; a Group B element, which is at least one of In and Tl; a Group C element, which is at least one selected from the group consisting of Group 4 elements, Group 5 elements, Group 6 elements, Group 7 elements, Group 8 elements, Group 9 elements, Group 10 elements, Group 14 elements, Group 15 elements, and Group 16 elements; and a solvent.

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.

Abstract: A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.

Abstract: A semiconductor device with a high on-state current is provided. The semiconductor device includes a first oxide, a second oxide over the first oxide, a third oxide over the second oxide, a first insulator over the third oxide, a conductor over the first insulator, a second insulator in contact with the second oxide and the third oxide, and a third insulator over the second insulator; the second oxide includes first region to fifth regions; the resistance of the first region and the resistance of the second region are lower than the resistance of the third region; the resistance of the fourth region and the resistance of the fifth region are lower than the resistance of the third region and higher than the resistance of the first region and the resistance of the second region; and the conductor is provided over the third region, the fourth region, and the fifth region to overlap with the third region, the fourth region, and the fifth region.

Abstract: Embodiments include two-dimensional (2D) semiconductor sheet transistors and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of 2D semiconductor sheets, where individual ones of the 2D semiconductor sheets have a first end and a second end opposite from the first end. In an embodiment, a first spacer is over the first end of the 2D semiconductor sheets, and a second spacer is over the second end of the 2D semiconductor sheets. Embodiments further comprise a gate electrode between the first spacer and the second spacer, a source contact adjacent to the first end of the 2D semiconductor sheets, and a drain contact adjacent to the second end of the 2D semiconductor sheets.

Abstract: A thin film transistor (TFT) substrate comprises a TFT located on a substrate and including a gate electrode, a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer, the gate electrode and the second semiconductor layer vertically stacked, and the first and second semiconductor layers are made of polycrystalline silicon, and wherein the first and second semiconductor layers are electrically connected to each other in series and respectively include first and second channel portions, and at least one of the first and second channel portions has a bent structure in a plan view.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

Abstract: A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.

Abstract: A semiconductor device includes an insulated gate bipolar transistor region and a diode region adjacent to each other, wherein the insulated gate bipolar transistor region includes base layers of a second conductive type provided on the first main surface side, emitter layers of the first conductive type selectively provided in a surface layer of the base layer on the first main surface side, multiple gate electrodes provided on the first main surface side of the semiconductor substrate, aligned in a first direction extending along the first main surface, and facing the emitter layer, the base layer, and the drift layer via a gate insulating film, carrier injection suppression layers of the first conductive type selectively provided in a surface layer of the base layer on the first main surface side and sandwiched by the base layers in the first direction.

Abstract: A Schottky barrier diode 1 includes: a semiconductor substrate made of gallium oxide; a drift layer made of gallium oxide; an anode electrode brought into Schottky contact with an upper surface of the drift layer; and a cathode electrode brought into ohmic contact with a lower surface of the semiconductor substrate. A ring-shaped outer peripheral trench is formed in the upper surface of the drift layer, and the anode electrode is partly filled in the outer peripheral trench. A ring-shaped back surface trench is formed in the lower surface of the semiconductor substrate such that the bottom thereof reaches the drift layer. This limits a current path to the area surrounded by the back surface trench, thereby mitigating electric field concentration in the vicinity of the bottom of the outer peripheral trench.

Abstract: Described herein is an optical sensor, a detector including the optical sensor for an optical detection of at least one object, and a method for manufacturing the optical sensor. The optical sensor (110) includes a substrate (120); a photoconductive layer (112) applied to a first portion (116) of a surface (118) of the substrate (120); and at least one electrode layer (124) applied to a second portion (126) of the surface (118) of the substrate (120). The optical sensor (110) exhibits a linear current-voltage characteristic according to Ohm's law.

Abstract: A solar cell module includes first and second solar cells each including a plurality of first and second electrodes formed on a back surface of a semiconductor substrate, a first conductive line connected to the first electrodes, and a second conductive line connected to the second electrodes, and an interconnector connecting the first conductive line of the first solar cell to the second conductive line of the second solar cell. At least one of an area of an overlap portion, an area of a connection portion, a connection position, and a connection shape between the interconnector and the first conductive line of the first solar cell is different from at least one of an area of an overlap portion, an area of a connection portion, a connection position, and a connection shape between the interconnector and the second conductive line of the second solar cell.

Abstract: Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, forming a first semiconductor region and a second semiconductor region on the back side of a substrate. A first conductive busbar can be formed above the first semiconductor region. A first portion of a second conductive busbar can be formed above the second semiconductor region. A second portion of the second conductive busbar can be formed above the second semiconductor region, where a separation region separates the second portion and the first portion of the second conductive busbar. A third conductive busbar can be formed above the first semiconductor region. A first conductive bridge can be formed above the separation region, where the first conductive bridge electrically connects the first conductive busbar to the third conductive busbar.

Abstract: A light sensor having a voltage reversing mechanism is provided. A photoelectric component converts a first light signal into a first photocurrent. A capacitor is charged to a first voltage by the first photocurrent. A counter counts a first coarse count value according to the first voltage. The photoelectric component converts a second light signal into a second photocurrent. The capacitor is charged from a reversed first voltage to a second voltage by the second photocurrent. The counter counts a second coarse count value according to the second voltage. The counter counts a fine count value according to the second coarse count value. One of the first light signal and the second light signal is emitted by both of an ambient light source and a light-emitting component and then reflected by a tested object, and the other one of them is emitted by only the ambient light source.

Abstract: A method of making a plasmonic metal/graphene heterostructure comprises heating an organometallic complex precursor comprising a metal at a first temperature T1 for a first period of time t1 to deposit a layer of the metal on a surface of a heated substrate, the heated substrate in fluid communication with the precursor; and heating, in situ, the precursor at a second temperature T2 for a second period of time t2 to simultaneously form on the layer of the metal, a monolayer of graphene and a plurality of carbon-encapsulated metal nanostructures comprising the metal, thereby providing the plasmonic metal/graphene heterostructure. The heated substrate is characterized by a third temperature T3. The plasmonic metal/graphene heterostructures, devices incorporating the heterostructures, and methods of using the heterostructures are also provided.

Abstract: A transparent electronic device includes an organic film, an amorphous transparent oxycarbide layer, and a matrix layer. The organic film includes a polymer containing carboxyl groups (—COOH). The amorphous transparent oxycarbide layer is disposed on the organic film and consists of a metal element, carbon element, oxygen element and an additional element. The metal element is selected from molybdenum (Mo), indium (In), tin (Sn), zinc (Zn), cadmium (Cd) and a combination thereof. An atomic number percentage of the additional element is equal to or greater than 0%, and is less than the least of an atomic number percentage of the metal element, an atomic number percentage of the oxygen element and an atomic number percentage of the carbon element. The matrix layer is disposed on the amorphous transparent oxycarbide layer. A manufacturing method of a transparent electronic device is also provided.

Abstract: The invention provides an optoelectronic device comprising a porous material, which porous material comprises a semiconductor comprising a perovskite. The porous material may comprise a porous perovskite. Thus, the porous material may be a perovskite material which is itself porous. Additionally or alternatively, the porous material may comprise a porous dielectric scaffold material, such as alumina, and a coating disposed on a surface thereof, which coating comprises the semiconductor comprising the perovskite. Thus, in some embodiments the porosity arises from the dielectric scaffold rather than from the perovskite itself. The porous material is usually infiltrated by a charge transporting material such as a hole conductor, a liquid electrolyte, or an electron conductor. The invention further provides the use of the porous material as a semiconductor in an optoelectronic device. Further provided is the use of the porous material as a photosensitizing, semiconducting material in an optoelectronic device.

Abstract: Photovoltaic device with band-stop filter. The photovoltaic device includes an amorphous photovoltaic material and a band-stop filter structure having a stopband extending from a lower limiting angular frequency ?min?0 to an upper limiting angular frequency ?max where ?max>?min. The band-stop filter structure is arranged in the photovoltaic device relative to the photovoltaic material in order to attenuate electromagnetic radiations reaching the photovoltaic material with angular frequencies of ?* in the stopband, so that ?min<?*<?max. The angular frequencies ?* correspond to electronic excitations ??* from valence band tail (VBT) states of the amorphous photovoltaic material to conduction band tail (CBT) states of the amorphous photovoltaic material.

Abstract: A method is provided for fabricating and inspecting a photovoltaic assembly including a base, at least one photovoltaic module, and at least one adhesion layer based on a crosslinkable polymer material. The method includes depositing the at least one adhesion layer on the base; an assembly step; a partial crosslinking step; an electrical connection step; inspecting for mechanical and electrical functioning; in the event of correct functioning being detected, a crosslinking finalization step; in the event of incorrect functioning being detected removing at least one defective photovoltaic module.

Abstract: A solar or photovoltaic (PV) system that includes a PV device with an upper surface configured for receiving sunlight and converting the received sunlight into electrical energy. An infrared (IR) reflecting film is placed over the upper surface to increase the efficiency of the PV device by retaining its operating temperature in more desired ranges. The IR reflecting film includes a substrate with a top surface and a bottom surface, and the bottom surface is mated with the upper surface of the PV device. The IR reflecting film also includes a plurality of structures, each with a recessed surface, formed on the top surface of the substrate. The IR reflecting film includes a reflective mask on the top surface of the substrate that includes reflective elements each disposed in the structures' recessed surfaces. In use, the IR reflecting film reflects sunlight having a wavelength greater than about 950 nanometers (nm).

Abstract: A solar module having on the front a cover plate with an outer surface and an inner surface is described. An optical interference layer for reflecting light within a predefined wavelength range is arranged on the inner surface. The inner surface and/or the outer surface have a patterned region. The patterned region has a height profile with hills and valleys, and a portion of the patterned region is composed of flat segments that are inclined relative to a plane of the cover plate.

Abstract: A light-emitting device includes one or more light-emitting units each including a light-emitting element including a function of a thyristor; an electrode for light emission to which a first voltage is applied for light emission of the light-emitting unit; and one or more light emission permission thyristors that permit the light-emitting element to emit light by a second voltage that is lower than the first voltage and set irrespective of the first voltage.

Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.

Abstract: Provided is a method to recycle valuable materials included in a photovoltaic module having a resin back sheet or the like, for efficiently and easily recovering the valuable materials by removing the resin components from the photovoltaic module. The method of recovering valuable materials from a photovoltaic module, includes: a loading step of loading a photovoltaic module (X) having a resin back sheet and a sealing resin layer on a heat-resistant porous molded body (A) with the back sheet surface facing down; and a heating step of heating a load including the photovoltaic module (X) and the porous molded body (A) in a heating furnace in an oxidizing atmosphere to melt and then combust the resin components.

Abstract: A process for manufacturing a multilayered thin film, includes: forming a photovoltaic conversion layer, comprising Cu2O as a main component, on a first transparent electrode; and placing, under a first atmosphere at an oxygen level of from 5.0×10?8 [g/L] to 5.0×10?5 [g/L] for 1 h to 1600 h, a member having the photovoltaic conversion layer formed on the first transparent electrode.

Abstract: A photovoltaic module, including a laminate including a solder strip; and a junction box arranged on a surface of the laminate and including a plate connected to the solder strip by laser soldering. The plate has a first region and a second region, in which a region covered by the solder strip on the plate is the first region, and a region not covered by the solder strip on the plate is the second region. A soldering seam formed by laser soldering includes a first soldering seam and a second soldering seam. The first soldering seam is located in the first region, and the first soldering seam extends through the solder strip into the plate along a thickness direction of the laminate. The second soldering seam is located in the second region, and the second soldering seam extends directly into the plate along the thickness direction of the laminate.

Abstract: A semiconductor light-emitting device includes a substrate having a first energy bandgap, a first semiconductor layers on the substrate, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer. The active layer includes a quantum well layer, and a first barrier layer between the first semiconductor layer and the quantum well layer. The first semiconductor layer has a second energy bandgap wider than the first energy bandgap. The quantum well layer has a third energy bandgap narrower than the first and second energy bandgaps. The second semiconductor layer has a fourth energy bandgap wider than the third energy bandgap. The substrate has a refractive index greater than a refractive index of the first semiconductor layer. The refractive index of the first semiconductor layer is not less than a refractive index of the first barrier layer.

Abstract: A light-emitting devise includes first and second type semiconductor layers, an active layer interposed therebetween, a current blocking layer disposed on the first type semiconductor layer and including a first strip portion, and a first electrode disposed on the current blocking layer and including a first electrode pad, a first electrode end portion distal from the first electrode pad, and a first electrode extension portion extending between the first electrode pad and the first electrode end portion. The first strip portion of the current blocking layer is located beneath the first electrode extension portion, and has a widened section having a width that gradually increases in a direction away from the first electrode pad.

Abstract: A light emitting device (LED) includes an n-doped semiconductor material layer, an active region including an optically active compound semiconductor layer stack configured to emit light located on the n-doped semiconductor material layer, a p-doped semiconductor material layer located on the active region, an anode contact contacting the p-doped semiconductor material layer, a reflector overlying and electrically connected to the anode contact, and a device-side bonding pad layer located on the reflector. The p-doped semiconductor material layer includes an electrically active region that is at least partially covered by the anode contact and an inactive region that an electrical conductivity less than 30% of the electrically active region.

Abstract: An optoelectronic device includes a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; a first insulating layer on the second semiconductor layer and including a plurality of first openings exposing the first semiconductor layer, wherein the first openings include a first group and a second group; a third electrode on the first insulating layer and including a first extended portion and a second extended portion, wherein the first extended portion and the second extended portion are respectively electrically connected to the first semiconductor layer through the first group of the first openings and the second group of the first openings, and wherein the number of the first group of the first openings is different from the number of the second group of the first openings; and a plurality of fourth electrodes on the second insulating layer and electrically connected to the second semiconductor layer, wherein in a

Abstract: An object is to provide a highly reliable light emitting device which is thin and is not damaged by external local pressure. Further, another object is to manufacture a light emitting device with a high yield by preventing defects of a shape and characteristics due to external stress in a manufacture process. A light emitting element is sealed between a first structure body in which a fibrous body is impregnated with an organic resin and a second structure body in which a fibrous body is impregnated with an organic resin, whereby a highly reliable light emitting device which is thin and has intensity can be provided. Further, a light emitting device can be manufactured with a high yield by preventing defects of a shape and characteristics in a manufacture process.

Abstract: A semiconductor light-emitting device includes a light-emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer which are sequentially stacked, a first insulating layer on the second semiconductor layer with a plurality of first openings having first widths and a plurality of second openings having second widths different from the first widths, a first electrode electrically connected to the first semiconductor layer through the first openings, a first sub-electrode layer between the second semiconductor layer and the first insulating layer, the first sub-electrode layer being exposed through the second openings, and a second sub-electrode layer on the first insulating layer, the second sub-electrode layer being connected to the first sub-electrode layer through the second openings, wherein a first distance between the first openings closest to each other is different from a second distance between the second openings closest to each other.

Abstract: Solid state transducer (“SST”) devices with selective wavelength reflectors and associated systems and methods are disclosed herein. In several embodiments, for example, an SST device can include a first emitter configured to emit emissions having a first wavelength and a second emitter configured to emit emissions having a second wavelength different from the first wavelength. The first and second emitters can be SST structures and/or converter materials. The SST device can further include a selective wavelength reflector between the first and second emitters. The selective wavelength reflector can be configured to at least substantially transmit emissions having the first wavelength and at least substantially reflect emissions having the second wavelength.

Abstract: A photocurable composition includes quantum dots, quantum dot precursor materials, a chelating agent, one or more monomers, and a photoinitiator. The quantum dots are selected to emit radiation in a first wavelength band in the visible light range in response to absorption of radiation in a second wavelength band in the UV or visible light range. The second wavelength band is different than the first wavelength band. The quantum dot precursor materials include metal atoms or metal ions corresponding to metal components present in the quantum dots. The chelating agent is configured to chelate the quantum dot precursor materials. The photoinitiator initiates polymerization of the one or more monomers in response to absorption of radiation in the second wavelength band.

Abstract: A light emitting device includes: a mounting substrate comprising a mounting substrate first surface; a first light emitting element configured to emit light having a first peak wavelength; a second light emitting element configured to emit light having a second peak wavelength longer than the first peak wavelength; a first light-transmissive member; and a first wavelength converting member located on the first light-transmissive member.

Abstract: Embodiments disclosed herein include micro light emitting device (LED) display panels and methods of forming such devices. In an embodiment, a display panel includes a display backplane substrate, a light emitting element on the display backplane, a transparent conductor over the light emitting element, a dielectric layer over the transparent conductor, and a color conversion device over the light emitting element. In an embodiment, the dielectric layer separates the transparent conductor from the color conversion device.

Abstract: A light-emitting diode (LED) package includes an LED chip on a substrate, an adhesive phosphor film on the LED chip, a cell lens on the adhesive phosphor film, and a lateral reflective layer covering respective lateral surfaces of the LED chip, the adhesive phosphor film, and the cell lens, a lateral surface of the lateral reflective layer being coplanar with a lateral surface of the substrate.

Abstract: The present application discloses a display panel and a manufacturing method thereof. The display panel manufacturing method includes forming an LED die including a sacrificial layer on an array substrate, and then coating black glue material on the array substrate. The black glue material covers the array substrate and a surface of the sacrificial layer away from the array substrate. Then, the black glue material and the sacrificial layer are heated, and the black glue material is cured to form a black glue layer such that the sacrificial layer is decomposed. The display panel and the manufacturing method thereof provided by the present application are for improving contrast of the display panel.

Abstract: The present disclosure relates to a light-emitting device. The light-emitting device includes a substrate, a first light-emitting chip, a first wavelength conversion member, and a barrier member. The first light-emitting chip is mounted on the substrate. The first wavelength conversion member covers the upper surface of the first light-emitting chip. A first reflective member covers the side surface of the first wavelength conversion member. Further, the barrier member includes an outer wall surrounding the side surfaces of the first light-emitting chip and the first reflective member.

Abstract: A display device may include a display panel including a pad disposed on a substrate and a driving unit including a bump electrically connected to the pad. The pad may include a first layer disposed on the substrate and including a conductive material, a second layer disposed on the first layer and including patterns arranged in a first direction and spaced apart from each other, and a third layer disposed on the second layer and including a conductive material. The first layer may include portions protruding toward the substrate and respectively corresponding to the patterns.

Abstract: Disclosed are a display panel and a display device. The display panel includes a base substrate. The base substrate is provided with bonding electrodes, Micro-LEDs are disposed on a side of the plurality of bonding electrodes facing away from the base substrate; and the plurality of Micro-LEDs are electrically connected to bonding electrodes in one-to-one correspondence. On a plane parallel to a plane where the base substrate is located, along a direction from a center of the base substrate to an edge of the base substrate, a size of each bonding electrode of the plurality of bonding electrodes gradually increases and/or a distance between centers of adjacent two of the plurality of bonding electrodes gradually increases to enable each Micro-LED of the plurality of Micro-LEDs to be bonded with a corresponding bonding electrode.

Abstract: A display device includes a substrate and a display element layer disposed on the substrate and emitting light. The display element layer includes a first electrode electrically connected to a portion of a first light emitting element, a second electrode electrically connected to another portion of the first light emitting element, and at least one insulating structure disposed on the substrate and having a convex shape protruding from the substrate. The first light emitting element is disposed in a space of the at least one insulating structure. A method of manufacturing the display device is also disclosed.

Abstract: A micro light emitting diode (LED) having a high light extraction efficiency includes a bottom conductive layer, a light emitting layer on the bottom conductive layer, and a top conductive structure on the light emitting layer. The micro LED additionally includes a conductive side arm electrically connecting the sidewall of the light emitting layer with the bottom conductive layer, and a reflective bottom dielectric layer arranged under the light emitting layer and above the bottom conductive layer. In some embodiments, the micro LED further includes an ohmic contact between the top conductive structure and the light emitting layer that has a small area and is transparent, thereby increasing the light emergent area and improving the light extraction efficiency.

Abstract: The invention refers to a method and an apparatus (20) for manufacturing of a prismatic unilaterally open battery cell container (21). First an extruded container (41) is formed from a slug (38) by extrusion. The slug (38) consists of a uniform material. The extruded container (41) is then formed by a first ironing in a first ironing station (25) and by a second ironing in a second ironing station (28). During ironing the container is moved by a respective ironing ram (26, 29) only partly through an associated die tool (27, 30) and is reversed when reaching a reversal point (U). After the second ironing a remaining edge (82) of the obtained intermediate container (77) is separated, thereby the battery cell container (21) is obtained.