Patents Issued in February 20, 2024
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Patent number: 11908737Abstract: There is provided a technique that performs: (a) forming a first metal film by supplying a plurality of times a first metal-containing gas and a first reducing gas without being mixed with each other to a substrate having a concave portion in a surface of the substrate; and (b) forming a second metal film on the first metal film by supplying a plurality of times at least a second metal-containing gas and a second reducing gas different from the first reducing gas without being mixed with each other or by simultaneously supplying at least a second metal-containing gas and a second reducing gas different from the first reducing gas, to the substrate.Type: GrantFiled: June 16, 2022Date of Patent: February 20, 2024Assignee: KOKUSAI ELECTRIC CORPORATIONInventor: Arito Ogawa
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Patent number: 11908738Abstract: A method of making a semiconductor component includes depositing a first metal material onto a structure having a first cavity and a second cavity such that the first metal material fills the first cavity and forms a first lining on exposed surfaces of the second cavity. The method further includes depositing a dielectric material onto the structure such that the dielectric material forms a second lining on exposed surfaces of the first lining. The method further includes depositing a second metal material onto the structure such that the second metal material fills remaining volume in the second cavity.Type: GrantFiled: October 18, 2021Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Nicholas Anthony Lanzillo, Chih-Chao Yang
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Patent number: 11908739Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.Type: GrantFiled: November 13, 2020Date of Patent: February 20, 2024Assignee: ADEIA SEMICONDUCTOR TECHNOLOGIES LLCInventor: Cyprian Emeka Uzoh
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Patent number: 11908740Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes source/drain structures on opposite sides of the gate structure. The semiconductor structure also includes a dielectric layer over the gate structure and the source/drain structures. The semiconductor structure also includes a via plug passing through the dielectric layer and including a first group IV element. The dielectric layer includes a second group IV element, a first compound, and a second compound, and the second compound includes elements in the first compound and the first group IV element.Type: GrantFiled: November 25, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Po Hsieh, Su-Hao Liu, Hong-Chih Liu, Jing-Huei Huang, Jie-Huang Huang, Lun-Kuang Tan, Huicheng Chang, Liang-Yin Chen, Kuo-Ju Chen
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Patent number: 11908741Abstract: The present invention provides a method for an improved protective coating for plasma dicing a substrate. A work piece having a support film, a frame and the substrate, the substrate having a top surface and a bottom surface, the top surface of the substrate having a plurality of device structures and a plurality of street areas is provided. The work piece is formed by adhering the substrate to a support film and then mounting the substrate with the support film to a frame. A composite material coating having a matrix component and a filler component is applied to the top surface of the substrate. The filler component has a plurality of particles. The composite material coating is removed from at least one street area to expose the street area. The exposed street area is plasma etched. The composite material coating is removed from the top surface of the substrate.Type: GrantFiled: January 24, 2023Date of Patent: February 20, 2024Assignee: Plasma-Therm LLCInventor: Russell Westerman
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Patent number: 11908742Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a semiconductor substrate, a first fin and a second fin extending from the semiconductor substrate, a first lower semiconductor feature over the first fin, a second lower semiconductor feature over the second fin. Each of the first and second lower semiconductor features includes a top surface bending downward towards the semiconductor substrate in a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins. The semiconductor device also includes an upper semiconductor feature over and in physical contact with the first and second lower semiconductor features, and a dielectric layer on sidewalls of the first and second lower semiconductor features.Type: GrantFiled: June 14, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
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Patent number: 11908743Abstract: Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.Type: GrantFiled: September 27, 2021Date of Patent: February 20, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huimei Zhou, Andrew M. Greene, Julien Frougier, Ruqiang Bao, Jingyun Zhang, Miaomiao Wang, Dechao Guo
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Patent number: 11908744Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure and a gate stack formed over the first fin structure and the isolation layer. The semiconductor device structure further includes a first source/drain structure formed over the first fin structure and spaced apart from the gate stack and a contact structure formed over the first source/drain structure. The semiconductor device structure includes a dielectric structure formed through the contact structure. In addition, the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer.Type: GrantFiled: August 9, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
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Patent number: 11908745Abstract: A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.Type: GrantFiled: March 13, 2023Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Hsiang Chan, Wen-Hung Huang, Shan-Mei Liao, Jian-Hao Chen, Kuo-Feng Yu, Kuei-Lun Lin
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Patent number: 11908746Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.Type: GrantFiled: August 28, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
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Patent number: 11908747Abstract: A method of processing a substrate includes forming a first layer stack on a substrate, the first layer stack including conductive layers and dielectric layers that alternate in the first layer stack. An opening is formed in the first layer stack, the opening extending through each of the conductive layers in the first layer stack such that sidewalls of each of the conductive layers are exposed within the opening. A second stack of layers is formed within the opening, the second stack of layers including channel layers of semiconductor material positioned in the second stack such that each channel layer contacts exposed sidewalls of a respective conductive layer of the first layer stack. Transistor channels are from the channel layers of the second stack such that each transistor channel extends between exposed sidewalls of a respective conductive layer within the opening.Type: GrantFiled: June 30, 2021Date of Patent: February 20, 2024Assignee: Tokyo Electron LimitedInventors: Mark I. Gardner, H. Jim Fulford
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Patent number: 11908748Abstract: A semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate and through the isolation feature in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate and through the isolation feature in the second region, and a second epitaxial feature over the second fin. A portion of the isolation feature located between the first fin and the second fin protrudes from a top surface of the isolation feature.Type: GrantFiled: November 15, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
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Patent number: 11908749Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.Type: GrantFiled: November 21, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu, Chih-Hsin Ko, Clement Hsingjen Wann
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Patent number: 11908750Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.Type: GrantFiled: May 28, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu Ling Liao, Chung-Chi Ko
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Patent number: 11908751Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.Type: GrantFiled: July 26, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Ying Chen, Sen-Hong Syue, Huicheng Chang, Yee-Chia Yeo
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Patent number: 11908752Abstract: A substrate processing apparatus that includes a substrate holder, a cup member, an elevating mechanism, a first nozzle, and a camera. The substrate holder holds a substrate and rotates the substrate. The cup member surrounds the outer circumference of the substrate holder. The elevating mechanism moves up the cup member so that the upper end portion of the cup member is located at the upper end position higher than the substrate held by the substrate holder. The first nozzle has a discharge port at a position lower than the upper end position, and discharges first processing liquid from the discharge port to an end portion of the substrate. The camera images an imaging region that includes the first processing liquid discharged from the discharge port of the first nozzle and is viewed from an imaging position above the substrate.Type: GrantFiled: September 25, 2019Date of Patent: February 20, 2024Assignee: SCREEN Holdings Co., Ltd.Inventors: Hideji Naohara, Yuji Okita, Hiroaki Kakuma, Tatsuya Masui
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Patent number: 11908753Abstract: Herein disclosed is a test head connection method, the method comprises the following steps. First, a load board and a card holder are provided between a test head and a probing machine, the card holder is disposed in the probing machine, and the card holder is used to accommodate the load board. A vacuum function of the test head is activated, and the test head is moved to align the card holder. The test head is moved to touch the load board in the card holder. At least one clamping piece is used to fix the test head and the card holder. Wherein the load board and a wafer are connected by direct probing.Type: GrantFiled: November 6, 2021Date of Patent: February 20, 2024Assignee: Chroma ATE Inc.Inventors: Kao-Shan Yang, Ching-Li Lin
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Patent number: 11908754Abstract: An etching apparatus is provided to be able to rotate or tilt a substrate holder on which a to-be-processed substrate is placed. According to a profile of a pre-process critical dimension of the substrate, the etching apparatus may rotate or tilt the substrate holder during an etching process in order to achieve a desired profile of a post-process critical dimension of the substrate that is related to the pre-process critical dimension.Type: GrantFiled: March 4, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jun Shimada, Chen-Fon Chang, Chih-Teng Liao
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Patent number: 11908755Abstract: In one example, a semiconductor device comprises a substrate comprising a top side, a bottom side, and a conductive structure, a body over the top side of the substrate, an electronic component over the top side of the substrate and adjacent to the body, wherein the electronic component comprises an interface element on a top side of the electronic component, a lid over the interface element and a seal between the top side of the electronic component and the lid, and a buffer on the top side of the substrate between the electronic component and the body. Other examples and related methods are also disclosed herein.Type: GrantFiled: February 21, 2020Date of Patent: February 20, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Sang Jae Jang, Weilung Lu, Burt Barber, Adrian Arcedera, Shingo Nakamura
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Patent number: 11908756Abstract: Techniques regarding qubit chip assemblies are provided. For example, one or more embodiments described herein can include an apparatus that can comprise a qubit chip positioned on an interposer chip. The apparatus can also comprise an electrical connector in direct contact with the interposer chip. The electrical connector can establish an electrical communication between a wire and a contact pad of the interposer chip that is coupled to the qubit chip.Type: GrantFiled: December 16, 2021Date of Patent: February 20, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Abraham, John Michael Cotte
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Patent number: 11908757Abstract: A chip package structure includes at least one semiconductor die attached to a redistribution structure, a first underfill material portion located between the redistribution structure and the at least one semiconductor die and laterally surrounding the solder material portions, a molding compound laterally surrounding at least one semiconductor die, and a second underfill material portion contacting sidewalls of the redistribution structure and sidewalls of the molding compound and including at least one cut region. The second underfill material portion includes a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.Type: GrantFiled: November 11, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chia-Kuei Hsu, Ming-Chih Yew, Shu-Shen Yeh, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11908758Abstract: A semiconductor package includes; a dual stiffener including an upper stiffener and a lower stiffener, an upper package including an upper package substrate, a semiconductor chip centrally mounted on an upper surface of the upper package substrate, and the upper stiffener disposed along an outer edge of the upper package substrate, and a lower package substrate that centrally mounts the upper package and includes the lower stiffener disposed on an upper surface of the lower package substrate to surround the upper package substrate.Type: GrantFiled: December 14, 2021Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Heungkyu Kwon, Junso Pak, Heeseok Lee
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Patent number: 11908759Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.Type: GrantFiled: March 3, 2021Date of Patent: February 20, 2024Assignee: MediaTek Inc.Inventors: Nan-Cheng Chen, Che-Ya Chou, Hsing-Chih Liu, Che-Hung Kuo
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Patent number: 11908760Abstract: A package is disclosed. In one example, the package comprises a carrier comprising a thermally conductive and electrically insulating layer, a laminate comprising a plurality of connected laminate layers, an electronic component mounted between the carrier and the laminate. An encapsulant is at least partially arranged between the carrier and the laminate and encapsulating at least part of the electronic component.Type: GrantFiled: January 13, 2022Date of Patent: February 20, 2024Assignee: Infineon Technologies AGInventor: Andreas Grassmann
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Patent number: 11908761Abstract: In one example, an electronic device comprises a base substrate comprising a base substrate conductive structure, a first electronic component over a first side of the base substrate, an encapsulant over the first side of the base substrate, wherein the encapsulant contacts a lateral side of the electronic component, an interposer substrate over a first side of the encapsulant and comprising an interposer substrate conductive structure, and a vertical interconnect in the encapsulant and coupled with the base substrate conductive structure and the interposer substrate conductive structure. A first one of the base substrate or the interposer substrate comprises a redistribution layer (RDL) substrate, and a second one of the base substrate or the interposer substrate comprises a laminate substrate. Other examples and related methods are also disclosed herein.Type: GrantFiled: January 20, 2023Date of Patent: February 20, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Seung Nam Son, Dong Hyun Khim, Jin Kun Yoo
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Patent number: 11908762Abstract: A temporary protective film comprising a support film and an adhesive layer provided on one surface or both surfaces of the support film is disclosed. The coefficient of linear expansion at 30° C. to 200° C. of the temporary protective film may be greater than or equal to 16 ppm/° C. and less than or equal to 20 ppm/° C. in at least one in-plane direction of the temporary protective film.Type: GrantFiled: March 1, 2019Date of Patent: February 20, 2024Assignee: RESONAC CORPORATIONInventors: Naoki Tomori, Tomohiro Nagoya, Takahiro Kuroda
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Apparatus having a functional structure delimited by a frame structure and method for producing same
Patent number: 11908763Abstract: An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure.Type: GrantFiled: September 23, 2021Date of Patent: February 20, 2024Assignee: INFINEON TECHNOLOGIES AGInventors: Prashanth Makaram, John Cooper, Joerg Ortner, Stephan Pindl, Caterina Travan, Alexander Zoepfl -
Patent number: 11908764Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.Type: GrantFiled: August 31, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Liang Lin, Po-Yao Chuang, Te-Chi Wong, Shuo-Mao Chen, Shin-Puu Jeng
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Patent number: 11908765Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor device and a heating structure. The semiconductor substrate includes a device region and a heating region surrounding the device region. The semiconductor device is located on the device region. The heating structure is located on the heating region and includes an intrinsic semiconductor area, at least one heating element and at least one heating pad. The intrinsic semiconductor area is surrounding the semiconductor device. The at least one heating element is located at a periphery of the intrinsic semiconductor area. The at least one heating pad is joined with the at least one heating element, wherein the at least one heating pad includes a plurality of contact structures, and a voltage is supplied from the plurality of contact structures to control a temperature of the at least one heating element.Type: GrantFiled: June 30, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tsung Shih, Chewn-Pu Jou, Stefan Rusu, Feng-Wei Kuo
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Patent number: 11908766Abstract: The present invention relates to a cooling system where a semiconductor component including a semiconductor chip and a cooling apparatus are joined, wherein a coolant is supplied to a substrate, on which a semiconductor chip is installed, through an opening member of the cooling apparatus so that a surface of the substrate may be directly cooled by the coolant so as to improve cooling efficiency, and a cooling post structure, which enables the coolant to smoothly flow, is used to further improve cooling efficiency.Type: GrantFiled: September 28, 2021Date of Patent: February 20, 2024Assignee: JMJ Korea Co., Ltd.Inventor: Yun Hwa Choi
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Patent number: 11908767Abstract: A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader.Type: GrantFiled: December 8, 2021Date of Patent: February 20, 2024Assignee: MEDIATEK INC.Inventors: Che-Hung Kuo, Hsing-Chih Liu, Chia-Hao Hsu
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Patent number: 11908768Abstract: Forming aluminum circuit layers forming an aluminum circuit layers on one surface of a ceramic substrate and forming copper circuit layers are included. The copper circuit layers are formed by laminating copper boards for the circuit layers on the respective aluminum circuit layers, arranging the laminate between a pair of support boards having a convex curved surface at least on one surface so as to face to each other, moving the support boards in a facing direction to press the laminate in a lamination direction, and heating in this pressing state so that the copper boards for the circuit layers are bonded on the aluminum circuit layers respectively by solid phase diffusion. In the step of forming the copper circuit layers, the support boards are arranged so that either one of the convex curved surface is in contact with the adjacent copper boards for the circuit layers in the laminate.Type: GrantFiled: February 15, 2022Date of Patent: February 20, 2024Assignee: MITSUBISHI MATERIALS CORPORATIONInventors: Ryohei Yumoto, Tomoya Oohiraki, Takeshi Kitahara, Yoshiyuki Nagatomo
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Patent number: 11908769Abstract: Example superlattice structures and methods for thermoelectric devices are provided. An example structure may include a plurality of superlattice periods. Each superlattice period may include a first material layer disposed adjacent to a second material layer. For each superlattice period, the first material layer may be formed of a first material and the second material layer may be formed of a second material. The plurality of superlattice periods may include a first superlattice period and a second superlattice period. A thickness of a first material layer of the first superlattice period may be different than a thickness of a first material layer of the second superlattice period.Type: GrantFiled: December 23, 2020Date of Patent: February 20, 2024Assignee: The Johns Hopkins UniversityInventors: Rama Venkatasubramanian, Jonathan M. Pierce, Geza Dezsi
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Patent number: 11908771Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.Type: GrantFiled: November 12, 2021Date of Patent: February 20, 2024Assignee: Infineon Technologies AGInventors: Jayaganasan Narayanasamy, Angel Enverga, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
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Patent number: 11908772Abstract: Provided is a semiconductor module including a semiconductor device and a cooling apparatus, wherein the semiconductor device includes semiconductor chips, circuit boards where the semiconductor chips are implemented, and a resin structure for sealing the semiconductor chips; the cooling apparatus includes a top plate, a side wall, a bottom plate, a coolant flow portion, a plurality of fins and reinforcement pins; the metal layer has a part overlapped with the cooling region, and other parts other than the part overlapped with one communication region of the first communication region and the second communication region in planar view; and the reinforcement pins are arranged in the one communication region.Type: GrantFiled: February 24, 2021Date of Patent: February 20, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takafumi Yamada, Hiromichi Gohara
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Patent number: 11908773Abstract: An element module includes an element, a plurality of conductive members, and a spacer member. The plurality of conductive members are connected to the element and arranged in a predetermined direction. The spacer member is disposed between two conductive members of the plurality of conductive members adjacent to each other in the predetermined direction and is in contact with parts of the two conductive members.Type: GrantFiled: July 30, 2019Date of Patent: February 20, 2024Assignee: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATIONInventor: Kento Kuwabara
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Patent number: 11908774Abstract: A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.Type: GrantFiled: June 27, 2022Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Heeseok Lee, Yunhyeok Im
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Patent number: 11908775Abstract: A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.Type: GrantFiled: December 22, 2021Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jaewon Hwang, Kwangjin Moon, Hojin Lee, Hyungjun Jeon
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Patent number: 11908776Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.Type: GrantFiled: January 6, 2021Date of Patent: February 20, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Nazila Dadvand, Sreenivasan Koduri
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Patent number: 11908777Abstract: A semiconductor device includes a semiconductor chip, a plurality of leads that each includes a lead body portion which has a mounting portion which includes an upper surface whereon a semiconductor chip is bonded, and a lead connecting portion for external connection which projects downward from a lower surface of the lead body portion, a first sealing resin that seals a space that is defined by each lead body portion and each lead connecting portion of the plurality of leads in a region below the upper surface of each lead body portion of the plurality of leads, and a second sealing resin that seals the semiconductor chip in a region above the upper surface of each lead body portion of the plurality of leads.Type: GrantFiled: May 27, 2022Date of Patent: February 20, 2024Assignee: ROHM CO., LTD.Inventor: Mamoru Yamagami
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Patent number: 11908778Abstract: A semiconductor module includes: a semiconductor element having a first main electrode and a second main electrode; a first conductive member and a second conductive member connected to the first main electrode and the second main electrode, respectively, and placed to sandwich the semiconductor element; and a main terminal including a first main terminal continuous from the first conductive member and a second main terminal continuous from the second conductive member. The main terminal has a facing portion, a non-facing portion, a first connection portion, and a second connection portion. In a width direction, a formation position of the second connection portion overlaps with a formation position of the first connection portion.Type: GrantFiled: September 8, 2021Date of Patent: February 20, 2024Assignee: DENSO CORPORATIONInventors: Hiroshi Ishino, Ryota Miwa, Shoichiro Omae, Takuo Nagase
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Patent number: 11908779Abstract: A semiconductor package structure includes a substrate comprising a land structure. The land structure includes a first land section having a first height in a cross-sectional view and a second land section having a second height in the cross-sectional view that is different than the first height. A mold encapsulant is disposed adjacent a lateral portion of the first land section and is disposed below a bottom portion of the second land section. A semiconductor die is attached to the substrate, and includes a first major surface, a second major surface opposing the first major surface, and an outer perimeter. The semiconductor die further includes a bonding structure disposed adjacent the first major surface, which is coupled to the second land section such that the first land section is disposed outside the perimeter of the semiconductor die A mold member encapsulates at least portions of the semiconductor die.Type: GrantFiled: April 19, 2021Date of Patent: February 20, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Kyoung Yeon Lee, Byong Jin Kim, Jae Min Bae, Hyung Il Jeon, Gi Jeong Kim, Ji Young Chung
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Patent number: 11908780Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.Type: GrantFiled: November 3, 2021Date of Patent: February 20, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jonathan Almeria Noquil, Satyendra Singh Chauhan, Lance Cole Wright, Osvaldo Jorge Lopez
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Patent number: 11908781Abstract: At least some embodiments of the present disclosure relate to a semiconductor package structure. The semiconductor package structure includes a substrate with a first surface, an encapsulant, an electronic component, and a patterned conductive layer. The encapsulant is disposed on the first surface of the substrate. The encapsulant includes a first surface and a second surface. The patterned conductive layer extends on the first surface and the second surface of the encapsulant and protrudes from the first surface and the second surface of the encapsulant. The electronic component is disposed on the patterned conductive layer.Type: GrantFiled: March 22, 2021Date of Patent: February 20, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Chih Cho, Chun-Hung Yeh, Tsung-Wei Lu
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Patent number: 11908782Abstract: An electronic assembly and methods of making the assembly are disclosed. The electronic assembly includes a substrate with an elastic member having an intrinsic stress profile. The elastic member has an anchor portion on the surface of the substrate; and a free end biased away from the substrate via the intrinsic stress profile to form an out of plane structure. The substrate includes one or more spacers on the substrate. The electronic assembly includes a chip comprising contact pads. The out of plane structure on the substrate touches corresponding contact pads on the chip, and the spacers on the substrate touch the chip forming a gap between the substrate and the chip.Type: GrantFiled: March 22, 2021Date of Patent: February 20, 2024Assignee: XEROX CORPORATIONInventors: Christopher L. Chua, Qian Wang, Yu Wang, Eugene M. Chow
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Patent number: 11908783Abstract: Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.Type: GrantFiled: October 21, 2021Date of Patent: February 20, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventor: Naoki Hayashi
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Patent number: 11908784Abstract: A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.Type: GrantFiled: September 23, 2020Date of Patent: February 20, 2024Assignee: NXP USA, Inc.Inventors: Akhilesh Kumar Singh, Andrew Jefferson Mawer, Nishant Lakhera, Chee Seng Foong, Nihaar N. Mahatme
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Patent number: 11908785Abstract: A semiconductor device includes: a first board that has a first end surface and a second end surface opposite to the first end surface; a second board that is attached to the second end surface of the first board; a plurality of first electrodes that are provided on the first end surface; a second electrode that is provided on the second end surface and electrically coupled to an electrode of the second board; an internal wiring that is provided inside the first board and electrically coupled to the second electrode; a plurality of third electrodes that are provided inside the first board and electrically couple the first electrodes to the internal wiring; and a strain sensor that is provided inside the first board and measures a strain generated in the first board, in which a linear expansion coefficient of each of the third electrodes is larger than a linear expansion coefficient of the first board.Type: GrantFiled: April 23, 2021Date of Patent: February 20, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takeru Tamari, Daisuke Sakurai, Kiyokazu Itoi
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Patent number: 11908786Abstract: A wiring structure includes a test pattern layer. The test pattern layer includes a test circuit pattern and a heat dissipating structure. The heat dissipating structure is disposed adjacent to the test circuit pattern, and is configured to reduce temperature rise of the test circuit pattern when a power is applied to the test circuit pattern.Type: GrantFiled: February 18, 2022Date of Patent: February 20, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Ting Wei Hsu
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Patent number: 11908787Abstract: A package structure includes a first and a second conductive feature structures, a die, an insulator, an encapsulant, an adhesive layer, and a first through via. The die is located between the first conductive feature structure and the second conductive feature structure. The die is electrically connected to the second conductive feature structure. The insulator is disposed between the die and the first conductive feature structure. The insulator has a bottom surface in physical contact with a polymer layer of the first conductive feature structure. The encapsulant is located between the first conductive feature structure and the second conductive feature structure. The encapsulant is disposed on the insulator and laterally encapsulates the die and the insulator. The adhesive layer is disposed between the die and the insulator. The first through via extends through the encapsulant to connect to the first conductive feature structure and the second conductive feature structure.Type: GrantFiled: February 22, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuei-Tang Wang, Chun-Lin Lu, Kai-Chiang Wu