Abstract: A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure.

Abstract: A 3D device, the device including: at least a first level including logic circuits; and at least a second level bonded to the first level, where the second level includes a plurality of transistors, where the device include connectivity structures, where the connectivity structures include at least one of the following: a. differential signaling, or b. radio frequency transmission lines, or c. Surface Waves Interconnect (SWI) lines, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions.

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Abstract: Disclosed herein is a micro light emitting diode (microLED) display structure with emission from the back side of a transparent substrate, which can be manufactured by fluidic assembly. The architecture allows microLED displays or display tiles to be fabricated simply, with processing and interconnection only on one side of the backplane. The structure may incorporate reflectors in the fluidic assembly structures to direct substantially all of the emitted light toward the viewer. Also disclosed are microLEDs and emission backplanes designed to support a back emission display.

Abstract: Disclosed are embodiments of apparatus and methods that provide light emitting displays with improved wide angle color viewing. A plurality of light emitting elements is arranged in a predetermined pattern and collectively creates a viewing plane. A portion of the light emitting elements are disposed in a primary orientation while the remainder of the light emitting element are disposed in a complementary orientation. Each light emitting element in a primary orientation is adjacent to a light emitting element in the complementary orientation. The spatial light emission pattern of the primary orientation is complementary to the spatial light emission pattern of the complementary orientation. Adjacent pairs of primary-complementary oriented light emitting elements cancel a substantial amount of color variation that would otherwise be seen when one varies the gaze angle upon the viewing plane.

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first alignment pattern having a plurality of first scale patterns arranged in a first direction. The second semiconductor device is mounted over the first semiconductor device and includes a second alignment pattern having a plurality of second scale patterns arranged in a second direction parallel to the first direction, and a scale pitch of the first scale patterns is different from a scale pitch of the second scale patterns.

Abstract: This disclosure relates to embodiments that include an apparatus that may comprise a first layer including a first plurality of active devices, a second layer including a second plurality of active devices, and/or a third layer including a plurality of passive devices and disposed between the first and the second layers. An active device of the first plurality of active devices and an active device of the second plurality of active devices may influence a state of charge of a passive device of the plurality of passive devices.

Abstract: A display device includes: a base layer having a first area and a second area extending at least partially around a periphery of the first area; conductive patterns in the second area; an insulating layer over the conductive patterns in the second area; a first electrode and a second electrode on the insulating layer; and a plurality of light emitting elements between the first electrode and the second electrode in the first area and being connected to the first electrode and the second electrode. The first electrode and the second electrode are spaced apart from each other in the first area and are respectively connected to portions of the conductive patterns through contact openings penetrating the insulating layer. The light emitting elements do not overlap the conductive patterns and the insulating layer.

Abstract: A display may include light-emitting components such as light-emitting diodes on a transparent substrate. Conductive signal paths between the light-emitting components, driver integrated circuits for controlling the light-emitting components, and the light-emitting components themselves may be opaque. To mitigate diffraction artifacts caused by the opaque components, the opaque footprint of the display may be selected to include non-periodic portions. The non-periodic portions increase randomness and reduce periodicity within the opaque footprint, which mitigates perceptible diffraction artifacts when viewing the display. One or both of the component mounting portions and interconnect portions of the opaque footprint may be non-periodic. The component mounting portions may have random shapes. The interconnect portions may follow random paths between the component mounting portions.

Abstract: An image display element includes micro light emitting elements disposed in an array on a driving circuit substrate. An excitation light emitting element includes a main body including a compound semiconductor, a metal electrode disposed on a side of the main body located closer to the driving circuit substrate, and a transparent electrode disposed on an opposite side to the driving circuit substrate, and a light emission layer included in the main body is disposed on a side opposite to the driving circuit substrate from a center portion of the main body.

Abstract: A display device and a method of fabricating a display device are provided. The display device includes a substrate comprising a contact area and a line area, a first electrode that extends in a first direction on the substrate, a first electrode pattern that extends in the first direction and is spaced apart from the first electrode on the substrate, a second electrode that extends in the first direction and is between the first electrode and the first electrode pattern on the substrate, a second electrode pattern that extends in the first direction and is between the first electrode and the second electrode on the substrate, and a first light-emitting element between the first electrode and the second electrode pattern in the contact area.

Abstract: A display device includes electrodes disposed on a substrate, extended in a first direction, and spaced apart from one another in a second direction intersecting the first direction, and light-emitting elements having ends disposed on the electrodes, wherein the electrodes include a first electrode having a first portion and a second portion, and a floating electrode adjacent to the first portion of the first electrode, and a width of the second portion is greater than a width of the first portion in the second direction.

Abstract: A display device with high resolution is provided. A display device with high display quality is provided. The display device includes a substrate, an insulating layer, a plurality of transistors, and a plurality of light-emitting diodes. The plurality of light-emitting diodes are provided in a matrix over the substrate. Each of the plurality of transistors is electrically connected to at least one of the plurality of light-emitting diodes. The plurality of light-emitting diodes are positioned closer to the substrate than the plurality of transistors are. The plurality of light-emitting diodes emit light toward the substrate. Each of the plurality of transistors includes a metal oxide layer and a gate electrode. The metal oxide layer includes a channel formation region. The top surface of the gate electrode is substantially level with the top surface of the insulating layer.

Abstract: A method for forming a semiconductor device includes: forming a fin structure protruding from a substrate of the semiconductor device; forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a first recess and a second recess; forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the first recess, wherein the first conductive line extends across the fin structure and wraps a portion of the fin structure; and forming a second conductive line in the same layer as the first conductive rail by filling a second conductive material into the second recess, wherein the second conductive line extends across the fin structure and contacts another portion of the fin structure.

Abstract: An integrated circuit includes a first transistor, a horizontal routing track extending in a first direction in a first metal layer, and a via connector conductively connecting the horizontal routing track to a first terminal of the first transistor. The integrated circuit also includes a backside routing track extending in the first direction in a backside metal layer, and a backside via connector conductively connecting the backside routing track to a second terminal of the first transistor. The backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. In the integrated circuit, either the first terminal or the second terminal is a gate terminal of the first transistor.

Abstract: An integrated circuit includes a cell layer including a first cell and a second cell, a first metal layer over the cell layer and having a first conductive feature, a second metal layer over the first metal layer and having a second conductive feature, and a first via between the first metal layer and the second metal layer and connecting the first conductive feature to the second conductive feature. The first conductive feature spans over a boundary between the first and second cells, and has a lengthwise direction along a first direction. The second conductive feature spans over the boundary between the first and second cells, and has a lengthwise direction along a second direction that is perpendicular to the first direction.

Abstract: A display device includes a substrate that includes a display area and a peripheral area outside the display area, a display element on the display area, a peripheral circuit on the peripheral area, the peripheral circuit including a thin film transistor, a first shielding layer on the peripheral circuit. and a second shielding layer on the first shielding layer. At least one of the first shielding layer and the second shielding layer includes a hole. One shielding layer of the first shielding layer and the second shielding layer includes the hole and overlaps the other one of the first shielding layer and the second shielding layer.

Abstract: A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

Abstract: Structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation. A semiconductor body includes a cavity, first and second gate structures extending over the semiconductor body, and a semiconductor layer including first and second sections on the semiconductor body. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section on the semiconductor layer is laterally positioned between the cavity and the second gate structure. An isolation structure is laterally positioned between the first and second sections of the semiconductor layer. The isolation structure includes a dielectric layer and a sidewall spacer having first and second sections. The dielectric layer includes a first portion in the cavity and a second portion between the first and second sections of the sidewall spacer.

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.

Abstract: A semiconductor device is disclosed. The semiconductor device may include an active pattern on a substrate, source/drain patterns on the active pattern, a fence spacer on side surfaces of each of the source/drain patterns, a channel pattern interposed between the source/drain patterns, a gate electrode crossing the channel pattern and extending in a first direction, and a gate spacer on a side surface of the gate electrode. A first thickness of an upper portion of the fence spacer in the first direction may be greater than a second thickness of the gate spacer in a second direction crossing the first direction.

Abstract: A FinFET is provided. The FinFET includes a substrate including an NMOS (N-type metal-oxide-semiconductor) region; a plurality of fins formed on the substrate; an isolation layer formed between adjacent fins of the plurality of fins and on the substrate; a gate structure across a length portion of the fin and covering a portion of each of a top surface and sidewalls of the fin; and an in-situ doped epitaxial layer formed on each of the etched fin on both sides of the gate structure. The doping ions in the in-situ doped epitaxial layer are N-type ions.

Abstract: A transistor device includes a substrate, a fin structure extending on the substrate in a direction parallel to a top surface of the substrate, a source region and a drain region provided at an upper portion of the fin structure, a constant current generating layer provided at a lower portion of the fin structure, a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure, and a gate electrode provided on the gate insulating film, wherein the gate electrode is provided on the fin structure and between the source region and the drain region, the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate. The substrate includes a first region, a second region, and an isolation region between the first region and the second region. The semiconductor structure also includes a first fin, a second fin and a third fin disposed over the first region, the second region, and the isolation region, respectively. Further, the semiconductor structure includes a gate structure. The gate structure includes a first work function layer over the first region and a first portion of the isolation region, and a second work function layer over the second region and a second portion of the isolation region. An interface where the first work function layer is in contact with the second work function layer is located over a top surface of the third fin.

Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.

Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.

Abstract: An electronic device is disclosed, which includes: a substrate; a first metal layer, disposed on the substrate and having a first hole; a second metal layer, disposed on the substrate and having a second hole; a light detecting element for detecting a light passing through the first hole and the second hole; a transistor, disposed on the substrate; and a light shielding layer, disposed between the substrate and the transistor.

Abstract: A TFT array substrate includes a substrate layer and a metal layer disposed on the substrate layer. The metal layer includes a metal layer bridging structure having a first metal layer and a bridging second metal layer. An insulating layer is disposed between the first metal layer and the bridging second metal layer. The first metal layer includes two segments of a first segment and a second segment of the first metal layer, which are disposed at intervals. The first segment and the second segment of the first metal layer are connected by the bridging second metal layer. The TFT array substrate has a bending region adopting a new metal layer routing structure, and routing of the first metal layer in the bending region is prevented from passing through two holes of a filling layer (OILD), thereby effectively reducing the risk of subsequent breakage due to over-etching.

Abstract: A flexible display device includes: a flexible substrate; a semiconductor layer on the flexible substrate, the semiconductor layer including a polycrystalline semiconductor; a gate insulation layer on the semiconductor layer; and a gate electrode on the gate insulation layer, the gate electrode overlapping a channel region of the semiconductor layer in a plan view, wherein the semiconductor layer includes a source region and a drain region that are at opposite sides of the channel region, wherein the channel region includes a first region contacting the source region and a second region contacting the drain region, and wherein a channel width of the first region is greater than a channel width of the second region.

Abstract: A display device includes: a substrate; a first scan line arranged along a first direction on the substrate; a shield electrode overlapping a part of the first scan line in a direction that is perpendicular to a plane of the substrate; a second connection electrode on the shield electrode; and a data line arranged along a second direction on the second connection electrode, and connected with the second connection electrode, wherein the shield electrode overlapping the first scan line and the second connection electrode in a direction that is perpendicular to a plane of the substrate.

Abstract: An active matrix substrate including a resin substrate including a plurality of external connection terminals arranged near a display region, the active matrix substrate includes: a plurality of first lead wires each extending from one of the external connection terminals to the display region; and a plurality of second lead wires each extending from one of the external connection terminals to a separation line, the second lead wires being arranged with an arrangement pitch along the separation line, and the arrangement pitch of the second lead wires being greater than an arrangement pitch of the first lead wires.

Abstract: An embodiment of a display device includes a substrate, a semiconductor layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a first storage electrode, a first interlayer insulating layer, a second interlayer insulating layer, a data line, and a driving voltage line. The semiconductor layer is disposed on the substrate. The first gate insulating layer is disposed on the semiconductor layer. The gate electrode is positioned on the first insulating layer. The second gate insulating layer is disposed on the gate electrode. The first storage electrode is positioned on the second gate insulating layer. The first interlayer insulating layer is disposed on the first storage electrode and has an opening surrounding the semiconductor layer, the gate electrode, and the first storage electrode. The second interlayer insulating layer is disposed on the first interlayer insulating layer and fills the opening.

Abstract: A display panel and a display device are provided. A retaining wall is disposed on a middle position of a driver circuit layer, the retaining wall can prevent an insulating film from overlapping a whole sealing layer in an insulating film coating process, which improves adhesion of the display panel and reliability against high temperature and high humidity, thereby improving quality of the display panel.

Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.

Abstract: A colored film has an uneven structure on a surface thereof, in which an average distance between adjacent projections in the uneven structure is equal to or shorter than 1,500 nm, a standard deviation of the distance between the adjacent projections is 10 to 300 nm, and 95.00% or more of the projections satisfy Formula (1), in Formula (1), h represents a height of the projections, and D represents an average distance between the adjacent projections, Formula (1) 3h/D?1.0.

Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.

Abstract: An imaging device includes a first substrate including a pixel array and a first multilayer wiring layer. The first multilayer wiring layer includes a first wiring that receives electrical signals based on electric charge generated by at least one photoelectric conversion unit, and a plurality of second wirings. The imaging device includes a second substrate including a second multilayer wiring layer and a logic circuit that processes the electrical signals. The second multilayer wiring layer includes a third wiring bonded to the first wiring, and a plurality of fourth wirings. At least one of the plurality of fourth wirings being bonded to at least one of the plurality of second wirings. The second multilayer wiring layer includes at least one fifth wiring that is connected to the plurality of fourth wirings and that receives a power supply signal.

Abstract: A first region includes a plurality of first transfer column regions distributed in a first direction. A second region includes a plurality of second transfer column regions distributed in the first direction. The second region is positioned downstream of the first region in a charge transfer direction in the second transfer section. Lengths in a second direction of the plurality of first transfer column regions are equal. Lengths in the second direction of the plurality of second transfer column regions are longer than the length of the first transfer column region, and increase as the second transfer column region is positioned downstream in the charge transfer direction. A third region is disposed to correspond to the first region and extends along the first direction.

Abstract: A display apparatus is provided. The display apparatus includes a display substrate, a first micro LED module disposed on the display substrate, and a second micro LED module disposed on the display substrate and adjacent to the first micro LED module. The first micro LED module and the second micro LED module have side surfaces facing each other. The side surfaces facing each other of the first micro LED module and the second micro LED module are inclined in an identical direction with respect to an upper surface of the display substrate.

Abstract: A display device of the invention includes pixels each connected to at least one of scan lines and at least one of emission lines, a scan driver providing scan signals to the scan lines, and an emission driver including stages connected to the emission lines, each of the stages providing an emission signal to a corresponding emission line. A first stage among the stages includes a first transistor including a first electrode connected to a first power source line, a second electrode connected to a first emission line, and a gate electrode connected to a first scan line, and a second transistor including a first electrode connected to a first node and a second electrode connected to the first emission line.

Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The i magnetic element is wider than the isolation element. The semiconductor device structure further includes a conductive line over the isolation element.

Abstract: A power converter is embodied on a semiconductor substrate member and has a first region with a passive electrical component with a first electrically conductive layer pattern of an electrically conductive material and a second electrically conductive layer pattern of an electrically conductive material deposited on respective sides of the semiconductor substrate member. A trench or through-hole is formed (by etching) in the substrate within the first region, and the electrically conductive material is deposited at least on a bottom portion of the trench or on a sidewall of the through-hole and electrically connected to one or both of the first conductive layer pattern and the second conductive layer pattern. A second region has an active semiconductor component integrated with the semiconductor substrate by being fabricated by a semiconductor fabrication process. There is also provided a power supply, such as a DC-DC converter, embedded the semiconductor substrate member.

Abstract: Provided are a capacitor and a semiconductor device including the capacitor. The capacitor includes a first electrode; a plurality of dielectric films on the first electrode in a sequential series, the plurality of dielectric layers having different conductances from each other; and a second electrode on the plurality of dielectric films, wherein the capacitor has a capacitance which converges to a capacitance of one of the plurality of dielectric films.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes a substrate extending along a first direction to define a length, a second direction orthogonal to the first direction to define a width, and a third direction orthogonal to the first and second direction to define a height. The substrate includes a first capacitance region and a second capacitance region. The first capacitance region has a first maximum operating voltage (Vmax) and the second capacitance region has a second Vmax that is greater than the first Vmax.