Abstract: Provided is a level shifter circuit that changes a voltage of a high-frequency input signal to output. Provided is a level shifter circuit provided with a first input terminal and a second input terminal to each of which an input signal having a level between a first potential level and a first reference potential level is input, a first output terminal and a second output terminal from each of which an output signal having a level between a second potential level higher than the first potential level and a second reference potential level is output, a second potential supply node that supplies a voltage at the second potential level, a reference potential supply node that supplies a voltage at the second reference potential level, first and second impedance elements, first to fourth transistors, and first and second nodes, in which each of the first impedance element and the second impedance element includes at least three terminals.

Abstract: For reading out a state of a qubit, a readout input waveform is injected into a system that comprises an information storage element for storing the state of the qubit and a readout resonator that is electromagnetically coupled to said information storage element. A readout output waveform is extracted from said system and detected. The injection of the readout input waveform takes place through an excitation port that is also used to inject excitation waveforms to the information storage element for affecting the state of the qubit. A phase of the readout input waveform is controllably shifted in the course of injecting it into the system.

Abstract: An integrated circuit is provided, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.

Abstract: The power of a semiconductor device is reduced. The semiconductor device includes a latch circuit composed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a plurality of clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. In a period during which “H” is supplied to a first clock signal, the potential of the first capacitor is updated on the basis of the results of decoding performed by the first circuit. In a period during which “H” is supplied to a second clock signal, the potential of the second capacitor is updated on the basis of the potential of the first capacitor, and the potential of the second capacitor is supplied as a first output signal to the first output terminal.

Abstract: Laboratory equipment with flammable refrigerant and connected to at least two different electrical potentials for supplying the equipment with electrical energy. An electrical switch arrangement has first and second switches for electrical separation from, respectively, the first and second potentials. A sequence controller switches on the first switch and thereafter the second switch. A monitoring device is connected via a first contact on the equipment side to the first switch and via a second contact on the mains side to an electrical potential other than the first electrical potential for detecting a switched-on state of the first switch and signaling the detection to the sequence controller. When the monitoring device signals a switched-on state, the sequence controller blocks operation of the equipment as a function of the signaled switched-on state and whether the first switch is expected to be switched on or switched off.

Abstract: A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.

Abstract: A method and apparatus for generating an RF signal uses digital signal components to generate a synthesized RF signal having a plurality of frequency components. An analog filter is used to filter the synthesized RF signal. The analog filter is a tunable, active feedback circuit having one or more variable resonators and a variable gain block connected in a signal loop that is defined by a passband. The analog filter is tuned such that the passband of the analog filter overlaps one or more desired frequency components of the plurality of frequency components of the synthesized RF signal, and such that the passband has a relative bandwidth of about 1% or less.

Abstract: An input driven self-clocked dynamic comparator, and associated systems and methods are described herein. In one embodiment, self-clocked dynamic comparator, includes a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT?) signal. The self-clocked dynamic comparator also includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF. The self-clocked dynamic comparator further includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF, and a logic gate configured to receive the TRI signal and one of the OUT+ signal and OUT? signal, and configured to output the CLKsf signal. The cycles of the CLKsf signal cause the latch to dissipate energy.

Abstract: Devices and methods are described herein for a pulse amplitude modulation (PAM) driver. In one embodiment, the PAM driver includes a first high-speed buffer configured to output a first voltage, a second high-speed buffer configured to output a second voltage, and a plurality of transistors coupled to the first high-speed buffer and the second high-speed buffer. At least one of the first voltage or the second voltage facilitates selective operation of a transistor of the plurality of transistors to output a third voltage.

Abstract: A multi-feedback circuit that compares a duty cycle corrected reference clock fREF, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32×, 4×, etc.) of the frequency of fREF with approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.

Abstract: A clocking circuit is provided using a master delay-locked loop (DLL) and a slave DLL. A master DLL code indicates a delay adjustment made at a master DLL. A delay of a slave DLL is adjusted based on the master DLL code. A replica phase detector at the slave DLL is temporarily enabled during an interface idle period. A slave DLL code is determined, and a configuration value is determined based on the slave DLL code to the master DLL code. The replica phase detector is then disabled.

Abstract: A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.

Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive an oscillator signal from phase-locked loop circuitry. The phase-locked loop circuitry may include a digital or analog phase-locked loop having a first frequency divider, a ring oscillator, and an auxiliary phase noise cancellation loop coupled to the ring oscillator. The auxiliary phase noise cancellation loop may include at least a time-to-digital converter, a second frequency divider, an amplifier, and a bandpass filter configured to reject thermal and quantization noise associated with the time-to-digital converter. The first frequency divider may have a first division ratio, whereas the second frequency divider may have a second division ratio that is less than the first division ratio to provide faster phase noise correction.

Abstract: A system and method to dynamically control a reset signal for an IQ divider are provided. The system includes an IQ divider configured to output a IQ divider output clock; an input configured to receive a reference clock; a failure sensing circuit configured to sense a failure in the IQ divider output clock, the failure sensing circuit including an automatic frequency calibration (AFC) logic; and a control circuit configured to control a reset signal provided to the IQ divider, based on an output of the failure sensing circuit corresponding the failure sensed by the failure sensing circuit.

Abstract: A SerDes module clock network architecture comprises, a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop. The reference lock input port receives an input clock and conveys the input clock to the phase locked loop, the phase locked loop receives the input lock and outputs a PLL output clock signal, the PLL output clock signal is conveyed to the plurality of data transmission channels, and the PLL output clock signal is conveyed to the frequency division branches, and after frequency division, user interface clocks are output and conveyed to the user logic interfaces. When the PLL output clock signal in a SerDes is provided to an internal dedicated channel, several frequency division branches are also divided, and after frequency division, the signal is output to the user logic interfaces for use by an FPGA.

Abstract: A Phase Locked Loop (PLL) with reduced jitter includes: a phase detector, for comparing the phases of a reference clock and feedback clock to generate up and down control signals; a Voltage Controlled Oscillator (VCO) for generating an oscillation signal; an output divider, for dividing the oscillation signal to generate an output clock; a fractional feedback divider for receiving the oscillation signal and performing frequency division on the oscillation signal according to a modulated sequence to generate a modulated clock; and a divider coupled in series to the fractional feedback divider, for dividing the modulated clock of the fractional feedback divider by a fixed modulus to generate a divided clock. A frequency of the modulated clock of the fractional feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and divided clock is used as the feedback clock.

Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

Abstract: Embodiments disclosed herein may reduce or even eliminate spurs introduced into the signals during analog to digital or digital to analog conversions. The spurs may be introduced by components such as clocks of the converter circuits. In an analog to digital conversion, the input signal may be split into two parts: the first portion passing through a first analog to digital converter (ADC) and an inverted second portion passing through a second ADC. A digital subtractor may subtract the output of the second ADC from the output of the first ADC converter thereby reducing the spurs. In digital to analog conversion, a digital input is passed through a first digital to analog converter (DAC) and an inverted digital input is passed through a second DAC. The output of the second DAC is inverted and combined with the output of the first DAC to reduce the spurs.

Abstract: A failure determination device: acquires a second digital value indicating a difference between an analog electrical output generated by inputting a first digital value incremented at a first time interval to a DA conversion circuit and a target output indicated by the first digital value at a second time interval; and determines whether the DA conversion circuit has a failure based on a signal strength in a predetermined frequency of the second digital value that is a discrete signal.

Abstract: A semiconductor integrated circuit has a digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of a second wiring which is discharged when multiplication data of first data stored in a memory cell and second data on a first wiring is a first logic; and a transition timing detector that detects a timing at which the logic of the binary signal transitions.

Abstract: A circuit portion comprising a clock domain is disclosed. A first clock is arranged to clock components in the clock domain. An analogue to digital converter is clocked by a second clock with a duty cycle. The second clock is derived from the first clock. The analogue to digital converter is arranged to output a feedback signal upon finishing a conversion of a sample, and the feedback signal is arranged to control the duty cycle.

Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.

Abstract: A data encoding device suitable for encoding a plurality of LDPC codes is disclosed including an input interface and an output interface, and a first circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of a first multiplexer circuit, a second circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of the first multiplexer circuit, a third circuit for encoding quasi-cyclic LDPC code, connected at an input to the output of the first multiplexer circuit and at an output to the input of a second multiplexer circuit.

Abstract: A data processing method and apparatus. The data process method includes: determining, by a transmitting node, a code block length N0 for encoding an information bit sequence to be transmitted according to a data characteristic for representing the information bit sequence to be transmitted and a preset parameter corresponding to the data characteristic; performing, by the transmitting node, polar encoding on the information bit sequence to be transmitted according to the code block length N0; and transmitting, by the transmitting node, a code block obtained through the polar encoding to a receiving node.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. The computing device is operable to receive a memory access request for a data object stored within the DSN, determine a realm for the memory access request, determine an authorization service for the realm and generate an authorization request for the memory access request. The computing device is further operable to transmit the authorization request to an authorization service, receive an authorization request response from the authorization service, determine whether the memory access request is authorized and process the memory access request.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.

Abstract: There are provided a signal generation unit that generates a predetermined digital signal, a level conversion unit that converts a level of the digital signal generated by the signal generation unit, a DA converter that converts the digital signal of which the level is converted by the level conversion unit into an analog signal in a predetermined intermediate frequency bandwidth, and a control unit that creates correction data for correcting a linearity of a level of an output signal of the DA converter for all frequencies to be used, based on actual data which is data of a level of an actual output signal when a setting of the level of the output signal of the DA converter is changed at a predetermined level interval, at a predetermined frequency, and converts a level of an input signal of the DA converter with the correction data.

Abstract: A MAC operator includes a plurality of data type converters and a plurality of multipliers. Each of the plurality of data type converters may receive 16-bit input data of one of first to fourth data types of a floating-point format to convert into L-bit output data of the floating-point format. Each of the plurality of multipliers may perform a multiplication on the “L”-bit output data of the floating-point format outputted from two of the plurality of data type converters to output multiplication result data of the floating-point format.

Abstract: A deep neural network (“DNN”) module compresses and decompresses neuron-generated activation data to reduce the utilization of memory bus bandwidth. The compression unit receives an uncompressed chunk of data generated by a neuron in the DNN module. The compression unit generates a mask portion and a data portion of a compressed output chunk. The mask portion encodes the presence and location of the zero and non-zero bytes in the uncompressed chunk of data. The data portion stores truncated non-zero bytes from the uncompressed chunk of data. A decompression unit receives a compressed chunk of data from memory in the DNN processor or memory of an application host. The decompression unit decompresses the compressed chunk of data using the mask portion and the data portion.

Abstract: According to one embodiment, a compression circuit generates substrings from input data for (3+M) cycles, the input data being N bytes per cycle, a byte length of each substring being greater than or equal to (N×(1+M)+1); obtains a set of matches, each of the matches including at least one past input data which input past and corresponds to at least a part of each of the substrings; selects a subset of matches from the set of matches including the input data of one cycle; and outputs the subset of matches. M is zero or a natural number. N is a positive integer which is two or more.

Abstract: In certain embodiments, an apparatus includes a switch matrix and frequency band isolation circuitry. The switch matrix is configured to receive, at an input port, an electrical signal, which corresponds to a transmission signal received at antennas of an antenna array. The transmission signal corresponds to a transmission spatial sector of the array. The electrical signal includes first and second signal portions in first and second frequency bands, respectively, the electrical signal having been generated from an optical signal that corresponds to the transmission signal. The switch matrix is configured to direct, via an output port and in accordance with a control signal, the electrical signal to a first of multiple signal conversion paths.

Abstract: In an electronic device and a method of operating the electronic device according to various embodiments, a front end module of the electronic device comprises: a first terminal connected to a transmission port for a first communication; a second terminal connected to a reception port for the first communication; a first amplifier connected to the first terminal; an amplifier circuit including a second amplifier and a bypass line connected in parallel with the second amplifier; a first switch connecting the amplifier circuit to one from among the second terminal, a third terminal connected to one of a reception port for a second communication or a transmission port for the second communication, and a fourth terminal connected to one of the reception port for the second communication or the transmission port for the second communication; and a second switch connecting an antenna to one of the amplifier circuit and the first amplifier, wherein a transmission signal of the second communication may be configured

Abstract: A transmitter (1; 21) to transmit an amplitude modulated data signal (2) in an RF-Field (3) over the air to a receiver (4) of an RFID communication system (5; 22) which transmitter (1; 21) comprises: a wave generator (6) to generate a carrier signal (7) with a particular frequency and waveform; a modulation stage (15) to modulate the carrier signal (7) in relation to a data signal to be transmitted; an antenna (11) connected to the modulation stage (15) or wave generator (6) via an amplifier (9) and a matching circuit (10) to transmit the amplitude modulated data signal (2) in the RF-Field (3) over the air, characterized in that the transmitter (1; 21) furthermore comprises: a shape stage (16) connected to the wave generator (6) to select the waveform of the carrier signal (7) depending directly or indirectly on the data signal.

Abstract: A circuit device includes a directional coupler with a first port receiving a radiofrequency signal, a second port outputting a signal in response to signal received by the first port, and a third port outputting a signal in response to a reflection of the signal at the second port. An impedance matching network is connected between the second port and an antenna. The impedance matching network includes fixed inductive and capacitive components and a single variable inductive or capacitive component. A diode coupled to the third port of the coupler generates a voltage at a measurement terminal which is processed in order to select and set the inductance or capacitance value of the variable inductive or capacitive component.

Abstract: Aspects of this disclosure relate to a tunable filter with harmonic rejection. The tunable filter includes mutually coupled inductors and a tunable capacitance circuit electrically connected to at least one of the mutually coupled inductors. The tunable capacitance circuit includes N switches configured to adjust effective capacitance of the tunable capacitance circuit to tune harmonic rejection of the tunable filter for at least 2×2N harmonics. The tunable filter can filter a radio frequency signal. Related methods, radio frequency systems, radio frequency modules, and wireless communication devices are also disclosed.

Abstract: In some implementations, a radiofrequency down converter comprises an input port to receive a radiofrequency input signal, and the down converter includes a first bandpass filter configured to filter the input signal. The down converter includes a mixer stage coupled to the bandpass filter, the mixer stage being configured to generate a mixer output signal by processing the filtered input signal using a gain adjustment device, one or more amplifiers, and a mixer. The down converter includes a signal adjustment stage coupled to receive the mixer output signal, the signal adjustment stage comprising: a temperature compensation device configured to compensate for changes in signal gain due to changes in temperature; a second bandpass filter; a gain adjustment device; one or more amplifiers; and a low pass filter. The down converter comprises an output port coupled to output an adjusted mixer output signal from the signal adjustment stage.

Abstract: In one aspect, a method comprises: initializing a front end circuit of a wireless device into a first mode in which a radio frequency (RF) signal processing path comprises a low noise amplifier (LNA) having an output coupled to an RF filter; and in response to an RF signal received in the front end circuit having a level greater than a first threshold, reconfiguring the front end circuit into a second mode in which the RF filter is coupled to an input of the LNA.

Abstract: A capsule-type endoscope capable of two-way communication includes an RFID receiving antenna receiving an RFID signal, a first matching circuit for impedance matching with the RFID receiving antenna, a human body communication electrode comprised of a ground electrode and a signal electrode transmitting a signal for human body communication, and a second matching circuit for impedance matching with the human body communication electrode.

Abstract: One embodiment is directed to a universal digital card (UDC) for use in a node of a distributed antenna system (DAS). The UDC is configured to convert data between an external interface format used to communicate on an external communication link and a fronthaul interface format natively used in the DAS. The UDC is configured to be selectively used either as: a donor card to communicatively couple the node to one or more base station entities via the external digital interface or a distribution card to communicatively couple the node to one or more non-DAS nodes, hubs, switches, or remote radio heads or one or more other DAS nodes access points. Other embodiments are disclosed.

Abstract: A method of operating a movable support for orienting and positioning a portable computing device in a vehicle includes supporting the portable computing device with the movable support, and receiving status data based on a status of the vehicle with a controller. The method also includes determining a target orientation of the portable computing device based on the status data with the controller, the target orientation including one of a portrait screen orientation and a landscape screen orientation, and determining a target angular position of the portable computing device based on the status data, the target angular position including one of a driver-oriented position and a passenger-oriented position. The method further includes using the controller to move the movable support to position the portable computing device in the target orientation and the target angular position.

Abstract: In an example, a system includes a plurality of acoustically coupled nodes. Each of the nodes includes a transducer, a communication circuit and a controller. The transducer is adapted to be mechanically coupled to a medium. The communication circuit is coupled to the transducer to send and receive acoustic signals via the medium according to at least one communication parameter. The controller is to adaptively configure the at least one communication parameter of the communication circuit based on an acoustic signal received from at least one other of the nodes.

Abstract: Disclosed is an electronic device including: first communication circuitry including a first amplifier, second communication circuitry including a second amplifier, a transceiver, a processor, and a power supply. The processor may be configured to: provide, to the first communication circuitry, a first voltage for transmitting a first signal using the power supply in a first time interval, and provide, to the second communication circuitry, a second voltage for transmitting a second signal using the power supply in a second time interval that does not overlap the first time interval.

Abstract: In ultra-wideband or impulse radio terahertz wireless communication, the electromagnetic signal may experience group delay dispersion (GDD). Without correction, this can degrade the achievable data transmission rate. An apparatus comprising a stratified structure having a front portion and a back portion is disclosed. The structure comprises a plurality of adjacent layers of differing refractive indices, wherein each layer has a refractive index different from an immediately adjacent layer. The structure further includes a backing layer at the back portion. The structure defines a GDD, which can be adjusted, and the structure is configured to introduce the GDD to an incident electromagnetic signal and thereby produce a dispersion-compensated electromagnetic signal when the incident signal is reflected by the structure. The GDD of the structure is configured to substantially cancel out the dispersive effects experienced by the electromagnetic signal in the signal path.

Abstract: An optical device may include a dispersion element. The optical device may include a reflective optic to reflect an optical beam with a fixed offset perpendicular to a dispersion direction of the dispersion element and with a negative offset in the dispersion direction of the dispersion element. The reflective optic may be aligned to the dispersion element to offset an optical beam with respect to the dispersion element and to cause the optical beam to pass through the dispersion element on a plurality of passes, offsetting the optical beam on each of the plurality of passes.

Abstract: A transmitter may include a digital signal processor (DSP) to generate an electrical signal associated with a beacon and a data signal. The transmitter may include an electro-optical component to convert the electrical signal to an optical signal to be transmitted by the transmitter. The beacon and the data signal may be on a common wavelength in the optical signal. A power of the beacon within the optical signal may be based on a value of an amplitude modulation factor applied to the beacon by the DSP in association with generating the electrical signal.

Abstract: A free-space optical (FSO) terminal may include a controller and an alignment sensor. The alignment sensor includes a set of detectors. Each detector generates a signal responsive to receiving electromagnetic radiation at a detection surface. The set of detectors includes an inner set of detectors and an outer set of detectors. The detection surfaces of the inner detectors and the outer detectors may be aligned in a plane. The outer set of detectors surround the inner set of detectors (e.g., in the plane) and have larger detection surfaces than the inner set of detectors. During a tracking mode, the controller is configured to adjust an orientation of the FSO terminal based on signals from the inner set of detectors. During an acquisition mode, the controller is configured to adjust the orientation of the FSO terminal based on signals from the outer set of detectors.

Abstract: The invention provides a visible light communication system with adaptive dimming and a modulation and demodulation method. The system includes: a source; an adaptive M-PAM modulator, separately modulating a signal transmitted by the signal source into a first and a second electrical signal; and a dual-path pulse generator, alternately generating a first and a second pulse control signal, where the first and the second pulse control signal are both periodic signals, where when a remaining operating duration of a high level of the first pulse control signal equals to a time of a rising edge of the second pulse control signal, the second pulse control signal starts to be generated, and when a remaining operating duration of a high level of the second pulse control signal is equal to a time of a rising edge of the first pulse control signal, the first pulse control signal starts to be generated.

Abstract: This application provides an example base station for an example wireless communication network and an example method. One example base station includes a central unit and a remote radio unit (RRU). The RRU includes one or more antennas. The RRU is coupled to the central unit via one or more optical transmission fibers. Each optical transmission fiber defines a respective downlink transmission channel for transmitting a respective downlink transmission signal from the central unit to the respective antenna of the RRU. The RRU is configured to provide a respective uplink feedback signal based on the respective downlink transmission signal via an uplink feedback channel to the central unit.

Abstract: A technology is described for a Photonic Integrated Circuit (PIC) radio frequency (RF) in-phase quadrature phase (I/O) correlator. The PIC RF Correlator can comprise two optical waveguides to receive first and second optical signals that are modulated by first and second RF signals, respectively. Two 1 to M optical splitters can split the first and second RF modulated optical signals. Optical delay lines can delay the M split first RF modulated optical signals. M optical balanced couplers can receive and combine the M first delayed RF modulated optical signals with the M split second RF modulated optical signals. Balanced photodetectors can output a differential integration on the first and second combined RF modulated optical signals for in-phase and quadrature phase signals. A processor can add the outputs of the M optical balanced photodetectors to form a frequency domain correlated signal of the first and second RF signals with real and imaginary parts.

Abstract: An ROF communication remote machine and an ROF system are disclosed. The machine comprises a first packaging module and a second packaging module. The first packaging module comprises a first branch and a second branch. The first branch is used for converting a downlink optical signal, and sending the downlink electrical signal to the second packaging module. The second branch receives the downlink electrical signal, converts the downlink electrical signal into a downlink optical signal, sends the downlink optical signal to the local machine, receives an uplink electrical signal, and sends the uplink electrical signal to the local machine. The second packaging module is used for amplifying the power of the downlink electrical signal, filtering the downlink electrical signal, then feeding back the downlink electrical signal to another component, receiving the uplink electrical signal, and sending the uplink electrical signal to the second port.