Patents Issued in February 20, 2024
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Patent number: 11907021Abstract: A deployable protective case and a method of deploying said case is provided. The case includes a main body which is divided into an upper portion and lower portion that are separated by a living hinge. The case is configured with guide surfaces that allow for the case to engage with more than one electronic device, such as a tablet and a keyboard. The protective case is movable to a stowed configuration and a deployed configuration. In the stowed configuration, the devices are protected during storage and transportation. In the deployed configuration, the devices are made accessible for use, such as by positioning a tablet relative to a keyboard. While deployed, the case maintains engagement with at least a part of the electronic device.Type: GrantFiled: April 24, 2020Date of Patent: February 20, 2024Assignee: Urban Armor Gear, LLCInventors: Steven Armstrong, Jay Veltz, Bryan Soriano
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Patent number: 11907022Abstract: Apparatus, systems, articles of manufacture, and methods are disclosed for physical keyboards with multi-display computing devices. An example keyboard includes a plurality of keys and a translucent backplate having a first side and a second side. The example keyboard also includes a coating between the first side of the backplate and the plurality of keys, the coating to pass light to illuminate the plurality of keys, and the coating to obscure the plurality keys when viewed from the second side of the backplate.Type: GrantFiled: April 25, 2023Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Jeff Ku, Tim Liu, Yihua Lai, Lance Lin, Gavin Sung
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Information processing system, information processing apparatus, terminal device, and display method
Patent number: 11907023Abstract: An information processing system includes an information processing apparatus including a display and a terminal device to execute one or more applications. The information processing apparatus includes first circuitry to transmit a detection result indicating at least one of a posture, an inclination, and a bending angle of the display to the terminal device, receive layout information of the applications and content information of the applications from the terminal device, and display one or more windows of the applications on the display based on the layout information and the content information received from the terminal device. The terminal device includes second circuitry to determine, based on the detection result, a layout of the one or more windows of the applications corresponding to the detection result transmitted from the information processing apparatus to generate the layout information and transmit the layout information to the information processing apparatus.Type: GrantFiled: April 19, 2022Date of Patent: February 20, 2024Assignee: Ricoh Company, Ltd.Inventor: Masato Takahashi -
Patent number: 11907024Abstract: According to one aspect of the disclosure an electronic device comprises a foldable housing including: a hinge structure, a first housing structure connected to the hinge structure, and including a first face and a second face opposite the first face, and a second housing structure connected to the hinge structure and including a third face and a fourth face opposite the third face, the second housing structure being configured to be rotated about the hinge structure; a flexible display extending over the first face and over the third face; at least one sensor disposed within the foldable housing, and configured to sense an angle formed between the first face and the third face; a first haptic actuator disposed within the first housing structure; a second haptic actuator disposed within the second housing structure; at least one processor disposed within the first housing structure or the second housing structure, and operatively connected to the flexible display, the at least one sensor, the first haptic actType: GrantFiled: October 25, 2022Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Minsoo Kim, Bongsub Kim, Taewon Kim, Sangmin Lee, Jongheon Lee, Jiwoo Lee
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Patent number: 11907025Abstract: A latch mechanism includes a latch and a rotation shaft supporting part. The latch is rotatable around a rotation shaft between a housing position and a lock position, and fixes a first unit and a second unit in a closed state at the lock position. The rotation shaft supporting part rotatably supports the rotation shaft. The latch has a first ring-shaped part disposed coaxially with the rotation shaft. The rotation shaft supporting part has a second ring-shaped part disposed coaxially with the rotation shaft. Heights of the first ring-shaped part and the second ring-shaped part are set such that an area of abutment between the first ring-shaped part and the second ring-shaped part increases as the latch rotates from the lock position to the housing position.Type: GrantFiled: August 11, 2022Date of Patent: February 20, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kenichi Shindo, Futoshi Kuriyama, Tatsuo Kuromoto
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Patent number: 11907026Abstract: A rotatable connector assembly includes a base and two connector members respectively connected to two sides of the base, where each of the connector members includes a first hinge and a second hinge, and both sides of the base are provided with a first sliding slot; one end of the first hinge is slidably connected to the first sliding slot and rotates with respect to the base, and the other end of the first hinge is hinged to one end of the second hinge; the rotatable connector assembly has an unfolded state and a folded state.Type: GrantFiled: July 29, 2021Date of Patent: February 20, 2024Assignee: VIVO MOBILE COMMUNICATION CO., LTD.Inventor: Yongjin Deng
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Patent number: 11907027Abstract: A portable information handling system supports a flexible OLED display film over housing portions rotationally coupled by a hinge by folding the OLED display film over the hinge. Hinge brackets that couple to the housing portions each have a gear member with a semicircular shape gear inner circumference that engages a gear subassembly of the hinge main body. Hinge bracket rotation translates through the gear subassembly for synchronized housing rotation. The hinge main body has first and second semicircular portions with a smooth surface defined to accept the outer circumference smooth surface of the gear member semicircular shape at first and second rotation axes about which the hinge brackets pivot so that the display film has space to fold in the closed position.Type: GrantFiled: October 19, 2021Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Christopher A. Torres, Kevin M. Turchin, Enoch Chen, Anthony J. Sanchez, Kai-Cheng Chao, Chia-Hao Hsu, Chia-Huang Chan
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Patent number: 11907028Abstract: A portable electronic device, including a first body and a second body, is provided. The second body includes a support structure and a display panel. The support structure is pivotally connected to the first body and is connected to the display panel. The support structure has a first bendable portion. An included angle between the first bendable portion and an edge of the support structure is 45 degrees. The support structure is adapted to be bent along the first bendable portion, so that the second body switches between a first mode and a second mode relative to the first body.Type: GrantFiled: June 16, 2022Date of Patent: February 20, 2024Assignee: COMPAL ELECTRONICS, INC.Inventors: Yu-Wen Cheng, Wei-Ning Chai, Ting-Wei Liu, Tzu-Yung Huang, Wang-Hung Yeh
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Patent number: 11907029Abstract: A portable blockchain mining system is disclosed comprising: a portable building; a plurality of blockchain mining processors mounted within, or a plurality of blockchain mining processor mounts located within, an interior of the portable building; an air inlet defined in the portable building; an air outlet defined in the portable building above the air inlet and oriented to direct exhaust air out of the portable building; and a cooling fan connected to convey air through the air inlet, across the plurality of blockchain mining processors and out the air outlet.Type: GrantFiled: March 31, 2020Date of Patent: February 20, 2024Assignee: Upstream Data Inc.Inventor: Stephen Barbour
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Patent number: 11907030Abstract: Disclosed herein are systems and methods that may be implemented in real time to determine the total volumetric rate of airflow through a chassis enclosure of an information handling system platform directly from real time measured cooling fan power consumption in combination with standalone or system-level cooling fan power characteristics (e.g., expressed as cooling fan power curves) that relate cooling fan volumetric airflow rate to cooling fan power consumption at the current fan rotation speed. This determined value of total real time volumetric airflow rate may then be used, for example, by individual system level thermal control algorithms and/or data center level thermal control algorithms.Type: GrantFiled: January 11, 2021Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Richard Eiland, Hasnain Shabbir
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Patent number: 11907031Abstract: A display device includes a display module including a first non-folding region, a folding region, and a second non-folding region arranged in a first direction, a first support plate disposed on the display module, a second support plate disposed on the first support plate, a heat dissipation layer disposed between the first and second support plates, and including a bending portion overlapping the folding region, a first adhesive layer disposed between the first support plate and the heat dissipation layer, and a second adhesive layer disposed between the second support plate and the heat dissipation layer. An opening defined in each of the first and second adhesive layers has a width greater than a width of the bending portion of the heat dissipation layer in a portion overlapping the folding region.Type: GrantFiled: February 11, 2022Date of Patent: February 20, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hun-Tae Kim, Jinhyoung Kim, Dongho Yoon, Gyumdong Bae
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Patent number: 11907032Abstract: A computing device is provided, including one or more processing devices, one or more temperature sensors, a fan, and a fan tachometer. The one or more processing devices may be configured to execute an application program. While executing the application program, the one or more processing devices may be further configured to collect performance data including temperature data received from the one or more temperature sensors and fan speed data received from the fan tachometer. The one or more processing devices may be further configured to generate a fan control signal at least in part by applying a machine learning model to the performance data. The one or more processing devices may be further configured to control the fan according to the fan control signal.Type: GrantFiled: June 21, 2021Date of Patent: February 20, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Nikita Ramesh Wanjale, David Michael Sutherland, Jonathan Robert Pease
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Patent number: 11907033Abstract: Systems and methods for providing adaptive power on reset (POR) signals for use with programmable logic devices (PLDs) and/or other semiconductor devices are disclosed. An example adaptive POR signal generator includes a logic device configured to detect a first supply voltage ramp traversal across a first threshold ramp voltage, detect a second supply voltage ramp traversal across a second threshold ramp voltage, and generate a POR signal based, at least in part, on a nominal operating voltage associated with the power supply and/or the supply voltage and/or on a ramp time associated with the first and second supply voltage ramp traversals. The second threshold ramp voltage is higher than the first threshold ramp voltage and the first and second threshold ramp voltages are lower than the nominal operating voltage.Type: GrantFiled: June 3, 2022Date of Patent: February 20, 2024Assignee: Lattice Semiconductor CorporationInventors: Chwei-Po Chew, Bradley A. Sharpe-Geisler
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Patent number: 11907034Abstract: A method of power management for a hub having a plurality of Universal Serial Bus (USB)-C ports includes: allocating a guaranteed power budget to each USB-C port of the hub, wherein one of the USB-C ports has a higher power priority and the other USB-C ports have a lower power priority; reducing the guaranteed power budget allocated to a USB-C port with the lower power priority if measured power for that USB-C port is below its currently guaranteed power budget by a predetermined amount; and offering additional power budget to the USB-C port with the higher power priority if the guaranteed power budget allocated to a USB-C port with the lower power priority was previously reduced. Corresponding USB-Power Delivery (PD) integrated circuit (IC) controllers and hubs are also described.Type: GrantFiled: June 15, 2022Date of Patent: February 20, 2024Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Karthik Sivaramakrishnan, Simon Abraham, Manaskant Dipakkumar Desai
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Patent number: 11907035Abstract: An interface of a device is used to couple to another device and includes a set of data pins to support high speed data communication on an interconnect link between the devices based on an interconnect protocol. The interface further includes at least one auxiliary pin to support a particular signal defined by the interconnect protocol. The device is further configurated to generate hint data for use by the other device and send the hint data as a sideband signal to the other device over the auxiliary pin, where the sideband signal is distinct from signals defined for the auxiliary pin by the interconnect protocol.Type: GrantFiled: May 15, 2020Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Ang Li, David J. Harriman, Kuan Hua Tan
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Patent number: 11907036Abstract: An integrated circuit includes a plurality of sub blocks configured to process an instruction according to an operating condition, a plurality of active counters configured to count an active time, which is a time for each of the plurality of sub blocks to process an instruction, and a Dynamic Voltage and Frequency Scaling (DVFS) controller configured to calculate power consumption of the plurality of sub blocks during a sample period based on the active time and adjust an operating condition of the plurality of sub blocks based on the power consumption.Type: GrantFiled: September 29, 2021Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Yousub Jung, Seokju Yoon, Jihan Cha
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Patent number: 11907037Abstract: Systems and methods for providing audio-file loop-playback functionality are provided. The system includes a processor that performs a method including setting a playback loop start-point based on a first selection of a button; setting a loop end-point, associating a loop with an audio file, and entering into the loop based on a second selection of the button; and exiting the loop based on a third selection of the button. Associating the loop with the audio file includes adding metadata to the audio file. The metadata associates the loop with a button. The method includes reentering the loop based on a fourth selection of the button and exiting the loop based on a fifth selection of the button.Type: GrantFiled: December 30, 2022Date of Patent: February 20, 2024Assignee: InMusic Brands, Inc.Inventors: John O'Donnell, Christopher Blane Roman, Vincent Ming Chen, Marcus Tillmans
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Patent number: 11907038Abstract: A temperature control device (e.g., a thermostat) may be configured to control an internal heat-generating electrical load so as to accurately measure a present temperature in a space around the temperature control device. The temperature control device may comprise a temperature sensing circuit configured to generate a temperature control signal indicating the present temperature in the space, and a control circuit configured to receive the temperature control signal and to control the internal electrical load. The control circuit may be configured to energize the internal electrical load in an awake state and to cause the internal electrical load to consume less power in an idle state. The control circuit may be configured to control the internal electrical load to a first energy level (e.g., a first intensity) during the awake state and to a second energy level (e.g., second intensity) that is less than the first during the idle state.Type: GrantFiled: August 19, 2022Date of Patent: February 20, 2024Assignee: Lutron Technology Company LLCInventors: Jason C. Killo, Donald R. Mosebrook, James P. Steiner
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Patent number: 11907039Abstract: An information handling system wirelessly interfaces with a location peripheral aid through primary radios that have a communication protocol, such as Bluetooth Low Energy or a wireless local area network, and through secondary radios having a low power wake and sleep using wake and sleep signals sent between the secondary radios. The location peripheral aid establishes communication with the information handling system, which reports its position to a network location to allow tracking location of the peripheral aid. The peripheral primary and secondary radio transmit and receive states operate with different profiles to manage power based upon bi-directional communications tracked over time.Type: GrantFiled: March 25, 2021Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Karthikeyan Krishnakumar, Minho Cheong
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Patent number: 11907040Abstract: The processor system includes a processor coupled to a memory having a plurality of memory banks and a region configurable as a heap region. At least one memory bank is allocated to the heap region dependent on a predetermined memory size required for execution of at least one cryptographic operation. At least one further memory bank is allocated to the heap region. The processor system may switch between first and second operating states. The first operating state has a lower power consumption than the second operating state. The processor system switches between a first and second operating mode by setting at least one memory bank and at least one further memory bank to an active state. The processor system switches between the second and first operating mode by setting at least one memory bank to a retention state and the at least one further memory bank to a power-down state.Type: GrantFiled: June 10, 2021Date of Patent: February 20, 2024Assignee: NXP USA, Inc.Inventors: Doru Cristian Gucea, Teodor Cosmin Grumei, Andrei Istodorescu
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Patent number: 11907041Abstract: Embodiments of this application disclose an application processor wakeup method and apparatus applied to a mobile terminal. In the method, whether the mobile terminal is in a preset first state is first detected. After it is determined that the mobile terminal is in the preset first state, a to-be-reported instruction that needs to be reported to an application processor and the priority of the to-be-reported instruction are obtained. When the priority of the to-be-reported instruction is higher than a preset priority, the to-be-reported instruction is reported to the application processor, to wake up the application processor, so that the application processor performs a corresponding operation.Type: GrantFiled: April 27, 2021Date of Patent: February 20, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventor: Dawei Lin
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Patent number: 11907042Abstract: A portable information handling system modular hybrid architecture separates components between rotationally coupled housing portions to minimize cabling, connectors and materials, and to provide improved durability that supports recycling and reuse of the components. A single cable between the housing portions provides power and data communications for the components. A battery in a first housing portion interfaces with a secondary board having a charger and embedded controller that cooperate to provide power at a native battery voltage to a main board of a second housing portion through the cable. A switched-capacitor voltage regulator coupled to the main board reduces the power to a system voltage with a selectable divider ratio that is set based upon the measured battery voltage applied at the main board.Type: GrantFiled: December 13, 2021Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Jace W. Files, John Trevor Morrison, Andrew P. Tosh
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Patent number: 11907043Abstract: A processor can include various processing pipelines that perform different data processing operations, with different pipelines having dedicated logic and memory circuits. A power management circuit can determine when to supply power to various pipelines, including the logic and memory circuits of the various pipelines, depending on a current operating mode of the processor. When a memory circuit transitions to a lower power state such as a sleep state, data can be saved to a different memory circuit that is not transitioning to a lower power state, and when the memory circuit is powered up again, the data can be restored from the different memory circuit.Type: GrantFiled: May 25, 2022Date of Patent: February 20, 2024Assignee: Apple Inc.Inventors: Ping Zhou, Nikolai Schlegel, Navid Ehsan, Zhimin Chen, Gerard D. Jennings
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Patent number: 11907044Abstract: A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state. The evaluation unit is configured for evaluating the plurality of memory cells in the first state to obtain a first evaluation result, and for evaluating the plurality of memory cells in the second state to obtain a second evaluation result.Type: GrantFiled: September 13, 2021Date of Patent: February 20, 2024Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers
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Patent number: 11907045Abstract: One embodiment provides a system for processing natural-language entries. The system obtains a plurality of historical natural-language entries associated with a first domain and pre-processes the historical natural-language entries to obtain a set of generic terms and a set of domain-specific terms. The system trains a machine learning model in the first domain using the plurality of historical natural-language entries associated with the first domain. The training comprises learning weight values of one or more generic terms, a weight value of a respective generic term indicating likelihood that the generic term is related to a trigger event. The system generalizes the machine learning model trained in the first domain, thereby allowing the model to be applied to a second domain.Type: GrantFiled: April 26, 2022Date of Patent: February 20, 2024Assignee: Novity, Inc.Inventors: Evgeniy Bart, Kai Frank Goebel
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Patent number: 11907046Abstract: An edge computing device is provided including at least one memory configured to store computer program code and at least one processor configured to access said computer program code and operate as instructed by said computer program code. The edge computing device is included in a distributed object identification system, which includes a plurality of edge computing devices, and the edge computing device is determined as a central control device based on election from the plurality of edge computing devices. The computer program code includes first capturing code configured to cause the at least one processor to capture a video stream of an environment and first obtaining code configured to cause the at least one processor to obtain identity information of an object in the video stream by performing object identification on the video stream.Type: GrantFiled: March 31, 2022Date of Patent: February 20, 2024Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventor: Wenxing Lai
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Patent number: 11907047Abstract: A data storage device, and an error tolerance selecting method thereof which includes: writing data to data blocks of the data storage device; reading written data of the data blocks as read data; comparing the read data and the written data of each data column in the data blocks, and calculating a number of error bits in each chunk including a plurality of data columns accordingly; calculating a difference value between the number of error bits in the chunk and a first threshold value to store the difference value in an error tolerance list; and selecting a largest difference value in the error tolerance list as an error tolerance.Type: GrantFiled: April 8, 2022Date of Patent: February 20, 2024Assignee: Silicon Motion, Inc.Inventor: Sheng-Yuan Huang
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Patent number: 11907048Abstract: A tool for scaling media utilizing healthy regions of a data storage cartridge. The tool determines a health status index for one or more regions of a data storage cartridge. The tool records the health status index to a cartridge memory and housekeeping dataset of the data storage cartridge. The tool determines one or more available regions of the data storage cartridge, based, at least in part, on a capacity designation and the health status index for the one or more regions. The tool returns the one or more available regions and a reduced capacity for the data storage cartridge to a user.Type: GrantFiled: December 2, 2021Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Setsuko Masuda, Tsuyoshi Miyamura, Mitsuhiro Nishida, Tatsuki Sawada
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Patent number: 11907049Abstract: The present information processing apparatus comprises a non-volatile memory that has a first portion including a code area configured to hold a program and a data area configured to hold data. In addition, the information processing apparatus acquires update data of a first portion, and updates the first portion with the acquired update data. In the updating process, at least a portion of the program held in the code area is deleted before updating the contents of the data area, and after updating the contents of the data area, updating to the code area is completed.Type: GrantFiled: January 12, 2022Date of Patent: February 20, 2024Assignee: Canon Kabushiki KaishaInventor: Hidemi Sasaki
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Patent number: 11907050Abstract: Aspects of the subject technology relate to systems, methods, and computer-readable media for diagnosing faults in a software stack by running a subset of processes of the software stack. An existence of a fault associated with running a software stack is determined. The software stack includes a plurality of dependent processes. An incrementing larger subset of the software stack is run according to one or more error thresholds associated with executing corresponding dependent processes in the incrementing larger subset. The incrementing larger subset includes an increasing number of processes of the plurality of dependent processes. One or more sources of the fault are diagnosed based on the running of the incrementing larger subset of the software stack.Type: GrantFiled: September 15, 2022Date of Patent: February 20, 2024Assignee: GM Cruise Holdings LLCInventor: Ishan Singh
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Patent number: 11907051Abstract: A method, computer system, and computer program product for data monitoring management are provided. A first invalid zero value candidate from a data stream is received. A memory location for the first invalid zero value candidate is received. At a first time an access connection to the memory location is established. At a second time subsequent to the first time the access connection to the memory location is checked. Based on the checking, a determination is made whether the first invalid zero value candidate contains an invalid zero value.Type: GrantFiled: September 7, 2022Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Bo Chen Zhu, Cheng Fang Wang, Ai Ping Feng, Xinzhe Wang, Yan Ting Li, Hong Yan Gu
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Patent number: 11907052Abstract: An information handling system may include a processor, a display device communicatively coupled to the processor, and a management controller communicatively coupled to the processor and the display device and configured to, in response to a failure of the information handling system, determine a component of the information handling system as a source of failure, generate a unique failure code associated with the failure, encrypt the unique failure code to generate an encrypted unique failure code, and display the encrypted unique failure code to the display device.Type: GrantFiled: April 20, 2020Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Craig L. Chaiken, Adolfo S. Montero, Geroncio O. Tan, Hong-Ji Huang, Yi-Fan Wang
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Patent number: 11907053Abstract: A failure handling apparatus (100) is provided with: an acceptance unit (15) that accepts specification of condition information in an execution condition; a code generation unit (16) that generates a program code of a conditional expression based on the specified condition information; a template generation unit (17) that generates an input template of a plurality of failure handling rules, including an input field of a determination criterion value for determining extracted information, based on the program code and an input field of a handling content; and a list generation unit (18) that sets input values, for the input template, in the input fields and stores the input values in a storage unit as a list.Type: GrantFiled: February 25, 2021Date of Patent: February 20, 2024Assignee: NEC CORPORATIONInventors: Nagi Moriyama, Yuko Takemura
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Patent number: 11907054Abstract: The system comprises a plurality of driver modules coupled by a fault condition bus, e.g. single-wire bus. Each driver module includes an Error Flag Interface block coupled between a single terminal error flag input/output (EF I/O) and a Control block. Each driver module may be coupled- to a motor. When a driver module detects a local fault condition, its Error Flag Interface block is configured to lower the voltage at the single terminal EF I/O to communicate the change to the other driver modules. The Error Flag Interface block is further configured to monitor voltage changes at its single terminal EF I/O. An external fault condition is detected when the single terminal EF I/O is at a low voltage. The Error Flag Interface block is further configured to send a signal disabling the output of the driver module.Type: GrantFiled: June 21, 2022Date of Patent: February 20, 2024Assignee: POWER INTEGRATIONS, INC.Inventors: Stefan Baeurle, Michael Yue Zhang
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Patent number: 11907055Abstract: It is desired to be able to easily identify a cause of a communication abnormality in an industrial machine. A controller of an industrial machine which communicates with an external device through a network includes: a plurality of communication units which respectively correspond to a plurality of communication protocols; and a diagnosis unit which starts up the communication units in a predetermined order and attempts communication using the communication protocols corresponding to each communication unit that is started up so as to diagnose the conditions of communication step by step.Type: GrantFiled: June 24, 2020Date of Patent: February 20, 2024Assignee: FANUC CORPORATIONInventor: Eiji Baba
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Patent number: 11907056Abstract: Disclosed herein is a data processing system comprising a processing unit operable to process data to generate a sequence of outputs, wherein the processing unit is configurable, when generating a sequence of outputs, such that the data processing for generating an output in the sequence of outputs will be performed within a respective processing period for the output. A controller for the processing unit is configured to cause the processing unit, when generating a sequence of outputs, during a respective processing period for at least one output in the sequence of outputs, to also undergo one or more fault detection test(s) such that both processing of data for the output and fault detection testing is performed during the respective processing period for the output.Type: GrantFiled: November 18, 2021Date of Patent: February 20, 2024Assignee: Arm LimitedInventors: Eamonn Quigley, Nicholas John Nelson Murphy, Jussi Tuomas Pennala, Henrik Nils-Sture Olsson
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Patent number: 11907057Abstract: Various embodiments of the teachings herein include a fault processing method comprising: receiving two historical faults similar to a target fault; searching keywords in a description of the target fault and each historical fault, wherein the keywords are classified into N grades, and for each system component in a grade, the grade comprises at least one keyword for describing the component, wherein N is an integer no less than 2; for each of the N grades, counting a quantity of identical system components represented by the keywords in the text description of each historical fault and the target fault; and comparing a degree of similarity of each historical fault to the target fault according to the quantity of identical system components counted in each grade of the N different grades, wherein a historical fault relating to a larger number of high-grade identical system components has a higher degree of similarity to the target fault.Type: GrantFiled: October 16, 2019Date of Patent: February 20, 2024Assignee: SIEMENS AKTIENGESELLSCHAFTInventors: Xiao Yin Che, Hao Tian Hui, Jiao Jian Wang, Ruo Gu Sheng, Daniel Schneegaß
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Patent number: 11907058Abstract: Disclosed are a method and device for positioning a faulty disk. The method comprises: in response to detecting that a first disk is faulted, determining positioning information of the first disk, the positioning information comprising a logic Enclosure Identity (EID) and a logic Slot Identity (SID); and positioning the first disk according to the EID and SID of the first disk.Type: GrantFiled: August 27, 2020Date of Patent: February 20, 2024Assignee: ZTE CORPORATIONInventor: Yuxue Liu
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Patent number: 11907059Abstract: An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.Type: GrantFiled: April 7, 2022Date of Patent: February 20, 2024Assignee: PHISON ELECTRONICS CORP.Inventor: Kok-Yong Tan
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Patent number: 11907060Abstract: A method begins by a processing module concurrently receiving a first data stream and a second data stream for transmission to a receiving entity. The method continues with the processing module dividing each of the first and second data streams to produce a first plurality of data blocks corresponding to the first data stream and a second plurality of data blocks corresponding to the second data stream, where data blocks of the first plurality of data blocks are time aligned with data blocks of the second plurality of data blocks. The method continues with the processing module creating a data matrix from the first and second plurality of data blocks and generating a coded matrix from the data matrix and an encoding matrix. The method continues with the processing module outputting a plurality of pairs of coded values of the coded matrix to the receiving entity.Type: GrantFiled: May 13, 2022Date of Patent: February 20, 2024Assignee: Pure Storage, Inc.Inventors: Gary W. Grube, Timothy W. Markison
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Patent number: 11907061Abstract: Methods, systems, and devices are described herein for using codewords to detect or correct errors in data (e.g., data stored in a memory device). A host device may generate one or more codewords associated with data to be stored in the memory device. In some cases, the host device may generate one or more codewords for error detection and correction (e.g., corresponding to data transmitted by the host device to the memory device). In some cases, the host device may transmit the codewords and the associated data using an extended (e.g., adjustable) burst length such that the one or more codewords may be included in the burst along with the data. Additionally or alternatively, the host device may transmit one or more of the codewords over one or more channels different than the one or more channels used to transmit the data.Type: GrantFiled: December 22, 2021Date of Patent: February 20, 2024Inventors: Scott E. Schaefer, Aaron P. Boehm
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Patent number: 11907062Abstract: A semiconductor system includes a controller configured to count the number of error check scrub (ECS) operations and configured to generate ECS information that includes information with regard to an address at which the ECS operation is to be performed based on the number of ECS operations. The semiconductor system further includes a memory apparatus configured to perform the ECS operation on a region that is selected by the ECS information.Type: GrantFiled: March 29, 2022Date of Patent: February 20, 2024Assignee: SK hynix Inc.Inventors: Hee Eun Choi, Kwang Soon Kim, Ji Eun Kim
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Patent number: 11907063Abstract: A read-disturb-based physical storage read temperature information identification system includes a global read temperature identification subsystem coupled to at least one storage device. Each at least one storage device reads valid data and obsolete data from at least one physical block in that storage device and, based on the reading of the valid data and the obsolete data, generates read disturb information associated with each row provided by the at least one physical block in that storage device. Each at least one storage devices then uses the read disturb information associated with each row provided by the at least one physical block in that storage device to generate a local logical storage element read temperature map for that storage device that it provides to the global read temperature identification subsystem.Type: GrantFiled: January 22, 2022Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Ali Aiouaz, Walter A. O'Brien, III, Leland W. Thompson
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Patent number: 11907064Abstract: A memory controller includes a fault predictor which predicts a fault which causes an error occurring in a memory device, an error correction code (ECC) manager which classifies a type of the fault based on the predicted fault, and a plurality of ECC engines which perform ECC in parallel depending on the classified type of the faults. The fault predictor includes a memory error profiler which receives raw data related to the error and processes the raw data into an error profile that is data available for machine learning, and a memory fault prediction network which receives the error profile as an input, performs the machine learning using the error profile, and predicts the fault which causes the error.Type: GrantFiled: March 17, 2022Date of Patent: February 20, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Youn Kim, Su Hun Lim
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Patent number: 11907065Abstract: Disclosed are various embodiments for improving the resiliency and performance of clustered memory. A computing device can generate at least one parity page from at least a first local page and a second local page. The computing device can then submit a first write request for the first local page to a first one of a plurality of memory hosts. The computing device can also submit a second write request for the second local page to a second one of the plurality of memory hosts. Additionally, the computing device can submit a third write request for the parity page to a third one of the plurality of memory hosts.Type: GrantFiled: January 25, 2023Date of Patent: February 20, 2024Assignee: VMware, Inc.Inventors: Marcos K. Aguilera, Keerthi Kumar, Pramod Kumar, Pratap Subrahmanyam, Sairam Veeraswamy, Rajesh Venkatasubramanian
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Patent number: 11907066Abstract: A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.Type: GrantFiled: May 2, 2022Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Xiangang Luo, Jianmin Huang, Lakshmi Kalpana Vakati, Harish R. Singidi
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Patent number: 11907068Abstract: A method comprising: receiving a request to read data stored in an array of drives; determining that the data is stored on one or more degraded drives in the array; reconstructing the data from one or more drives in the array other than the degraded drives; providing the reconstructed data in response to the request; and after providing the reconstructed data, writing the reconstructed data to one or more drives in the array other than the degraded drives.Type: GrantFiled: February 10, 2022Date of Patent: February 20, 2024Assignee: Nyriad, Inc.Inventors: Stuart John Inglis, Sheridan John Lambert, Adam Gworn Kit Fleming, Daniel James Nicholas Stokes
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Patent number: 11907069Abstract: In network devices, during manufacturing, input for designation of a region code to be a non-specific region code is stored in a BIOS memory of the network device, and a specific region code is stored off the BIOS. During boot up, the BIOS is checked for a specific region code to regulate wireless transmissions at a physical location of operation. Responsive to receiving the non-specific region code from BIOS, the specific region code is requested from a region code server based on a network device identifier. Once received, the region code is stored in flash memory, until rebooted or otherwise reset, rather than BIOS.Type: GrantFiled: December 9, 2020Date of Patent: February 20, 2024Assignee: Fortinet, Inc.Inventors: Yong Zhang, Peter Yongchun Liu, Koroush Akhavan-Saraf, Xin Wang, Andrew Q Ji, Ben Wilson
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Patent number: 11907070Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.Type: GrantFiled: July 30, 2021Date of Patent: February 20, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Eric Busta, Michael L. Golden, Sean M. O′Mullan, James Wingfield, Keith A. Kasprak, Russell Schreiber, Michael Estlick
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Patent number: 11907071Abstract: An information handling system may include a processor and first non-transitory computer-readable media communicatively coupled to the processor and having stored thereon a basic input/output system (BIOS) core comprising BIOS core firmware sufficient to execute features of a BIOS of the information handling system to a particular portion of BIOS execution and an extension agent. The extension agent may be configured to identify and enumerate a firmware volume of a second non-transitory computer-readable media communicatively coupled to the processor and having stored thereon a BIOS extension comprising BIOS extension firmware for executing completion of BIOS execution from the particular portion of BIOS execution and in response to unavailability of the firmware volume of the second non-transitory computer-readable media, failover to and recover the BIOS extension from extended firmware information stored on a networked storage resource communicatively coupled to the information handling system.Type: GrantFiled: May 9, 2022Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Shekar Babu Suryanarayana, Karunakar Poosapalli