Patents Issued in March 7, 2024
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Publication number: 20240078189Abstract: The present disclosure provides systems, methods, devices, and computer program products for cache eviction enforcement and multi-tenant distributed cache architectures and operations. Systems, methods, devices, and computer program products may access a slab of a multi-tenant caching system, perform an eviction review by sequentially reaping through the slab, based on the class size, flag a first cache item by the eviction review based on a header of the first cache item, wherein the header comprises a prefix indicative of an expiry time, confirm expiration of the first cache item via a lock and lookup operation, and evict the first cache item from the slab. Significant optimization and efficiency benefits may be realized through the slab organization, cache architectures, and operations discussed herein.Type: ApplicationFiled: September 5, 2023Publication date: March 7, 2024Inventors: Stuart Clark, Hong Lu, Eden Zik
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Publication number: 20240078190Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.Type: ApplicationFiled: October 30, 2023Publication date: March 7, 2024Inventors: Naveen BHORIA, Timothy David ANDERSON, Pete HIPPLEHEUSER
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Publication number: 20240078191Abstract: An integrated circuit (IC), including a functional circuit and a security system, is disclosed. The functional circuit generates a request packet for an indirect memory access of a memory. The security system validates the functional circuit based on a security attribute and a functional identifier of the functional circuit. Based on the request packet and the validation of the functional circuit, the security system identifies an instruction sequence associated with the indirect memory access. Further, the security system determines a type of the indirect memory access based on the instruction sequence, and validates the type of the indirect memory access based on the security attribute and the request packet. Based on the validation of the type of the indirect memory access, the instruction sequence is executed, thereby facilitating the indirect memory access for the functional circuit.Type: ApplicationFiled: October 26, 2022Publication date: March 7, 2024Inventors: Vivek Singh, Nikhil Tiwari, Vishal Gulati
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Publication number: 20240078192Abstract: Systems, apparatuses, and methods related to isolating virtual machines in a memory device are described. A memory apparatus includes a memory device and a controller coupled to the memory device, wherein the controller is configured to provide a plurality of Peripheral Component Interconnect express (PCIe) functions of the memory device and isolate access to each of the plurality of PCIe functions via respective passwords and digital signatures created from host keys.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Inventors: Michael Burk, Lance Dover
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Publication number: 20240078193Abstract: An output device includes an interaction interface configured to be connected to an interaction device, a first interface group configured to be connected to a first processing device, a second interface group configured to be connected to a second processing device, an output apparatus, and a processing apparatus configured to switch the output device between a first mode and a second mode. In the first mode, the output apparatus outputs media data from the first processing device, and interaction data is transmitted between the first processing device and the interaction device. In the second mode, the output apparatus outputs media data from the second processing device, and the interaction data is transmitted between the second processing device and the interaction device.Type: ApplicationFiled: August 29, 2023Publication date: March 7, 2024Inventors: Shuang HAN, Hsiang-I CHEN
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Publication number: 20240078194Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Inventors: Luca Iuliano, Simon Nield, Thomas Rose
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Publication number: 20240078195Abstract: An electronic device includes a processor having processor circuitry and a leader memory controller, a controller coupled to the processor and having a follower memory controller, and a memory. The processor circuitry is operable to access the memory by issuing memory access requests to the leader memory controller. The leader memory controller is operable to complete the memory access requests using the follower memory controller to issue memory commands to the at least one memory die.Type: ApplicationFiled: August 29, 2023Publication date: March 7, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Niti Madan, Gabriel H. Loh, James R. Magro
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Publication number: 20240078196Abstract: An information handling system includes a motherboard installed within a chassis, a first backplane coupled to the motherboard, a second backplane coupled to the motherboard. The first backplane is located in a front side of the chassis, and is configured to receive first add-in modules from the front of the chassis. The second backplane is located in a middle portion of the chassis, and is configured to receive second add-in modules. The second add-in modules are positioned above DIMMs installed in the motherboard.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Inventors: Misa Wang, Quy Ngoc Hoang, Krishna Kakarla
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Publication number: 20240078197Abstract: A data processing node includes a processor element and a data fabric circuit. The data fabric circuit is coupled to the processor element and to a local memory element and includes a crossbar switch. The data fabric circuit is operable to bypass the crossbar switch for memory access requests between the processor element and the local memory element.Type: ApplicationFiled: June 29, 2023Publication date: March 7, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Gabriel H. Loh
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Publication number: 20240078198Abstract: In accordance with some aspects of the present disclosure, a non-transitory computer readable medium is disclosed. In some embodiments, the non-transitory computer readable medium includes instructions that, when executed by a processor, cause the processor to receive, from a workload hosted on a host of a cluster, first I/O traffic programmed according to a first I/O traffic protocol supported by a cluster-wide storage fabric exposed to the workload as being hosted on the same host. In some embodiments, the workload is recovered by a hypervisor hosted on the same host. In some embodiments, the non-transitory computer readable medium includes the instructions that, when executed by the processor, cause the processor to adapt the first I/O traffic to generate second I/O traffic programmed according to a second I/O traffic protocol supported by a repository external to the storage fabric and forward the second I/O traffic to the repository.Type: ApplicationFiled: September 15, 2023Publication date: March 7, 2024Applicant: Nutanix, Inc.Inventors: Dezhou Jiang, Kiran Tatiparthi, Monil Devang Shah, Mukul Sharma, Prakash Narayanasamy, Praveen Kumar Padia, Sagi Sai Sruthi, Deepak Narayan
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Publication number: 20240078199Abstract: A just-in-time (JIT) scheduling method includes the operations of: receiving a request to perform a memory operation using a hardware resource associated with a memory device; determining a type of the memory operation; identifying a traffic class corresponding to the memory operation; determining, based on the traffic class and the type of the memory operation, whether the memory operation is to be processed during a current scheduling time frame; and responsive to determining the memory operation is to be processed during the current scheduling time frame, submitting the memory operation to the memory device.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Inventors: Johnny A. Lam, Alex J. Wesenberg, Guanying Wu, Sanjay Subbarao, Chandra Guda
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Publication number: 20240078200Abstract: Disclosed are a memory operating method, memory and electronic device. The memory complies with a read-write parallel protocol and includes a plurality of memory banks, and the method includes: sequentially mapping read and write transactions for consecutive logical addresses to different banks according to a predetermined transmission bit width by an address decoder, and arbitrating the read transaction and write transaction mapped to the same bank in a current clock cycle by an arbitration circuit, wherein in case that a specific low address bits of the logical address are the same, the read and/or the write transaction are mapped to the same bank. The disclosure avoids long-term occupation of a certain physical bank with specific low address decoding solution, thereby improving the execution efficiency of the read-write parallel protocol. Furthermore, an arbitration mechanism is introduced to arbitrate read and write conflicts for the same memory bank in each clock cycle.Type: ApplicationFiled: April 27, 2023Publication date: March 7, 2024Inventors: Ze HE, Nanfei WANG, Yingwu ZHANG
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Publication number: 20240078201Abstract: Provide is a FIFO memory system. The FIFO memory system includes: a FIFO memory; a read clock frequency circuit, configured to provide at least two clock signals, wherein the at least two clock signals include a first clock signal and a second clock signal, a frequency of the first clock signal being greater than a frequency of the second clock signal; and a controller, configured to determine a data volume in the FIFO memory, control the read clock frequency circuit to output the first clock signal in a case that the data volume in the FIFO memory is in a first range, or control the read clock frequency circuit to output the second clock signal in a case that the data volume in the FIFO memory is in a second range, the lower limit of the first range being not less than an upper limit of the second range.Type: ApplicationFiled: July 1, 2022Publication date: March 7, 2024Inventors: Xiangye WEI, Liming XIU
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Publication number: 20240078202Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Jungwon SUH, Pankaj DESHMUKH, Shyamkumar THOZIYOOR, Subbarao PALACHARLA
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Publication number: 20240078203Abstract: Disclosed herein is a semiconductor device including a processor that processes input data received via a bus and transmits the process input data as output data via the bus; an input/output data converter that receives the output data via the bus, converts the output data into transmit preGPIO data, and transmits the transmit preGPIO data to the bus; and a GPIO input/output unit that receives the transmit preGPIO data via the bus, converts the transmit preGPIO data into transmit GPIO data, and outputs the transmit GPIO data to at least one GPIO pad.Type: ApplicationFiled: September 1, 2023Publication date: March 7, 2024Applicant: LX SEMICON CO., LTD.Inventor: Jung Yang BAE
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Publication number: 20240078204Abstract: An apparatus for interprocessor communication includes a coupling element, a first transducer, and a second transducer. The coupling element includes a first interface to a first microprocessor and a second interface to a second microprocessor. The first interface and the second interface are connected together in a galvanically-isolated manner for communication purposes. The first transducer includes a third interface to the first microprocessor and a fourth interface to the second transducer. The second transducer includes a fifth interface to the second microprocessor and a sixth interface to the first transducer.Type: ApplicationFiled: August 21, 2023Publication date: March 7, 2024Inventors: Andreas Roehrle, Elias Froehlich, Pushpanathan Pradeep
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Publication number: 20240078205Abstract: A field of printing devices, and a method and device for detecting a connection of a chip to a printing device. A controller in the printing device obtains an actual voltage value of a bus of the printing device when it detects that a plurality of chips connected in parallel become interfacing with the bus, and compares the actual voltage value with a voltage threshold. If the actual voltage value is less than or equal to the voltage threshold, it is determined that each chip is connected to the printing device. If the actual voltage value is greater than the voltage threshold, it is determined that each chip is not connected to the printing device.Type: ApplicationFiled: May 18, 2023Publication date: March 7, 2024Inventor: Zhishu CUI
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Publication number: 20240078206Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.Type: ApplicationFiled: November 6, 2023Publication date: March 7, 2024Inventors: Dheera BALASUBRAMANIAN, Joseph ZBICIAK, Sureshkumar GOVINDARAJ
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Publication number: 20240078207Abstract: A one-to-many communication circuit includes a recommended standard 232 signal transceiver, a main controller area network transceiver, and a plurality of subordinate controller area network transceivers. The recommended standard 232 signal transceiver is used to receive a control signal from a main controller and convert the control signal into a first signal conforming to the recommended standard 232 communication protocol. The main controller area network transceiver is used to convert the first signal into a second signal conforming to the controller area network communication protocol. And each of the plurality of subordinate controller area network transceivers is used to convert the second signal into a third signal conforming to the recommended standard 232 communication protocol.Type: ApplicationFiled: September 22, 2022Publication date: March 7, 2024Applicants: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATIONInventor: You ZHANG
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Publication number: 20240078208Abstract: The embodiments of the present disclosure relate to the technical field of communications, and provide a method and circuit for multiplexing a USB interface, an electronic device and a storage medium. The method includes: acquiring at least one path of level signal, other than a service data signal and a ground signal, in a USB interface; according to a logic result of the at least one path of level signal and a predefined correlation, determining a target port of a target processor corresponding to the logic result as a transmission object of the USB interface, wherein the correlation comprises a logic result of the at least one path of level signal uniquely corresponding to each port of each processor; and transmitting received data to the transmission object by means of the USB interface, and sending data to be sent of the transmission object by means of the USB interface.Type: ApplicationFiled: February 28, 2022Publication date: March 7, 2024Inventor: Zhe CHANG
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INTEGRATED CIRCUIT (IC) DEVICES WITH EFFICIENT PIN-SHARING FOR MULTIPROTOCOL COMMUNICATION INTERFACE
Publication number: 20240078209Abstract: Systems and methods related to communication interface are provided. An interface circuitry arrangement for communication between integrated circuit (IC) devices, the interface circuitry arrangement including serial peripheral interface (SPI) circuitry having an SPI clock port, an SPI data port, and an SPI chip select (CS) port; inter-integrated circuit (I2C) circuitry having an I2C clock port and an I2C data port, wherein the I2C clock port and the SPI clock port are electrically coupled to a first connection port, and wherein the I2C data port and the SPI data port are electrically coupled to a second connection port; pattern detection circuitry to detect a signal pattern at a third connection port, the third connection port electrically coupled to the SPI CS port; and selection circuitry to selectively couple the SPI circuitry or the I2C circuitry to a data path responsive to an output of the pattern detection circuitry.Type: ApplicationFiled: October 7, 2022Publication date: March 7, 2024Applicant: Analog Devices International Unlimited CompanyInventors: Yong Wang, Rengui Luo -
Publication number: 20240078210Abstract: [Object] To perform serial communication at high speed by combining different communication methods with each other. [Solving Means] A communication apparatus includes a communicating unit configured to add identification information identifying a data block to one set of the data block including a serial signal group, the serial signal group being transmitted from a master in synchronism with a clock and complying with SPI (Serial Peripheral Interface), and transmit the one set of the data block to a communication partner apparatus within one frame period of a predetermined communication protocol, or add identification information identifying each of multiple data blocks to the multiple data blocks each including a part of the serial signal group and transmit the multiple data blocks to the communication partner apparatus in multiple frame periods.Type: ApplicationFiled: February 3, 2022Publication date: March 7, 2024Inventors: Toshihisa Hyakudai, Junya Yamada, Satoshi Ota
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Publication number: 20240078211Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.Type: ApplicationFiled: September 14, 2023Publication date: March 7, 2024Inventors: David Shippy, Martin Langhammer, Jeffrey Eastlack
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Publication number: 20240078212Abstract: A systolic array cell is described, the cell including two general-purpose arithmetic logic units (ALUs) and register-file. A plurality of the cells may be configured in a matrix or array, such that the output of the first ALU in a first cell is provided to a second cell to the right of the first cell, and the output of the second ALU in the first cell is provided to a third cell below the first cell. The two ALUs in each cell of the array allow for processing of a different instruction in each cycle.Type: ApplicationFiled: October 4, 2023Publication date: March 7, 2024Inventors: Reginald Clifford Young, Trevor Gale, Sushma Honnavara-Prasad, Paolo Mantovani
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Publication number: 20240078213Abstract: Targetless snapshots of a storage object are characterized in terms of likelihood of access using time-series analysis. Metadata of replication data structures of individual targetless snapshots is maintained in either uncompressed or compressed form based on the characterization of the targetless snapshot. Metadata is compressed at the page level, with same-pages of all replication data structures of cold snapshots of a storage object being compressed together. Compressed pages of targetless snapshot metadata are maintained of storage devices selected based on storage device performance and the time-series characterization of the targetless snapshot.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Applicant: DELL PRODUCTS L.P.Inventors: Ramesh Doddaiah, Sandeep Chandrashekhara
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Publication number: 20240078214Abstract: Operations and Maintenance Design drawing maintenance, As-Built drawing conformance, and Record drawing conformance processes for protecting the integrity of dynamically modified files for Brownfield Assets through all phases of a drawing's lifecycle.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Inventors: Holly Marie Forden, Christopher Alan Bresciani, Laura Lee Allen, Thomas Lloyd Fitzgerald, IV
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Publication number: 20240078215Abstract: Intelligent mapping from created item information to sustainability reference content from a variety of sources can be implemented to facilitate created item footprint management and other sustainability applications. The difficult task of finding appropriate emission factors across a portfolio can be automated. Assisted search can be implemented using enhanced search techniques. Fallback mappings can be implemented to accommodate different levels of granularity during search. A machine learning model can be trained based on a variety of input data, including confirmed mappings, mapping history, and rules. The process of mapping to emission datasets can thus be simplified, enabling footprint calculations to proceed.Type: ApplicationFiled: September 5, 2022Publication date: March 7, 2024Applicant: SAP SEInventors: Swarnava Chatterjee, Nisheeth Agarwal, Ramana Mohanbabu, Stefan Feickert, Himanshu Goyal
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Publication number: 20240078216Abstract: Various methods, apparatuses/systems, and media for data migration readiness of a target data source are disclosed. A processor receives a request having configurable filters and parameters from a consumer service to obtain data; invokes, in response to receiving the request, a service application programming interface (API) for the data; fetches requested data from a legacy data source in response to calling the service API; fetches data corresponding to the same request having the same configurable filters and parameters from a target data source; compare the fetched data from the legacy data source to the fetched data from the target data source; generates, in response to comparing, a data quality validation score; and when it is determined that the data quality validation score is equal to or more that predetermined threshold value, validates the target data source for migration readiness and terminating the legacy data source.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Applicant: JPMorgan Chase Bank, N.A.Inventors: Maxwell EVERS, Prakash RAVI, Amit Kumar MESHRAM, Indrajit BISWAS
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Publication number: 20240078217Abstract: Systems and methods for generating analytical data based on captured audit trails are described. An exemplary method includes generating a natural language preference for the natural language of a document based on an opening action performed by an end user using a client device associated with the end user during a user session; generating a unique transaction key in response to the opening action; correlating subsequent actions relative to the document via the unique transaction key; generating content rich analytical data from an audit trail generated during the user session; obtaining informational content for the end user from informational content stored in a database; translating the obtained informational content; reformatting a native extensible markup language format of the obtained informational content obtained from the database; and providing the translated and formatted informational content to the end user.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Inventors: Andrew Trese, Frank Closset
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Publication number: 20240078218Abstract: The apparatus for validating various kinds of data and a digital twin operation includes a validation target data selector configured to select a target to be validated among various kinds of input data, a data validator configured to validate individual data for each type of data selected for validation, and a data linkage validator configured to validate various kinds of multiple data by linking the various kinds of multiple data in order to detect an error in a process of linking the various kinds of multiple data.Type: ApplicationFiled: August 29, 2023Publication date: March 7, 2024Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Myung-Sun BAEK, Young Soo PARK, Yong Tae LEE, Eui Suk JUNG
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Publication number: 20240078219Abstract: Techniques are disclosed for tuning external invocations utilizing weight-based parameter resampling. In one example, a computer system determines a plurality of samples, each sample being associated with a parameter value of a plurality of potential parameter values of a particular parameter. The computer system assigns weights to each of the parameter values, and then selects a first sample for processing via a first external invocation based on a weight of the parameter value of the first sample. The computer system then determines feedback data associated with a level of performance of the first external invocation. The computer system adjusts the weights of the parameter values of the particular parameter based on the feedback data. The computer system then selects a second sample of the plurality of samples to be processed via execution of a second external invocation based on the adjustment of weights of the parameter values.Type: ApplicationFiled: November 15, 2023Publication date: March 7, 2024Applicant: Oracle International CorporationInventor: Debajyoti Roy
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Publication number: 20240078220Abstract: An example method of tuning a machine learning operation can include receiving a data query comprising a reference to an input data set of a database, generating a plurality of hyperparameter sets based on the input data set, in response to receiving the data query, training a plurality of machine learning models using the plurality of hyperpararneter sets, selecting a first mathine learning model of the plurality of machine learning models based on an accuracy of an output of the first machine learning model, and in response to receiving the data query, returning the output of the first machine learning model.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Inventors: Boxin Jiang, Qiming Jiang
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Publication number: 20240078221Abstract: A temporal graph model is provided that can handle all six graph updates cases: vertex created; vertex deleted; vertex property updated; edge created; edge deleted; and edge property updated. A memory efficient temporal graph storage solution stores the delta change of graph evolution at each update (e.g., instead of storing the whole graph snapshot at each time). Temporal graph querying techniques are described that can determine what the graph looks like at a given time in the past and can perform any graph query on that graph's snapshot at that time as if time traveling back to that time. Also provided are event sourcing techniques of recording and tracing temporal graph updates that make the evolution of the temporal graph explainable. Further provided is a seamless integration with a massive parallel graph processing and storage engine that fully leverages the multicore and multinode cluster computation and storage resources.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Inventors: Renchu Song, Yihui Chen, Brandon Jones Gunaman
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Publication number: 20240078222Abstract: A value is assigned to a rate threshold for adding child nodes to a distinct parent node in a tree data structure. A first datum comprising a first variable assigned a first value and a second variable assigned a first value is added to the tree at a first timestamp, by adding to the first level in the tree a first parent node representing the first variable assigned the first value and adding to the second level in the tree a first child node representing the second variable assigned the first value and connected by a first directed edge from the first parent node. A second datum comprising the first variable assigned the first value and the second variable assigned a second value is received at a second timestamp. The method blocks adding to the second level in the tree a second child node representing the second variable assigned the second value and connected by a second directed edge from the first parent node when a rate based on the first timestamp and the second timestamp exceeds the rate threshold.Type: ApplicationFiled: September 2, 2022Publication date: March 7, 2024Inventors: Daniel W. Brown, Johnathan Hoyt, Sseziwa A. Mukasa, Thomas R. Hobson
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Publication number: 20240078223Abstract: Methods and apparatus to estimate cardinality of users represented across multiple bloom filter arrays are disclosed. Examples includes processor circuitry to execute and/or instantiate instructions to generate a first composite Bloom filter array based on first and second Bloom filter arrays. The processor circuitry is to generate a final composite Bloom filter array based on the first composite Bloom filter array and a third Bloom filter array. Different ones of the first, second, and third Bloom filter arrays representative of different sets of users who accessed media. The first, second, and third Bloom filter arrays including differential privacy noise. The processor circuitry to estimate a cardinality of a union of the first, second, and third Bloom filter arrays based on the final composite Bloom filter array.Type: ApplicationFiled: August 3, 2023Publication date: March 7, 2024Inventors: Michael Sheppard, Jonathan Sullivan, DongBo Cui, Jake Ryan Dailey, Christie Nicole Summers, Diane Morovati Lopez, Molly Poppie
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Publication number: 20240078224Abstract: A system of configuring a database which is distributed across multiple nodes according to a table distribution, e.g., by storing respective tables of the database at respective nodes. A graph partitioning procedure is applied to a graph of the distributed database, with vertices representing tables and edges representing cross-table operations. A distribution of the tables across the nodes is determined based on the partitioning. The storage of the tables is configured according to the determined distribution.Type: ApplicationFiled: August 14, 2023Publication date: March 7, 2024Inventors: Lyubov NAKRYYKO, Suzanne JANSSEN
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Publication number: 20240078225Abstract: A transaction management apparatus, which is a queuing server configured to execute processing of holding a history of transactions between a WEB server (client) and a distributed ledger server in a blockchain system, processing of identifying a transaction updating a sane key based on the history and saving the transaction to a queue, and processing of transmitting the transaction after an elapse of a prescribed time period in which the same key is not updated in the same block.Type: ApplicationFiled: March 7, 2023Publication date: March 7, 2024Applicant: Hitachi, Ltd.Inventor: Nao NISHIJIMA
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Publication number: 20240078226Abstract: A computer-readable storage medium may include executable instructions stored thereon that, when executed by a processor, may be configured to establish a connection to a node of a distributed ledger network that maintains a distributed ledger. The processor may obtain a first dataset from a first user, perform pre-processing on the first dataset to obtain a first data asset based on the first dataset, and store the first data asset. The processor may calculate a first value for the first data asset and generate a first data proposition based on the first data asset. The processor may obtain acceptance data from a second user, which may include data indicating acceptance by the second user of the first data proposition. The processor may transmit a first distributed ledger record to the node of the distributed ledger network.Type: ApplicationFiled: October 23, 2023Publication date: March 7, 2024Applicant: OMNY, Inc.Inventors: Sean Christopher O'BRIEN, Maik Andre LINDNER, Alexis Jorge LIATIS, Alan Michael POHL
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Publication number: 20240078227Abstract: Techniques are disclosed relating to managing data objects. A computer system may access a first application comprising a set of functions and may execute a second application to facilitate execution of the first application. The first application may be written in a different programming language than the second application. The second application may manage, on behalf of the first application, memory resources of data objects that are defined within ones of the set of functions of the first application. The second application may establish, for the data objects, ownership information that indicates which ones of the functions are utilizing the data objects. The ownership information may be usable to determine, upon completion of a function of the set of functions, whether a given one of the data objects can be deallocated based on whether the given data object is being utilized by another function.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Inventors: Rui Zhang, Douglas Doole, Abhijith Anilkumar
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Publication number: 20240078228Abstract: Systems, computer program products, and methods are described herein for script-based querying and aggregation of endpoint data via a directory access protocol. The present invention is configured to deploy a directory access protocol executor to a plurality of endpoint devices, determine an operating system for at least one of the plurality of endpoint devices, select a script to execute at the plurality of endpoint devices, and execute the script via the directory access protocol executor, wherein the script is executed as a login script, wherein the script determines a status of endpoint data at the endpoint, and wherein the endpoint data comprises endpoint tools currently available at the endpoint.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Applicant: BANK OF AMERICA CORPORATIONInventors: Ambarish Regmi, Elizabeth Anne Bueche, Vineesh Chandran Pillai
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Publication number: 20240078229Abstract: Among other things, we describe a method of receiving a portion of metadata from a data source, the portion of metadata describing nodes and edges; generating instances of a data structure representing the portion of metadata, at least one instance of the data structure including an identification value that identifies a corresponding node, one or more property values representing respective properties of the corresponding node, and one or more pointers to respective identification values, each pointer representing an edge associated with a node identified by the corresponding respective identification value; storing the instances of the data structure in random access memory; receiving a query that includes an identification of at least one particular element of data; and using at least one instance of the data structure to cause a display of a computer system to display a representation of lineage of the particular element of data.Type: ApplicationFiled: June 30, 2023Publication date: March 7, 2024Inventors: David Clemens, Dusan Radivojevic, Neil Galarneau
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Publication number: 20240078230Abstract: A method, performed by at least one processor, and an apparatus for augmenting multi-turn text-to-SQL datasets is provided. The method and computer program code include generating an SQL-to-text model to converse with a text-to-SQL model, pre-training the SQL-to-text model and the text-to-SQL model based on input training data, sampling an SQL query as a goal query of an interaction between the SQL-to-text model and the text-to-SQL model, generating the interaction based on the goal query, a current utterance, previous utterances in the interaction, an SQL query from a preceding turn of the interaction, and a serialized database, filtering interactions based on a similarity score between the last turn of the interaction and the goal query, and re-training the SQL-to-text model and the text-to-SQL model based on the input training data and the filtered interactions.Type: ApplicationFiled: August 30, 2022Publication date: March 7, 2024Applicant: TENCENT AMERICA LLCInventor: Linfeng SONG
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Publication number: 20240078231Abstract: A database system is operable to read a plurality of rows from memory of a relational database stored in memory resources. Each of the plurality of rows are assigned to a corresponding one of a plurality of training data subsets of the plurality of rows based on performing a row dispersal process. A plurality of sets of candidate model coefficients are generated based on executing a plurality of parallelized optimization processes. Each set of candidate model coefficients is generated based on executing a corresponding parallelized optimization process upon a corresponding training data subset independently from executing other ones of the plurality of parallelized optimization processes upon other ones of the plurality of training data subsets. A most favorable set of candidate model coefficients is selected from the plurality of sets of candidate model coefficients generated via the plurality of parallelized optimization processes.Type: ApplicationFiled: June 2, 2023Publication date: March 7, 2024Applicant: Ocient Holdings LLCInventor: Jason Arnold
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Publication number: 20240078232Abstract: A database system is operable to generate a query operator execution flow for a query that includes a plurality of operators implementing a plurality of parallelized optimization processes configured to facilitate generating of a machine learning model. The query operator execution flow is executed in conjunction with executing the query based on executing the plurality of operators. Executing each of the plurality of parallelized optimization processes includes generating a corresponding set of candidate model coefficients of a plurality of sets of candidate model coefficients. A corresponding set of candidate model coefficients is based on processing the set of best positions generated via the second type of optimization algorithm. The machine learning model is generated in executing the query based on selection of a most favorable set of candidate model coefficients from a plurality of sets of candidate model coefficients outputted via the plurality of parallelized optimization processes.Type: ApplicationFiled: August 29, 2023Publication date: March 7, 2024Applicant: Ocient Holdings LLCInventor: Jason Arnold
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Publication number: 20240078233Abstract: Techniques for automatic error mitigation in database systems using alternate plans are provided. After receiving a database statement, an error is detected as a result of compiling the database statement. In response to detecting the error, one or more alternate plans that were used to process the database statement or another database statement that is similar to the database statement are identified. A particular alternate plan of the one or more alternate plans is selected. A result of the database statement is generated based on processing the particular alternate plan.Type: ApplicationFiled: September 2, 2022Publication date: March 7, 2024Inventors: Krishna Kantikiran Pasupuleti, Hong Su, Jiakun Li, Mohamed Ziauddin
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Publication number: 20240078234Abstract: An apparatus, a method, and a storage medium for database pagination. The apparatus, method, and storage medium are configured to perform following processes, including: acquiring a pagination request from a user; determining a query parameter based on the pagination request; determining a corresponding pagination pattern and a request data amount based on the query parameter; determining a target query mode based on the request data amount; generating a query task based on the pagination pattern and the target query mode; obtaining at least one first query result based on the query task; determining a target result set based on the at least one first query result; and paging the target result set based on the pagination pattern and the target query mode to obtain multiple pages of pagination data.Type: ApplicationFiled: November 21, 2022Publication date: March 7, 2024Applicant: Starlord (Cayman) LimitedInventors: Chao XIE, Xuan YANG, Xiaofan LUAN, Enwei JIAO
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Publication number: 20240078235Abstract: A system for improving task scheduling on a cloud data platform is provided. A task to be executed using resources of a computing cluster is received. A task execution plan is generated and information about data to be used for the ask is accessed. Resource requirements for executing the task are predicted by applying machine learning to the task execution plan and the information about the data. Assignment data is generated to execute the task on the resources by applying machine learning information about a current state of the resources and predicted resource requirements.Type: ApplicationFiled: July 31, 2023Publication date: March 7, 2024Inventors: Qiming Jiang, Orestis Kostakis, John Reumann
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Publication number: 20240078236Abstract: The data processing system described in this specification enables a user to generate non-application specific statements for controlling execution of an application that executes on a user device (client device). The application can include a browser. The statements can be written to control behavior of a webpage or application at the user. The data processing system enables a user to provide non-application specific statements, such as SQL queries or commands. These non-application specific commands are uniform in syntax an enable the user to access other systems, such as web services, databases, and so forth, using the commands with a uniform syntax.Type: ApplicationFiled: August 24, 2023Publication date: March 7, 2024Inventor: Thomas R. Kennedy
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Publication number: 20240078237Abstract: Aspects of the disclosure are directed to early filtering of candidate rows for a join operator of a query statement before the join operator is evaluated to generate a result set. Early filtering, e.g., before execution of the join operator, reduces the number of candidate rows fetched from a database during a join operator, which can improve the rate at which queries including join operators are executed by a DBMS for the database. One or more Bloom filters or other probabilistic data structures can be produced and consumed according to different join conditions, allowing for early pruning of unqualified rows during a database scan operation.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Inventors: Xiaobin Ma, Xun Cheng
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Publication number: 20240078238Abstract: A system, method, server, and computer readable medium for tracking goal progression. Input is received establishing one or more clients. The one or more clients are individuals receiving treatment or assistance. Each of the one or more clients are assigned to an account. Goals are established for each of the one or more clients. Data associated with each of the one or more clients is compiled as received from one or more monitoring devices. A determination is made where the goals are being met in response to the thresholds for the compiled data. Alerts are automatically communicated in response to the compiled data varying from a threshold to become significant for one of the one or more clients.Type: ApplicationFiled: November 6, 2023Publication date: March 7, 2024Applicant: Data Health Partners, Inc.Inventors: Nathaniel T. Bradley, James Gaynor, Joshua S. Paugh, Paul Arena, Lisa A. Marshall