Abstract: A method for fabricating a semiconductor device includes: providing a substrate having a front surface and a rear surface opposite to the front surface; forming a trench in the front surface of the substrate; forming a gate dielectric layer over the trench; forming a gate electrode that fills a bottom portion of the trench over the gate dielectric layer; forming a sealing layer that includes a first portion covering the gate electrode, the gate dielectric layer, and the front surface of the substrate, and a second portion covering the rear surface of the substrate; selectively removing the second portion of the sealing layer; and performing an annealing process to form a hydrogen treated surface on an interface between the trench and the gate dielectric layer.

Abstract: A method of forming a recessed access device comprises forming a trench in semiconductor material. Sidewalls and a bottom of the trench are lined with low-k gate-insulator material. The low-k gate-insulator material is characterized by its dielectric constant k being no greater than 4.0. Sacrificial material is formed in a bottom portion of the trench over the low-k gate-insulator material and over the trench bottom. A high-k gate-insulator material is formed in an upper portion of the trench above the sacrificial material and laterally-inward of the low-k gate-insulator material that is in the upper portion of the trench. The high-k gate-insulator material is characterized by its dielectric constant k being greater than 4.0. The sacrificial material is replaced with a conductive gate that has its top above a bottom of the high-k gate-insulator material. A pair of source/drain regions is formed in upper portions of the semiconductor material on opposing lateral sides of the trench.

Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a semiconductor layer, and a first conductive layer. The second insulating layer is positioned over the first insulating layer and the island-shaped semiconductor layer is positioned over the second insulating layer. The second insulating layer has an island shape having an end portion outside a region overlapping with the semiconductor layer. The fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, is in contact with part of a top surface of the semiconductor layer, and is in contact with the first insulating layer outside the end portion of the second insulating layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure, and the first gate stack has a first width. The semiconductor device structure further includes a second gate stack over the second channel structure. The second gate stack has a protruding portion extending away from the second channel structures. The protruding portion of the second gate stack has a second width, and half of the first width is greater than the second width.

Abstract: A transistor with a shared gate structure includes an active area and a gate. The active area has a body extending in a first direction on a substrate, and a protrusion extending in a second direction perpendicular to the first direction from a central portion of the body in the first direction. The gate is arranged above the active area to overlap a channel area of the active area, and has an inverted pi () structure that, from a plan view, surrounds on three sides but does not cover a portion of the active area that includes two corner portions of the active area. The active area is divided into a first active area and a second active area by a separation area extending in the second direction and separating the body and a portion of the protrusion. The protrusion is divided into a first portion separated into two sub-portions by the separation area and a second portion, wherein the first portion is between the body and the second portion in the second direction.

Abstract: A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.

Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first oxide, a second oxide over the first oxide, a first insulator over the second oxide, a first conductor over the first insulator, and a second conductor and a third conductor over the second oxide. The second conductor includes a first region and a second region, the third conductor includes a third region and a fourth region, the second region is positioned above the first region, the fourth region is positioned above the third region, and each of the second conductor and the third conductor contains tantalum and nitrogen. The atomic ratio of nitrogen to tantalum in the first region is higher than the atomic ratio of nitrogen to tantalum in the second region, and the atomic ratio of nitrogen to tantalum in the third region is higher than the atomic ratio of nitrogen to tantalum in the fourth region.

Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features.

Abstract: A semiconductor device includes a semiconductor layer structure that comprises silicon carbide, a gate dielectric layer on the semiconductor layer structure, the gate dielectric layer including a base gate dielectric layer that is on the semiconductor layer structure and a capping gate dielectric layer on the base gate dielectric layer opposite the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. A dielectric constant of the capping gate dielectric layer is higher than a dielectric constant of the base gate dielectric layer.

Abstract: Various methods and systems are provided for facilitating the creation of a new and potentially thinner form of dielectric. Alternatively, for a given capacitance, a thicker layer can be created with lower risk of leakage. The present disclosure will enable the creation of physically smaller electronic components. Isotope-Modified Hafnium Dielectric is used to create a dielectric layer with a greater range of dielectric coefficients, which may enable the creation of smaller and/or more reliable electronic components.

Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers.

Abstract: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.

Abstract: A method includes forming a semiconductor fin on a substrate; forming a dielectric layer over the semiconductor fin; forming a metal gate electrode in the dielectric layer and extending across the semiconductor fin; forming a source/drain regions on the semiconductor fin and on opposite sides of the metal gate electrode; performing a first non-zero bias plasma etching process to the metal gate electrode; after performing the first non-zero bias plasma etching process, performing a first zero bias plasma etching process to the metal gate electrode.

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

Abstract: A semiconductor device with high reliability is provided. The present invention relates to a method for manufacturing a transistor including an oxide semiconductor. A stacked-layer structure of an oxide semiconductor and an insulator functioning as a gate insulator is subjected to microwave-excited plasma treatment, whereby the carrier concentration of the oxide semiconductor is reduced and the barrier property of the gate insulator is improved. In addition, a conductor functioning as an electrode and the insulator functioning as a gate insulator are formed in contact with the oxide semiconductor and then the microwave-excited plasma treatment is performed, whereby a high-resistance region and a low-resistance region can be formed in the oxide semiconductor in a self-aligned manner. Moreover, the microwave-excited plasma treatment is performed under an atmosphere containing oxygen with a high pressure, whereby a transistor having favorable electrical characteristics can be provided.

Abstract: Provided is a high ruggedness heterojunction bipolar transistor (HBT), including a collector layer. The collector layer includes a InGaP layer or a wide bandgap layer. The bandgap of the InGaP layer is greater than 1.86 eV.

Abstract: An apparatus includes a substrate; a group III-Nitride barrier layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being arranged at or below the group III-Nitride barrier layer; and a recovery enhancement circuit configured to reduce an impact of an overload received by the gate. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a gate electrode and a single field plate. The source electrode, the drain electrode, and the gate electrode are disposed on the second nitride-based semiconductor layer. The gate electrode is between the source and drain electrodes. The single field plate is disposed over the gate electrode and extends toward the drain electrode. The field plate has a first end part, a second end part and the central part. The first and the second end parts are located at substantially the same height. Portions of the central part are in a position lower than that of the first and second end parts, and the first end part extends laterally in a length greater than a width of the gate electrode.

Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

Abstract: A semiconductor device including a source region formed at one main face of a semiconductor substrate; a drain region formed at the one main face and connected to the source region through a channel region; a gate electrode formed above the channel region; a drift layer formed at the one main face at a position between a lower portion of the gate electrode and the drain region; a trench including an opening in which one end is at the lower portion of the gate electrode and another end is at a position adjacent to the drain region, the trench being formed in the semiconductor substrate at a predetermined depth from the one main face to cut vertically across the drift layer; and an electrical field weakening portion, provided at vicinity of the one end, that weaken an electrical field generated between the source region and the drain region.

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

Abstract: A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate.

Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.

Abstract: A novel oxide semiconductor, a novel oxynitride semiconductor, a transistor including them, or a novel sputtering target is provided. A composite target includes a first region and a second region. The first region includes an insulating material and the second region includes a conductive material. The first region and the second region each include a microcrystal whose diameter is greater than or equal to 0.5 nm and less than or equal to 3 nm or a value in the neighborhood thereof. A semiconductor film is formed using the composite target.

Abstract: A transistor in an embodiment includes an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first region and a second region, a first gate electrode including a region overlapping the oxide semiconductor layer, the first gate electrode being arranged on a surface of the oxide semiconductor layer opposite to the substrate, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a first oxide conductive layer and a second oxide conductive layer between the oxide semiconductor layer and the substrate, the first oxide conductive layer and the second oxide conductive layer each including a region in contact with the oxide semiconductor layer.

Abstract: Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

Abstract: A conductive contact structure of a solar cell is provided, includes a substrate; a semiconductor region; and an electrode. The semiconductor region is disposed on or in the substrate. The electrode is disposed in the semiconductor region. The electrode includes a seed layer in contact with the semiconductor region. The seed layer includes an alloy material, and includes a main component and an improved component. The main component is one or more metals having an average refractive index lower than 2 and a wavelength in a range of 850-1200 nm, and the improved component includes any one or more of Mo, Ni, Ti, W, Cr, Mn, Pd, Bi, Nb, Ta, Pa, Si, and V.

Abstract: A semiconductor structure includes a group IV substrate including group IV dies separated by a scribe line. A group IIIV-chiplet is situated over the group IV substrate at least partially over the scribe line. A group III-V process control monitoring device in the group III-V chiplet is situated over the scribe line. Functional group III-V optoelectronic devices can be situated over the group IV dies.

Abstract: Luminescent solar concentrators (LSCs) based on engineered quantum dots (QDs) are disclosed that include at least one lower band-gap energy LSC layer and at least one higher band-gap energy LSC layer. The higher band-gap energy LSC layer has a higher internal quantum efficiency (IQE) than the lower band-gap energy LSC layer. The lower band-gap energy LSC layer may broadly absorb the remainder of the solar spectrum that is not absorbed by previous layers. An external optical efficiency (EQE) of at least 6%, and in some cases, more than 10%, may be achieved by such LSCs.

Abstract: The present disclosure provides a functional part, a photovoltaic module and a method of manufacturing photovoltaic modules. The functional part is configured to form a photovoltaic module with a cell string that includes a plurality of cells. Adjacent cells of share an overlapped region. The functional part has a first surface facing the cell string and a second surface opposite to the first surface. The functional part includes at least one groove extending from the first surface toward the second surface. A location of each groove corresponds to a location of at least one overlapped region.

Abstract: Provided is a preparation method of a detector material. The present disclosure epitaxially grows a buffer layer on a surface of a gallium arsenide substrate, deposits a silicon dioxide layer on the buffer layer, and etches the silicon dioxide layer on the buffer layer according to a strip pattern by photolithography and etching to form strip growth regions with continuous changes in width. Finally, a molecular beam epitaxy (MBE) technology is used to epitaxially grow the detector material in the strip growth regions under set epitaxy growth conditions. Because of the same mobility of atoms arriving at the surface of the substrate, numbers of atoms migrating to the strip growth regions are different due to different widths of the strip growth regions, such that compositions of the material change with the widths of the strip growth regions or a layer thickness changes with the widths of the strip growth regions.

Abstract: A method for annealing an absorber layer is disclosed, the method including contacting a surface of the absorber layer with an annealing material provided as a gel. The annealing material comprises cadmium chloride and a thickening agent. A viscosity of the gel of the annealing material is greater than or equal to 5 millipascal seconds.

Abstract: Described herein is an electric injection annealing test device for crystalline silicon photovoltaic solar cells, the test device comprises a dark box, a sample test bench, a temperature control device, a power supply device and an image acquisition device. The sample test bench, the temperature control device, the power supply device and the image acquisition device are located in the dark box; the sample test bench is used to place a solar cell sheet; the temperature control device is used to control a temperature of the solar cell sheet; the power supply device provides a current to the solar cell sheet, the image acquisition device is used to acquire electroluminescence images of the solar cell sheet under different temperatures and current conditions.

Abstract: Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and in a direction away from the rear surface and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure being less than or equal to 2 ?m; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer; and a second passivation layer located on a surface of the doped conductive layer.

Abstract: An electroluminescent display panel and a display device are provided. In the embodiments of the disclosure, a photosensitive component is arranged in the photosensitive component arranging region. The extending line of at least one line is arranged in the photosensitive component arranging region so that the orthographic projection of the extending line on the light-emitting surface of the electroluminescent display panel overlaps with the first pixels in the first and second specific pixel groups in the photosensitive component arranging area; the first and second specific pixel groups include respective first pixels located in first straight lines of the second pixels correspondingly connected to two adjacent signal lines, the first and second specific pixel groups are adjacent in the second direction, and the first straight lines extend in the first direction.

Abstract: A semiconductor light emitting device includes a light emitting structure having a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer, a transparent electrode layer on the second conductivity-type semiconductor layer and spaced apart from an edge of the second conductivity-type semiconductor layer, a first insulating layer on the light emitting structure to cover the transparent electrode layer and including a plurality of holes connected to the transparent electrode layer, and a reflective electrode layer on the first insulating layer and connected to the transparent electrode layer through the plurality of holes.

Abstract: A method for manufacturing a light-emitting device includes: forming a cover, which comprises: sandwiching a fixing member by a molding device, injecting a light-transmissive material into a space defined in the molding device, and hardening or curing the injected light-transmissive material, wherein the formed cover comprises an upper portion, a sidewall, and a recess, the cover being integrated with the fixing member such that the fixing member projects from a part of an outer lateral surface of the sidewall; disposing a light-transmissive member on a light extraction surface of a light-emitting element to be disposed on a substrate; and disposing the cover so that the light-emitting element is housed in the recess. The fixing member is formed of a material that is deformable due to a pressing force generated in the event of an engagement with a counterpart member.

Abstract: An UV or DUV light-emitting diode package includes: a foundation; a first metal layer, a second metal layer, and third metal layer formed on a top surface of the foundation, wherein the first metal layer and the second metal layer are electrically isolated by a first gap, the third metal layer surrounds the first and second metal layers and is electrically isolated from the first and second metal layers by a second gap; a lens attached to the top surface of the foundation, wherein a cavity is formed between the foundation and the lens; a chip disposed in the cavity, wherein an anode of the chip is electrically connected to the first metal layer and a cathode of the chip is electrically connected to the second metal layer; and a fluid encapsulate, wherein the cavity is fully or partially filled with the fluid encapsulate.

Abstract: A light emitting device includes: a base member having a first surface including a first region and a second region; a first frame provided on the base member and surrounding the first region; a light emitting element provided on the base member in the first region; a light-transmissive first member provided inward of the first frame, and covering the light emitting element; an electronic component provided on the base member in the second region and electrically connected with the light emitting element; and a plurality of pin holes arrayed in a first direction and electrically connected with the electronic component, the first direction being orthogonal to a thickness direction of the base member. The electronic component is provided on a side opposite the plurality of pin holes with respect to the light emitting element in a second direction that is orthogonal to the thickness direction and the first direction.

Abstract: An optoelectronic component may include a layer sequence having an active layer configured to emit an electromagnetic primary radiation and a conversion element arranged in the beam path of the primary radiation. The conversion element may include a conversion layer and a conversion potting arranged over the conversion layer. The conversion layer may include a first matrix material and a converter material, and the conversion potting may include a second matrix material and a converter material. There may be a jump in concentration of converter material between the conversion layer and the conversion potting.

Abstract: Solid-state radiation transducer (SSRT) devices and methods of manufacturing and using SSRT devices are disclosed herein. One embodiment of the SSRT device includes a radiation transducer (e.g., a light-emitting diode) and a transmissive support assembly including a transmissive support member, such as a transmissive support member including a converter material. A lead can be positioned at a back side of the transmissive support member. The radiation transducer can be flip-chip mounted to the transmissive support assembly. For example, a solder connection can be present between a contact of the radiation transducer and the lead of the transmissive support assembly.

Abstract: Discussed is a bolting device that effectively protects an internal configuration of a battery pack and increases manufacturing efficiency during a bolting operation. The bolting device for manufacturing a battery pack includes an electric screwdriver provided with a rotation motor; a driver bit connected to the rotation motor to enable a rotation movement and configured to rotate a bolt; a bit guide member provided with a hollow tube such that the driver bit is inserted into an inside of the hollow tube to be movable; and a guide jig provided with a main body configured to be mounted on an upper portion of a pack housing, the main body having a plate shape and having at least one through hole, and a fixing member inserted into the through hole and mounted therein, and having an insertion hole.

Abstract: A separator having low resistance, suitable porosity and electrolyte retention while ensuring heat resistance is provided. The separator includes a porous substrate and a low-resistance coating layer formed on at least one surface of the porous substrate, wherein the low-resistance coating layer includes node(s) containing inorganic particles and a polymer resin covering at least a part of the surfaces of inorganic particles, and filament(s) formed from the polymer resin of the node in a thread-like shape, at least one filament extended from one node is formed, and the filaments are arranged in such a manner that they connect one node with another node.

Abstract: Slurry compositions, tape casting binder systems and fabrication methods for the fabrication of lithium-garnet electrolyte scaffolds for use in solid state batteries and other devices are provided. Slurry compositions may be optimized mixtures of LLZO powder, a dispersant, a lithium salt, a wetting agent a binder, a plasticizer and at least one solvent. The optimized ceramic slurry compositions may include MgO as a sintering additive to improve density and ionic conductivity of the doped-LLZO sheets and produce a fine-grained microstructure. Sintering protocols for cast slurries of commercially available doped LLZO powders eliminate the requirement of mother-powder coverings or externally applied pressure. An environmentally friendly water-based system using methylcellulose as a binder is also provided producing green tape and final properties comparable to those obtained with organic solvent-based systems.

Abstract: A solid-state battery includes a first electrode; a second electrode having a first side facing a first side of the first electrode and spaced from the first electrode; and a solid electrolyte at least partially disposed in a space between the first electrode and the second electrode for providing a path for metal ions associated with the first electrode and/or the second electrode to move through. The metal ions are kept differentially distributed along the path.