Abstract: Provided is a method of high-density pattern forming, which includes: providing a substrate; forming a hard mask layer on the substrate; forming a sacrificial layer on the hard mask layer; forming photoresists arranged at intervals on the sacrificial layer; etching the sacrificial layer to enable the sacrificial layer to form a mandrel corresponding to the photoresist one by one, wherein a cross-sectional size of the mandrel gradually decreases from an end of the mandrel away from the hard mask layer to an end close to the hard mask layer; forming an isolation layer on the mandrel; removing the isolation layer on the top of the mandrel, the isolation layer covering the hard mask layer, and the mandrel to form an isolation sidewall pattern; and transferring the isolation sidewall pattern to the hard mask layer.

Abstract: A wafer processing method for processing a wafer having a chamfered portion formed at a periphery thereof includes a tape attaching step of attaching a protective tape to a front surface of the wafer and making a diameter of the protective tape coincide with a diameter of the wafer; a grinding step of grinding a back surface of the wafer held by a holding table with use of grinding stones so as to thin the wafer to a thickness thinner than half of an original thickness, to reduce the diameter of the wafer, and to form a protruding portion where the protective tape protrudes from the wafer; and a contracting step of heating and contracting the protruding portion of the protective tape after the grinding step is carried out.

Abstract: Described herein are etching solutions and method of using the etching solutions suitable for etching aluminum nitride (AlN) from a semiconductor substrate during the manufacture of a semiconductor device comprising AlN and silicon material without harming the silicon material. The etching solution comprises a cationic surfactant, water, a base, and a water-miscible organic solvent.

Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.

Abstract: Embodiments of methods and apparatus for reducing warpage of a substrate are provided herein. In some embodiments, a method for reducing warpage of a substrate includes: applying an epoxy mold over a plurality of dies on the substrate in a dispenser tool; placing the substrate on a pedestal in a curing chamber, wherein the substrate has an expected post-cure deflection in a first direction; inducing a curvature on the substrate in a direction opposite the first direction; and curing the substrate by heating the substrate in the curing chamber.

Abstract: A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.

Abstract: A stack package and a method of manufacturing the stack package are provided. The method includes: attaching a first semiconductor device onto a first surface of a first package substrate; attaching a molding resin material layer onto a first surface of a second package substrate; arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other; compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and hardening the reflowed molding resin material layer.

Abstract: The present disclosure provides a semiconductor manufacturing method and a system therefore. The semiconductor manufacturing method includes: providing a gas from a container through an outlet to a semiconductor wafer manufacturing equipment, wherein a control valve is connected to the outlet to control a gas flow; retrieving a set of parameters corresponding to the gas flow; and determining a nominal position of the control valve by incorporating the set of parameters through a processor in order to provide a desired flow passage into the semiconductor wafer manufacturing equipment, wherein the semiconductor wafer manufacturing equipment includes a plurality of independent reaction chambers, wherein each reaction chamber is individually supplied with a gas pipe, and each gas pipe receives the gas from the container.

Abstract: A substrate cleaning and drying system includes a cleaning station, a drying station positioned adjacent the cleaning station, a cleaner robot to transfer a substrate from the cleaning station to the drying station, an aligner stage adjacent to the drying station, a robot arm rotatable between a substantially vertical first position for receiving the substrate from the drying station and a substantially horizontal second position for releasing the substrate onto the aligner stage, and a factory interface robot to transfer a substrate from the aligner stage into a factory interface module while in a horizontal orientation. The aligner stage includes a rotatable support to hold the substrate in a substantially horizontal orientation and to rotate the substrate to a desired orientation.

Abstract: A semiconductor manufacturing apparatus includes a tool performing joining by ultrasonic vibration while applying a load to a metal terminal. The tool includes a plurality of protrusions arranged along the X-axis direction and the Y-axis direction on a pressing surface in a rectangular shape at a tip end portion facing the metal terminal. The intervals between the plurality of protrusions are equal in the X direction of the pressing surface, and are larger on the inner peripheral side than on the outer peripheral side in the Y-axis direction of the pressing surface.

Abstract: A wafer support device includes a support base having a wafer-facing surface, the support base comprising a heater, and an electrostatic chuck supported by the support base, the electrostatic chuck having an attraction surface configured to attract a wafer for wafer processing. During the wafer processing, the wafer-facing surface and the attraction surface are positioned at respective different positions in a direction perpendicular to the wafer-facing surface so that the attraction surface is separated from the wafer-facing surface by a distance.

Abstract: An ultraviolet (UV) lamp assembly of a UV curing tool is provided for curing a low dielectric constant (low-k) material layer of a semiconductor wafer. The UV lamp assembly includes: a UV lamp which emits UV light; a first reflector arranged proximate to a first side of the UV lamp, the first reflector including a first surface facing the UV lamp from which UV light emitted by the UV lamp is at least partially reflected; and a UV reflective coating partially coating the first surface of the reflector. Suitably, a plurality of areas of the first surface of the reflector remain uncoated with the UV reflective coating and the plurality of uncoated areas are arranged to promote a uniform exposure of the semiconductor wafer to UV irradiation.

Abstract: A substrate processing system configured to process a substrate includes a carry-in/out unit configured to carry the substrate from/to an outside thereof; a processing unit configured to process a processing surface of the substrate; a cleaning unit provided between the carry-in/out unit and the processing unit when viewed from a top, and configured to clean the processing surface after being processed in the processing unit; a first transfer unit stacked on top of the cleaning unit, and configured to transfer the substrate; and a second transfer unit provided between the processing unit and the first transfer unit when viewed from the top, and configured to transfer the substrate. The first transfer unit transfers the substrate between the carry-in/out unit and the second transfer unit. The second transfer unit transfers the substrate between the first transfer unit and the processing unit and between the processing unit and the cleaning unit.

Abstract: A control method includes: calculating a correction value after a predetermined process is executed; and controlling a control target based on an output value of at least one of a real sensor and a virtual sensor during execution of the predetermined process. The calculating includes correcting an output value of the virtual sensor. The controlling includes: controlling the control target based on an output value of the real sensor while monitoring a failure of the real sensor; correcting an output value of the virtual sensor with the correction value when the real sensor fails; and switching from a control based on the output value of the real sensor to a control based on the output value of the virtual sensor after the correcting the output value of the virtual sensor.

Abstract: A monitoring device for monitoring a fabrication process in a fabrication system. The monitored fabrication system includes a process chamber and a plurality of flow components. A quartz crystal microbalance (QCM) sensor monitors one flow component of the plurality of flow components of the fabrication system and is configured for exposure to a process chemistry in the one flow component during the fabrication process. A controller measures resonance frequency shifts of the QCM sensor due to interactions between the QCM sensor and the process chemistry in the one flow component during the fabrication process. The controller determines a parameter of the fabrication process in the process chamber as a function of the measured resonance frequency shifts of the QCM sensor within the one flow component.

Abstract: An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing; a load port; a robot arm inside the housing; and a processor. The load port is configured to load a wafer carrier into the housing. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.

Abstract: There is provided a technique that includes a substrate support including a support column made of metal and a plurality of supports installed at the support column and configured to support a plurality of substrates in multiple stages; a process chamber configured to accommodate the plurality of substrates supported by the substrate support; and a heater configured to heat the plurality of substrates accommodated in the process chamber, wherein the plurality of supports includes at least a contact portion configured to make contact with the plurality of substrates and made of at least one selected from the group of a metal oxide and a non-metal material.

Abstract: A system and computer-implemented method are provided for manufacturing a semiconductor electronic device. An assembler receives a jig and a boat supporting a die. The assembler includes a separator that separates the jig into a first jig portion and a second jig portion and a loader that positions the boat between the first jig portion and the second jig portion. A robot receives an assembly prepared by the assembler and manipulates a locking system that fixes an alignment of the boat relative to the first jig portion and the second jig portion to form a locked assembly. A process chamber receives the locked assembly and subjects the locked assembly to a fabrication operation.

Abstract: A poling apparatus for poling a polymer thin film formed on a workpiece carried by a workpiece carrier. The workpiece has grounding electrodes and grounding pads located at edges, and a thin film covering the grounding electrodes but exposing the grounding pads. The workpiece carrier has carrier electrodes located around the workpiece and inside grounding ports at the bottom. The poling apparatus includes, in a poling chamber, a poling source generating a plasma, a Z-elevator to raise the workpiece carrier toward the poling source using the grounding ports, and grounding mechanisms including downwardly biased electrical contacts which, when the workpiece carrier is raised by the Z-elevator, connect the grounding pads of the workpiece with the carrier electrodes, to ground the workpiece. The poling apparatus additionally includes preparation platform and transfer platform with conveyer systems with rollers and Z-elevators to move the workpiece carrier in and out of the poling chamber.

Abstract: A semiconductor wafer cassette roller type transportation structure system includes a roller type transportation structure body, a rotating transportation structure body, and a lateral movement transportation structure body. The roller type transportation structure system includes connected left and right supporting frames. A plurality of large rollers are provided on an inner surface end of each of the right and left supporting frames. A plurality of small rollers are provided under the large rollers. A plurality of driving wheels are provided under the large rollers. The large and small rollers are driven by a driving belt. The driving wheels can linearly move a wafer cassette. In response to the roller type transportation structure body transporting the wafer cassette, the rotating transportation structure body rotates to change a movement direction of the wafer cassette, and the lateral movement transportation structure body transports the wafer cassette along a lateral movement direction.

Abstract: An apparatus including a first base plate, where the first base plate is configured to have at least one linear drive component and/or at least one power coupling component connected to a top side of the first base plate, where the first base plate is configured to be located inside a vacuum chamber; and a plurality of rails or transport guides on the top side of the first base plate. An end of the first base plate includes at least one alignment feature configured to align an end of the first base plate to an end of a second base plate. The first base plate is configured to provide, in combination with the second base plate, a structural platform inside the vacuum chamber for a robot drive to move in the vacuum chamber along the plurality of transport guides.

Abstract: A pre-aligner for pre-aligning a wafer having a notch. The pre-aligner includes a wafer platform having a wafer receiving surface, and a drive device. A detector is provided to detect the notch, and a memory is provided to store a notch window defining a range of angles in which the notch is predicted to be located in relation to a start position. A controller performs a pre-alignment operation where the wafer is rotated from the start position to an alignment location. The controller performs the operation such that the wafer is rotated at maximum acceleration/deceleration values from the start position to a notch location detected by the detector: where the operation is limited to a maximum velocity for rotation of the wafer from the start position to a notch window; and where the operation is limited to a scanning velocity within the notch window until the notch location is detected.

Abstract: Exemplary substrate support assemblies may include an electrostatic chuck body that defines a substrate support surface. The substrate support surface may define a plurality of protrusions that extend upward from the substrate support surface. A density of the plurality of protrusions within an outer region of the substrate support surface may be greater than in an inner region of the substrate support surface. The substrate support assemblies may include a support stem coupled with the electrostatic chuck body. The substrate support assemblies may include an electrode embedded within the electrostatic chuck body.

Abstract: A semiconductor device including: a trench defining an active region in a substrate; a first semiconductor liner formed over the trench; a second semiconductor liner formed over the first semiconductor liner; and a device isolation layer formed over the second semiconductor liner and filling the trench. Disclosed is also a method for fabricating a semiconductor device, the method including: forming a trench defining an active region in a substrate; forming a plurality of semiconductor liners over the trench; performing pretreatment before forming each of the semiconductor liners; and performing post-treatment after forming each of the semiconductor liners.

Abstract: A contact window structure and a method for forming the contact window structure are provided. The method includes: an etching spacer is formed on a surface of a target layer, and a dielectric layer covering a substrate, the target layer and the etching spacer is formed; the dielectric layer is etched to form an etching hole in the dielectric layer, a bottom of the etching hole exposing a top surface of the etching spacer; and the etching spacer is removed along the etching hole to form an etching channel communicating with the etching hole, the etching channel exposing a portion of the surface of the target layer and constituting a contact window structure with the etching hole.

Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.

Abstract: The method for preparing the semiconductor structure includes: providing a substrate; successively arranging a first conductive material layer, a barrier material layer, a second conductive material layer and a first dielectric material layer on the substrate stacked onto one another; forming a supporting layer on the first dielectric material layer, in which the supporting layer includes a plurality of supporting pattern structures spaced apart from each other, and a first trench is provided between two adjacent supporting pattern structures; forming a second dielectric layer, in which the second dielectric layer fills the first trench; etching the second dielectric layer, the first dielectric material layer, the second conductive material layer, the barrier material layer and the first conductive material layer to form a bit line array; and forming a bit line protective layer.

Abstract: A semiconductor device includes a gate structure on a substrate and a dielectric film stack over the gate structure and the substrate, where the dielectric film stack includes a first inter layer dielectric (ILD) over the substrate and the gate structure, a barrier layer over the first ILD, a second ILD over the barrier layer, and a contact extending through the dielectric film stack. An upper portion of a contact sidewall has a first slope, a lower portion of the contact sidewall has a second slope different from the first slope, and a transition from the first slope to the second slope occurs at a portion of the contact extending through the barrier layer.

Abstract: A protective film forming agent for plasma dicing which can favorably form an opening (processed groove) of a desired shape by irradiation of a laser beam, at a desired position of the protective film, upon producing semiconductor chips by cutting a semiconductor substrate by plasma dicing, and a method for producing a semiconductor chip using this protective film forming agent. The protective film forming agent comprises a water-soluble resin, a light absorber, and a solvent, and a weight loss rate when the temperature is raised to 500° C. in thermogravimetry of the water-soluble resin is at least 80 weight %.

Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.

Abstract: A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed.

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

Abstract: A method is provided for producing a plurality of transistors on a substrate comprising at least two adjacent active areas separated by at least one electrically-isolating area, each transistor of the plurality of transistors including a gate having a silicided portion, and first and second spacers on either side of the gate, the first spacers being located on sides of the gate and the second spacers being located on sides of the first spacers. The method includes forming the gates of the transistors, forming the first spacers, forming the second spacers, siliciding the gates so as to form the silicided portions of the gates, and removing the second spacers. The removal of the second spacers takes place during the silicidation of the gates and before the silicided portions are fully formed.

Abstract: Controlling an etch process applied to a multi-layered structure, by calculating a spectral derivative of reflectance of an illuminated region of interest of a multi-layered structure during an etch process applied to the multi-layered structure, identifying in the spectral derivative a discontinuity that indicates that an edge of a void formed by the etch process at the region of interest has crossed a layer boundary of the multi-layered structure, determining that the crossed layer boundary corresponds to a preselected layer boundary of the multi-layered structure, and applying a predefined control action to the etch process responsive to determining that the crossed layer boundary corresponds to the preselected layer boundary of the multi-layered structure.

Abstract: A semiconductor memory according to an embodiment includes first and second areas, an active region, a non-active region, a first stacked body, a plurality of first pillars, a first contact, a second stacked body, and a second contact. The active region includes part of each of the first and second areas. The non-active region includes part of each of the first and second areas. The second stacked body is in the non-active region. The second stacked body includes second insulators and second conductors which are alternately stacked. A second contact is in contact with a second conductor in a first interconnect layer and a second conductor in a second interconnect layer.

Abstract: A semiconductor package includes a substrate, a package structure, and a lid structure. The package structure is disposed on the substrate. The lid structure is disposed over substrate, wherein the lid structure includes a main body covering and surrounding the package structure and a plurality of rib portions protruded from the main body and extended toward the package structure.

Abstract: A composite substrate includes a base layer formed of a composite material containing diamond and a metal, the base layer a first surface, and a second surface opposite to the first surface; a flat layer having a lower surface bonded to the first surface of the base layer, and an upper surface having a surface roughness Ra of 10 nm or less; and an insulating layer directly bonded to the upper surface of the flat layer.

Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

Abstract: A method of forming a semiconductor device, the method including the steps of providing a metal component having a top surface, and providing a passivation layer over the metal component such that an outer layer of the passivation layer is substantially planar and does not extend below the top surface of the metal component.

Abstract: An electronic assembly includes a first printed wiring board (PWB) on a first side of the electronic assembly, and a first stiffener secured to the first PWB. The electronic assembly also includes a second PWB on a second side of the electronic assembly, opposite the first side, a second stiffener secured to the second PWB, and a center stiffener seated in the second stiffener and between the first stiffener and the second stiffener. The center stiffener has a first side facing the first stiffener, a second side that is opposite the first side and facing the second stiffener, a first end, and a second end, opposite the first end. Electronic devices are secured to the center stiffener. The center stiffener dissipates heat from the electronic devices, and the electronic devices include power dies.

Abstract: A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.

Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer, where each of the plurality of heat sink interconnects is directly coupled to the heat transfer layer in a vertical orientation.

Abstract: An integrated circuit (IC) package with an embedded heat spreader in a redistribution layer (RDL) is provided. IC packaging facilitates a high density package for ICs, including monolithic microwave integrated circuits (MMICs). However, IC packaging may result in reduced heat removal from an IC, decreasing radio frequency (RF) circuit performance. In an exemplary aspect, an IC package is provided which incorporates an embedded heat spreader within a dielectric layer of an RDL coupled to an IC die. The embedded heat spreader provides efficient heat transfer, robust RF performance, and operation through millimeter wave (mmW) frequencies, all in a miniature low-cost, low-profile surface mountable (SM) package.

Abstract: A package has a cavity to be sealed by a lid. The package includes a heat sink having a coefficient of thermal expansion of 9 ppm/° C. or more and 15 ppm/° C. or less from 25° C. to 100° C. and a frame disposed on the heat sink, made of ceramics, and surrounding the cavity in plan view. An outer edge of the frame includes a first linear portion extending along a first direction, a second linear portion extending along a second direction orthogonal to the first direction, and a chamfer connecting the first linear portion and the second linear portion in plan view.

Abstract: Provided is a semiconductor device having excellent heat dissipation capacity and electromagnetic wave suppression effect. A semiconductor device 1 includes a semiconductor element 30; a conductive cooling member 40 provided above the semiconductor element 30, a conductive thermally conductive member 10 that is provided between the semiconductor element 30 and the cooling member 40 and contains a cured resin. The conductive thermally conductive member 10 is connected to a ground 60 in the substrate 50 to electrically connect the cooling member 40 and the ground 60.

Abstract: A semiconductor apparatus with a heat dissipation conduit in a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device including the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes: a carrier substrate having a first region and a second region adjacent to each other; a semiconductor device on the first region; and an interconnection structure on the second region, wherein the interconnection structure includes: an electrical isolation layer; a conductive structure in the electrical isolation layer, wherein at least a part of components require to be electrically connected in the semiconductor device is in contact with and therefore electrically connected to the conductive structure in a lateral direction, wherein the conductive structure is located at a corresponding height in the interconnection structure; and a heat dissipation conduit in the electrical isolation layer.

Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.