Abstract: Probes for contacting electronic components include compliant modules stacked in a serial configuration, which are supported by a sheath, exoskeleton, or endoskeleton which allows for linear longitudinal compression of probe ends toward one another wherein the compliant elements within the compliant modules include planar springs (when unbiased). Alternatively, probes may be formed from single modules or back-to-back modules that may share a common base/standoff. Modules may allow for lateral and/or longitudinal alignment relative to array structures or other modules. Planar springs may be spirals, interlaced spirals having common or offset longitudinal levels, with similar or different rotational orientations that are functionally joined, and planar springs may transition into multiple thinner planar spring elements along their length. Compression of probe tips toward one another may cause portions of spring elements to move closer together or further apart.

Abstract: Probe structures having multiple beams are joined at their ends with at least one functioning as a current carrying beam (i.e. an electrical beam) and at least one functioning as a structural beam (i.e. non-current carrying beam) that conveys desired mechanical or structural parameters for the probe such as spring force, scrubbing, over travel, operational stability and repeatability, and the like. The current carrying beam provides little with regard to mechanical properties, and the structural beam is separated from the current carrying beam along a majority of its length and does not pass current between the probe ends due to its dielectric nature or the presence of at least one dielectric barrier located at an end or along its length.

Abstract: Improved probe arrays (e.g. buckling beam arrays) are formed using probe preforms that have desired array spacings but not intended individual probe configurations. Groups of preforms are engaged with one or more deformation plates that cause permanent (i.e. plastic) deformation of the probe preforms to provide probe from deformed probe preforms with desired probe configurations where at least part of the deformation of multiple probe preforms occur simultaneously and where multiple deformations of individual probe preforms may occur in parallel or in series and where deformation is provided by substantially lateral displacement of the one or more deformation plates relative to a permanent or temporary array substrate or one or more different deformation plates. In some variations, the substantial lateral displacement may be accompanied by longitudinal shifting as necessary to accommodate for change in relative longitudinal positioning as lateral displacement occurs.

Abstract: Probes for testing (e.g. wafer level testing or socket level testing) of electronic devices (e.g. semiconductor devices) and more particularly, arrays of such probes are provided. Probes are formed by initially fabricating probe preforms in batch with bases and/or ends located in array patterns, directly or indirectly on one or more build substrates with the arrayed preforms being in a longitudinally compressed state and whereafter the preforms are longitudinally plastically deformed to yield probes or partially formed probes with extended longitudinal lengths. Probes may be formed with deformable spring elements formed from one or more single layers which are joined by vertical elements located on other layers or they may be formed by spring elements that are formed as multi-layer structures. Arrays may include probe preforms with laterally overlapping or interlaced structures (but longitudinally displaced) which may remain laterally overlapping or become laterally displaced upon plastic deformation.

Abstract: A magnetic sensor includes: a sensor chip having magnetic layers magnetically coupled to each other through a magnetic gap and a magnetic sensing element disposed on a magnetic path formed by the magnetic gap; an external magnetic member magnetically coupled to one of the magnetic layer 21; and a measuring current coil wound around the external magnetic member and through which a current for generating a magnetic field to be measured flows. The magnetic sensing element 31 and the magnetic layers are thus integrated in the sensor chip, so that the magnetic gap can be designed to be very small in width, and a leakage magnetic field can be applied in large amounts to the magnetic sensing element. Thus, even when the current I flowing in the measuring current coil is weak, a magnetic field generated by the current I can be detected with high sensitivity.

Abstract: A magnetic current sensor includes a magnetic circuit, an electrical winding, an insulating coil, and two leads respectively mounted on terminal parts of the coil and connected to ends of the winding. Each lead includes a main body, received in complementary fashion in a recess of the coil, and elongate along a body axis transversal to a coil axis. Each lead also includes two tongues protruding from a lateral face of the main body, each running from an end joined to the main body up to a free end. At their joining end, the tongues extend along respective tongue axes, which are parallel and each extend transversely to the coil axis and to the body axis. Between their joining end and their free end, the tongues are folded against the same lateral wall of the recess so as to keep the lead in position.

Abstract: A voltage supervisor (VS) or voltage sensing circuitry or architecture that can detect fast voltage transients. To detect fast voltage transients, a dedicated differential pair is routed between a point of load, such as a die or other chip, processor, etc., and the circuitry of the voltage supervisor. By connecting the differential pair at the point of load, fast voltage transients may be detected at the load level (e.g., at the point of load) and thereafter used to enable, disable, and/or restart an electronic device, such as a die, chip, processor, or other electronic component or system.

Abstract: A method for sensing current includes (a) generating a first current signal representing magnitude of current flowing through a sensing element while a first switching device is in its on-state and a second switching device is in its off-state, each of the first switching device and the second switching device being electrically coupled to the sensing element, (b) generating a second current signal representing magnitude of current flowing through the sensing element while the first switching device is in its off-state and the second switching device is in its on-state, and (c) generating a composite current signal from the first current signal and the second current signal, the composite current signal representing magnitude of current flowing through the sensing element.

Abstract: To enable necessary information to be obtained from a sensor when necessary. An information processing device includes a processing unit including a memory, a sensing unit, a condition storage unit configured to store a condition for outputting a situation value indicating a state according to a situation in which the information processing device is disposed, a determination unit configured to determine whether the condition is satisfied, a situation value calculation unit configured to calculate the situation value based on a measured value acquired by the sensing unit, and an output unit configured to output the situation value when the condition is satisfied.

Abstract: A current sensing apparatus may include a common mode core surrounding two or more current conductors and a current sensing element proximate the common mode core.

Abstract: A laundry machine comprising: a drum; a motor to rotate the drum; electric heating element(s) configured to produce heat; an airflow path from the heating element(s) to the drum; an analog to digital converter (ADC) configured to sample an AC voltage from a first power line of a group of power lines connected to the machine; and a controller configured to: (a) trigger the ADC to sample an AC voltage from the first power line, (b) determine a timing of occurrence of a peak value of the sampled AC voltage from the first power line, (c) compare the timing of occurrence of the peak value to predetermined timing signatures, (d) choose one of the timing signatures based on the comparison, and (e) control power to the electric heating element based on the chosen timing signature. Methods of operating a laundry washing machine are also provided.

Abstract: In an aspect, measurement processing circuitry may obtain, from a sensor, a first measured value of a measured object, the first measured value corresponding to a first power consumption level of the measured object at a first time point. The measurement processing circuitry may obtain, from the sensor, one or more second measured values of the measured object, the one or more second measured values corresponding to one or more second power consumption levels of the measured object at one or more second time points earlier than the first time point. The measurement processing circuitry may determine a corrected value based on the first measured value and the one or more second measured values, the corrected value representing the first power consumption level of the measured object at the first time point.

Abstract: Provided are a power level acquisition circuit and apparatus, used for solving the problem in the prior art, when conducting reinforced insulation testing, of work hour wastage and safety hazards.

Abstract: A measurement system includes an input port, a signal splitter, first and second signal paths, an analysis circuit, and a control circuit. The input port is configured to receive an input signal to be measured. The signal splitter is configured to split the input signal into a first signal that is forwarded to the first signal path and a second signal that is forwarded to the second signal path. The analysis circuit is connected to the first signal path and the second signal path so as to receive both a first processed signal and a second processed signal. The analysis circuit is configured to a complex-valued product signal from the processed signals average the complex-valued product signal over a predetermined number of samples, and determine an averaged power signal based thereon. The control circuit is configured to directly or indirectly add an offset to the averaged power signal.

Abstract: The present disclosure provides a measurement application device, comprising a number of signal measurement paths, each one of the number of signal measurement paths comprising a plurality of signal processing components, and a scheduler coupled to the number of signal measurement paths, wherein the scheduler is configured to selectively control at least one of the signal measurement paths depending on a selected one of a number of operating modes to power down at least one of the signal processing components, or to power up at least one of the signal processing components. The present disclosure further provides a measurement application setup and a respective method.

Abstract: A wideband variable impedance load for high volume manufacturing qualification and diagnostic testing of a radio frequency power source, an impedance matching network and RF sensors for generating plasma in a semiconductor plasma chamber for semiconductor fabrication processes. The wideband variable impedance load may comprise a fixed value resistance operable at a plurality of frequencies and coupled with a variable impedance network capable of transforming the fixed value resistance into a wide range of complex impedances at the plurality of frequencies. Response times and match tuning element position repeatability may be verified. Automatic testing, verification and qualification of production and field installed radio frequency power sources for plasma generation are easily performed.

Abstract: The present disclosure provides a thin film sensor and a manufacturing method thereof, and belongs to the technical field of sensors. The thin film sensor of the present disclosure has a plurality of conductive-wire regions intersecting each other, and a plurality of hollow-out parts defined by the plurality of conductive-wire regions; the thin film sensor includes: a base substrate; a plurality of conductive wires on the base substrate, with the conductive wires being in the conductive-wire regions one to one; and a functional structure on the base substrate, where the functional structure is configured to allow at least part of light, which is transmitted along a preset direction and enters the functional structure from the conductive wire-regions, to exit from the hollow-out parts, and the preset direction is a direction from the base substrate towards the conductive wires.

Abstract: This disclosure provides an electromagnetic field detector, and a method of operating the electromagnetic field detector in a wireless telecommunications network, the electromagnetic field detector including a first optical transmitter, a second optical transmitter, and a transmission medium, wherein the first optical transmitter is configured to transmit a probe signal at a probe frequency and the second optical transmitter is configured to transmit a coupling signal at a coupling frequency, wherein the probe frequency is set to excite electrons of the transmission medium from a ground state to a first excited state and the coupling frequency is set to excite electrons of the transmission medium to a predetermined excited state so as to induce an Electromagnetic Induced Transparency (EIT) effect such that an incident electromagnetic field at the transmission medium causes a detectable change in the probe signal.

Abstract: Disclosed herein is an untact DC electric-field sensor having improved sensitivity. The untact DC electric-field sensor has a circuit composed of a variable capacitor and an RF generator and improves sensitivity through resonance of the circuit by connecting an inductor to the sensor.

Abstract: A data analysis system comprises an artificial intelligence of the machine learning type. The data analysis system collects reference data relating to measurements made and recorded during previous flights of aircraft. A training of the artificial intelligence of the machine learning type is implemented by virtue of reference data, with a first classification run for training to detect potential malfunctions suffered by integrated drive generators and a second classification run for training to determine causes of the malfunctions, where relevant. After using in production, the data analysis system collects data to be analyzed relating to measurements made and recorded during flights of the aircraft comprising an integrated drive generator to be monitored, and uses the artificial intelligence of the machine learning type to predict a potential malfunction and, where relevant, predict its cause using data to be analyzed.

Abstract: The present invention relates to corona charge deposition systems that use High Voltage (HV) amplifiers for precisely controlling corona charge deposition. Some implementations, provide a corona charge deposition system that uses multiple voltage sources to maintain specified voltages applied on several electrodes to precisely control the corona current required to deposit a desired amount of charge on a sample. The HV amplifiers are able to source and sink currents to maintain stable voltages applied on control electrodes in the presence of a higher voltage applied on a needle electrode. The proposed apparatus and method of monitoring multiple signals, controlling multiple voltages, and predicting charge profile deposited on a sample can precisely control charge deposition processes.

Abstract: A disconnection detector circuit that can favorably inspect a connection state of a wire without increase in parasitic capacitance is provided. A semiconductor device includes, in one package, a first integrated circuit including a transformer including a primary coil and a secondary coil, and a second integrated circuit connected to a midpoint and one end of the secondary coil. The second integrated circuit includes a reference line and a detector circuit. The reference line connects the midpoint of the secondary coil and a reference potential. On basis of a potential at a predetermined reference point of the first power supply line, the detector circuit detects whether a connection state between the second integrated circuit and the secondary coil is normal or abnormal.

Abstract: An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.

Abstract: A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit or a burn-in heat distribution across the integrated circuit that includes a set of circuit blocks or a first set of heaters. The integrated circuit design corresponding to the integrated circuit. The performing the simulation includes determining a heat signature of the integrated circuit design from configured power information or location information for each circuit block of the set of circuit blocks or each heater of the set of heaters included in the integrated circuit design. The heat signature includes heat values distributed throughout the integrated circuit design.

Abstract: A circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. The circuit test structure further includes a test structure connected to the conductive line. The circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.

Abstract: A test board for semiconductor devices is provided which contains a plurality of semiconductor devices and is loaded into a testing apparatus. The test board includes: a receiving part formed with a plurality of semiconductor device receiving grooves that respectively receive a plurality of semiconductor devices; and a lid part removably attached to the receiving part, wherein the lid part includes a heat transfer portion having a first heat transfer end portion, which is exposed on the outside of the lid part while the lid part is attached to the receiving part, and a second heat transfer end portion, which extends from the first heat transfer end portion and is exposed to a temperature regulating region defined to include at least one of the plurality of semiconductor device receiving grooves.

Abstract: Resetting an integrated circuit (IC) by reset circuit of the IC comprises receiving a clock signal and a data signal. A sequence of bits of the data signal is stored in a memory based on the clock signal. A test mode signal is received and the sequence of bits is decoded in response to receiving the test mode signal. One of adjusting a counter value of a counter of the reset circuitry and outputting a reset signal corresponding to the counter value is performed based on the decoded sequence of bits.

Abstract: A fine electrical probe can provide fine-pitch applications in devices such as smart watches and smart phones. Fingers are positioned on a substrate. The substrate has a recess that allows the fingers to flex. The substrate and fingers are positioned in an assembly. The assembly has a recess that allows the substrate to flex.

Abstract: A memory having a first authentication code includes a communication port configured to transmit information including debug data to or receive the information including debug data from the external device; and a debug port controller that is usable for blocking of a communication path connecting to the communication port. The debug port controller is configured to receive an authentication request including a second authentication code from an external device, determine whether the second authentication code matches the first authentication code, and block the communication path if the second authentication code is not determined to match the first authentication code. The communication port may be configured to be disabled until the second authentication code matches the first authentication code.

Abstract: A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation.

Abstract: A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.

Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

Abstract: A method or system for estimating delays in design under tests (DUTs) using machine learning. The system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays, along with the corresponding feature vectors, are used to train a machine learning delay model. The trained model is designed to receive a combinatorial path of a DUT as input and generate an estimated wire delay as output. This approach leverages machine learning to predict delays in electronic designs, improving the efficiency and accuracy of delay estimations in complex circuits.

Abstract: A circuit for improving control over asynchronous signal crossings during circuit scan tests includes multiple scan registers and a decoder configured to translate a combined output of the scan registers into multiple one-hot controls to the local clock gates of scan registers disposed in multiple different clock domains. Programmable registers are provided to selectively enable and disable the local clock gates of the different clock domains.

Abstract: A system of performing boundary scan test on pin through test point and a method thereof are disclosed. When an under-test pin of a target connector is determined to be unable to perform a boundary scan test, a test point connected to and closest to the under-test pin is searched, a test signal is transmitted to a target connector, a result signal from the target connector in response to the test signal is received, an expected result and the result signal are compared to generate a test result, so that a boundary scan function can be applied to test a connector of a computer product, to achieve the technical effect of providing a better test range and a better test coverage to improve test efficiency and reduce test cost, compared to conventional boundary scan test.

Abstract: Embodiments of the present invention can selectively enable 16 lane (×16) or 8 lane (×8) device testing using multiplexor circuitry disposed between a CXL1.1 CPU and the DUTs during testing. In this way, parallelism and testing efficiency are significantly improved compared to existing approaches that can only test devices using 8 lanes of the CXL 1.1 CPU.

Abstract: A failure insertion unit for connection to an object under test connected to a bus or network interface, wherein the object under test can be subjected by means of the failure insertion unit to fault voltages that are greater than the maximum voltage for which the bus or network interface is designed, with a fuse circuit which protects a bus or network interface connected to the failure insertion unit from voltages that are greater than the maximum voltage for which the bus or network interface is designed. This provides a way to be able to use failure insertion units even in systems that work with buses with high bandwidths without the risk of damaging bus or network interfaces due to overvoltages.

Abstract: A method of testing a motor of a robot arm for a fault during a start-up procedure of the robot arm. The robot arm comprises a first link connected to a second link by a joint, the joint permitting the second link to move relative to the first link. The motor is for driving the joint and is a multiple-phase motor, each phase of the motor comprising a motor winding and a motor drive circuit for applying power to the motor winding from a power supply rail and for applying drive signals to the motor winding.

Abstract: A method of providing financial service based on BEV (battery electric vehicle) and a financial service system for performing the method can include generating, by a battery electric vehicle financial product generation device, a battery electric vehicle-based financial product and adjusting, by a residual value-based risk management device, a risk of the financial product based on battery value evaluation data.

Abstract: A state of battery testing system is disclosed which includes a charger, a load to be coupled across the battery's positive and negative terminals, a processer adapted to apply a predetermined voltage pulse across the battery's positive and negative terminals, apply the load to the battery, measure and log current through the load as Iexp, and establish a model based on establishing an initial estimation of state of the battery (?0), and establishing a modeled state of battery (?i) based on a plurality of internal parameters of the battery. The model is adapted to output a model current through the load, inputting ?0 and the plurality of internal parameters of the model to thereby generate Imodel, generate an objective function (f) based on a comparison of Imodel and Iexp, and iteratively optimize ?i, and output ?optimal based on the iterations.

Abstract: A method of managing a battery record and an apparatus for performing the method can include generating, by a battery record management device, a battery non-fungible token (NFT) based on a blockchain. The method can also include generating, by the battery record management device, battery value evaluation data corresponding to the battery NFT and recording the generate battery value evaluation data on the blockchain.

Abstract: A battery simulator includes a circuit simulator that simulates an operation of an RC parallel circuit which is an equivalent circuit of a battery to be monitored and an RC parallel circuit optimization device that optimizes the RC parallel circuit based on a monitoring frequency of the battery, wherein the RC parallel circuit optimization device is configured to: delete a capacitance value of the RC parallel circuit when the monitoring frequency is determined to be a low frequency, and delete resistance and capacitance values of the RC parallel circuit when the monitoring frequency is determined to be a high frequency.

Abstract: Methods, systems, and media for mitigating defects in battery packs are provided. In some embodiments, a method comprises: (a) monitoring one or more battery parameters associated with one or more battery elements of a battery pack comprising a plurality of battery elements; (b) determining individual status information, each corresponding to one of the one or more battery elements of the battery pack based on the one or more battery parameters; and (c) modifying a use pattern of the battery pack based at least in part by considering an aggregate of the individual status information.

Abstract: According to an example embodiment, a method is provided, the method comprising: determining a respective impedance curve for a plurality of cells extracted from a plurality of rechargeable batteries, wherein each impedance curve is descriptive of an internal impedance of the respective cell as a function of frequency over a predefined frequency range; determining, for each of the plurality of cells, respective one or more impedance characteristics based on the impedance curve determined for the respective cell; and sorting the plurality of cells into one or more quality classes in accordance with the one or more impedance characteristics determined for the plurality of cells.

Abstract: Methods, systems, and apparatuses for mitigating battery defects are provided. In some embodiments, a method comprises: monitoring one or more battery parameters associated with a rechargeable battery; obtaining a rate of change of at least one battery parameter of the one or more battery parameters; and determining a defect status of the rechargeable battery based at least in part on the rate of change of the at least one battery parameter.

Abstract: A battery state estimation device includes: a first state of charge (SOC) calculator that calculates a first SOC using a first method that uses the battery model parameter of a battery; a second SOC calculator that calculates a second SOC using a second method different from the first method; an alternating-current (AC) impedance measurement unit that measures the AC impedance of the battery when the error between the first SOC and the second SOC is greater than a predetermined threshold; and a battery model parameter calculator that calculates a battery model parameter using the measured AC impedance. The first SOC calculator recalculates the first SOC using the battery model parameter calculated.

Abstract: Systems, methods, and devices are provided for determining an early battery depletion (EBD) condition of an implantable medical device that includes a memory storing program instructions and a processor executing the program instructions. Circuitry is electrically coupled to the processor, and the circuitry and processor perform one or more tasks related to at least one of collecting signals indictive of physiologic activity, analyzing collected signals, delivering therapy, or communicating with an external device. A battery supplies energy to the circuitry and processor. A monitoring circuit coupled to the battery measures actual energy usage from the battery representing at least one of a current draw from the battery during corresponding tasks or a voltage measurement across the battery. Circuitry and processor calculate projected energy usage from the battery in connection with the corresponding tasks, and determine when an EBD condition exists based on projected energy usage and actual energy usage.

Abstract: Example devices and techniques are described herein for determining a relative state-of-charge of a battery. An example device includes memory, a battery, a temperature sensor and processing circuitry coupled to the memory and the temperature sensor. The temperature sensor may be configured to sense a battery temperature. The processing circuitry may be configured to estimate an end-of-discharge state-of-charge of the battery. The processing circuitry may be configured to estimate a remaining capacity of the battery. The processing circuitry may be configured to estimate a full charge capacity of the battery. The processing circuitry may be configured to estimate a relative state-of-charge of the battery and generate a representation of the estimate of the relative state-of-charge of the battery for output.

Abstract: A method for estimating battery cell capacity may comprise deriving a discharge curve for each battery cell included in a module including a plurality of battery cells; deriving a charge curve for each battery cell included in the module; calculating an additional dischargeable capacity of a second battery cell based on a pattern of the discharge curve of a first battery cell; calculating an additional chargeable capacity of the second battery cell based on the transition of the charge curve of the first battery cell; and calculating a capacity of the second battery cell based on the additional dischargeable capacity and the additional chargeable capacity of the second battery cell.

Abstract: A method includes applying a preliminary discharge/charge cycle to a plurality of battery cells to obtain an initial capacity of each battery cell, applying multiple small current discharge/charge cycles to the plurality of battery cells to minimize initial voltage deviations of the plurality of battery cells, configuring a first battery cell to be tested at a plurality of first testing points, configuring a second battery cell to be tested at a plurality of second testing points, and configuring a third battery cell to be tested at a plurality of third testing points, wherein the first battery cell, the second battery cell and the third battery cell are tested concurrently for generating an OCV-SOC curve, and the plurality of first testing points, the plurality of second testing points and the plurality of third testing points are arranged in an alternate manner.