Abstract: The present disclosure relates to the technical field of semiconductors, and provides a method and an apparatus for determining an address mapping relationship, and a storage medium. The method for determining an address mapping relationship includes: obtaining a mapping relationship table between preset addresses and DRAM physical addresses under a preset condition; and analyzing values of bit addresses in the DRAM physical address according to a first preset rule, to determine an attribute of each bit address in the DRAM physical address, where the attribute is used for representing an address field of the DRAM physical address.

Abstract: An air freight rate data caching method and system. The method includes converting air freight rate data into a data format of a first-level cache, and storing same in the first-level cache; performing, on the basis of a flight origin city and a flight destination city, data fragmentation on the air freight rate data stored in the first-level cache so as to generate fragmented data; and storing the fragmented data, after same is validated, in a second-level cache. Each data node of the fragmented data cached in the second-level cache only includes part of the air freight rate data on which a fragmentation algorithm can be performed, and therefore, the horizontal expansion capacity of a cache system is improved relative to the case where cached data copies are all complete sets.

Abstract: A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

Abstract: A computing system that enables data stored in a persistent memory region to be preserved when a processor fails can include volatile memory comprising the persistent memory region, non-volatile memory, and a system on a chip (SoC). The SoC can include a main processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include an auxiliary processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include instructions that are executable by the auxiliary processor to cause the data in the persistent memory region of the volatile memory to be transferred to the non-volatile memory in response to a failure of the main processor.

Abstract: Methods, systems, and devices for techniques for enhanced system performance after retention loss are described. A memory system may program a page of memory cells in response to receiving a power down notification. As part of the programming, the memory system may record an indication of a voltage threshold of the page and power down for a duration of time, during which the memory system may experience retention loss. Upon powering on, the memory device may compare the voltage threshold of the page to the indication stored prior to powering down and determine a voltage offset for one or more blocks of the memory system. In some cases, the memory system may use the voltage offset to determine a starting bin, and may initiate a bin scan to determine a final bin for the one or more blocks.

Abstract: A memory device is described, including a command decoder configured to receive a copy command to copy data stored in a first memory location to a second memory location without transmitting the data to an external controller, a memory array electrically connected to the command decoder and including a plurality of memory locations including the first memory location and the second memory location, a data line electrically connected to the memory array and configured to receive, from the first memory location, the data to be transmitted to the second memory location through the same data line, and an output buffer configured to store the data received from the first memory location through the data line to be written into the second memory location without transmitting the data to the external controller.

Abstract: A database system is operable to determine a query for execution that requires access to a set of records stored by the database system. A first proper subset of the set of records are accessed in conjunction with executing the query by reading exactly one of a set of multiple replicas of each record of the first proper subset of the set of records from the replication-based storage system. A second proper subset of the set of records are accessed in conjunction with executing the query by reading at least one redundancy-coded segment from the redundancy-coding based storage system. A final resultant for the query is generated by performing at least one query operation on the first proper subset of the set of records and the second proper subset of the set of records in conjunction with executing the query.

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

Abstract: The disclosure relates to technology for pre-fetching data. An apparatus comprises a processor core, pre-fetch logic, and a memory hierarchy. The pre-fetch logic is configured to generate cache pre-fetch requests for a program instruction identified by a program counter. The pre-fetch logic is configured to track one or more statistics with respect to the cache pre-fetch requests. The pre-fetch logic is configured to link the one or more statistics with the program counter. The pre-fetch logic is configured to determine a degree of the cache pre-fetch requests for the program instruction based on the one or more statistics. The memory hierarchy comprises main memory and a hierarchy of caches. The memory hierarchy further comprises a memory controller configured to pre-fetch memory blocks identified in the cache pre-fetch requests from a current level in the memory hierarchy into a higher level of the memory hierarchy.

Abstract: The embodiments herein describe a multi-tenant cache that implements fine-grained allocation of the entries within the cache. Each entry in the cache can be allocated to a particular tenant—i.e., fine-grained allocation—rather than having to assign all the entries in a way to a particular tenant. If the tenant does not currently need those entries (which can be tracked using counters), the entries can be invalidated (i.e., deallocated) and assigned to another tenant. Thus, fine-grained allocation provides a flexible allocation of entries in a hardware cache that permits an administrator to reserve any number of entries for a particular tenant, but also permit other tenants to use this bandwidth when the reserved entries are not currently needed by the tenant.

Abstract: The present disclosure provides a method and apparatus for parsing contiguous system addresses, and an electronic device. The method for parsing contiguous system addresses comprises: acquiring system level information upon receiving contiguous system addresses; acquiring logical address ranges of objects in a first level based on the contiguous system addresses and the system level information; and when successively acquiring logical address ranges of objects in a second level, . . . , or an Nth level of the system, acquiring logical address ranges of objects in a present level based on a logical address range of a previous level and the system level information, wherein N is the number of levels, and N is an integer greater than or equal to 2, and a logical address range of an object comprises a start address and an end address of the object.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: allocate a named portion of the non-volatile storage device; generate, according to a first block size, first block-wise mapping data; translate, using the first block-wise mapping data, logical addresses defined in the named portion to logical addresses defined for the entire non-volatile storage media, which can then be further translated to physical addresses in a same way for all named portions; determine a second block size; generate, according to the second block size, second block-wise mapping data; translate, using the second block-wise mapping data, the logical addresses defined in the named portion to the logical addresses defined for the entire non-volatile storage media.

Abstract: Compressing memory addresses within an execution trace via reference to a translation lookaside buffer (TLB) entry. A microprocessor identifies a TLB entry within a TLB slot, the TLB entry mapping a virtual memory page to a physical memory page. The microprocessor initiates logging of the TLB entry by initiating logging of at least a virtual address of the virtual memory page, and an identifier that uniquely identifies the TLB entry from among a plurality of live TLB entries. Subsequently, the microprocessor identifies a cache entry within a memory cache slot, the cache entry comprising a physical memory address corresponding to a cache line. The microprocessor initiates logging of the cache entry by matching a physical memory page identification portion of the physical memory address with the TLB entry, and then initiates logging of at least the identifier for the TLB entry and an offset portion.

Abstract: Provided is a cache memory device including a command reception unit for packetizing each of read commands and write commands and classifying them as even or odd; a cache scheduler comprising a first reorder scheduling queue for receiving commands classified as even numbers from the command reception unit and scheduling the commands classified as even numbers for cache memory accesses and a second reorder scheduling queue for receiving commands classified as odd numbers from the command reception unit and scheduling the commands classified as odd numbers for cache memory accesses; and an access execution unit for performing cache memory accesses via a cache tag to scheduled commands classified as even numbers and scheduled commands classified as odd numbers.

Abstract: A system includes a multi-port RAM configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine (engine) that processes the data stream using the instruction table. The engine includes a decoder circuit that determines validity of active states output from the multi-port RAM and a plurality of priority FIFO memories (PFIFOs) operating concurrently. Each PFIFO can initiate a read from a different port of the multi-port RAM. Each PFIFO can track a plurality of active paths for the regular expression and a priority of each active path by, at least in part, storing entries corresponding to active states in each respective PFIFO in decreasing priority order. The engine includes switching circuitry that selectively routes the active states from the decoder circuit to the plurality of PFIFOs according to the priority order.

Abstract: Embodiments of systems and methods for selecting and configuring grouped peripherals in shared workspaces are described. In an illustrative, non-limiting embodiment, an IHS may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution by the processor, cause the IHS to: group a plurality of devices available during a shared workspace session into a plurality of groups; transmit, to a remote service: (a) an indication of a performance metric, and (b) an indication of the plurality of groups; and receive, from the remote service, a selection of one device in each of the plurality of groups for use during the shared workspace session based, at least in part, upon the performance metric.

Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.

Abstract: Described are techniques including a computer-implemented method that comprises defining a respective priority classification for each of a plurality of sockets used for communicating between an initiator computational system and a target computational system. The method further comprises automatically assigning a respective priority classification to each of a plurality of Input/Output (IO) requests based on a type of data associated with each IO request. The method further comprises sending the plurality of IO requests to respective sockets of the plurality of sockets with a matching priority classification.

Abstract: An electronic component is formed by a semiconductor component or a semiconductor-like structure having gate electrode assemblies, for reading out the quantum state of a qubit in a quantum dot. The electronic component comprises a substrate having a two-dimensional electron gas or electron hole gas. Electrical contacts connect the gate electrode assemblies to voltage sources. The gate electrode assemblies have gate electrodes, which are arranged on a surface of the electronic component, for producing potential wells in the substrate.

Abstract: The present technology relates to an information processing system, information processing method, and information processing device capable of reducing load on an information processing unit in a case where data is shared among a plurality of information processing devices.

Abstract: Techniques to reduce overhead in a direct memory access (DMA) engine can include processing descriptors from a descriptor queue to obtain a striding configuration to generate tensorized memory descriptors. The striding configuration can include, for each striding dimension, a stride and a repetition number indicating a number of times to repeat striding in the corresponding striding dimension. One or more sets of tensorized memory descriptors can be generated based on the striding configuration. Data transfers are then performed based on the generated tensorized memory descriptors.

Abstract: A Baseboard Management Controller (BMC) that may configure itself is disclosed. The BMC may include an access logic to determine a configuration of a chassis that includes the BMC. The BMC may also include a built-in self-configuration logic to configure the BMC responsive to the configuration of the chassis. The BMC may self-configure without using any BIOS, device drivers, or operating systems.

Abstract: A USB hub, including multiple USB upstream ports, multiple downstream ports, multiple image processing units, a USB hub unit, a first multiplexer, and a second multiplexer, is provided. The USB upstream ports include a first USB upstream port and a second USB upstream port. The downstream ports include a first downstream port and a second downstream port. The image processing units include a first image processing unit and a second image processing unit. The first multiplexer is coupled to the first USB upstream port, the second USB upstream port, the first image processing unit, the second image processing unit, and the USB hub unit. The second multiplexer is coupled to the first image processing unit, the second image processing unit, the USB hub unit, the first downstream port, and the second downstream port.

Abstract: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.

Abstract: A Universal Serial Bus (USB) connector functionality modification system includes a USB connector coupled to a first subsystem and a second subsystem by a multiplexer device. A USB connector functionality modification subsystem is coupled to the multiplexer device and operates to receive a USB connector functionality modification instruction while the multiplexer device is configured to allow the first subsystem to transmit and receive data via the USB connector and the second subsystem cannot transmit and receive data via the USB connector. In response to receiving the USB connector functionality modification instruction, the USB connector functionality modification subsystem reconfigures the multiplexer device to allow the second subsystem to transmit and receive data via the USB connector while the first subsystem cannot transmit and receive data via the USB connector.

Abstract: An integrated circuit device includes multiple heterogeneous functional circuit blocks and interface circuitry that permits the heterogeneous functional circuit blocks to exchange data with one another using communication protocols of the respective heterogeneous functional circuit blocks. The IC device includes fixed-function circuitry, user-configurable circuitry (e.g., programmable logic), and/or embedded processors/cores. A functional circuit block may be configured in fixed-function circuitry or in the user-configurable circuitry (i.e., as a plug-in). The interface circuitry includes a network-on-a-chip (NoC), an adaptor configured in the user-configurable circuitry, and/or memory. The memory may be accessible to the functional circuit blocks through an adaptor configured the user-configurable circuitry and/or through the NoC. The IC device may be configured as a SmartNIC, DPU, or other type of system-on-a-chip (SoC).

Abstract: Disclosed is an electronic device including a first interface configured to receive information about a device information storage device configured to store information about another electronic device, a second interface configured to communicate with a processor of the other electronic device, and at least one processor, wherein the at least one processor is configured to, when the device information storage device is identified through the first interface, acquire the information about the other electronic device from the device information storage device through the first interface, when the device information storage device is not identified through the first interface, check whether the other electronic device is identified through the second interface, and when the other electronic device is identified through the second interface, acquire the information about the other electronic device through the second interface based on communication with the processor of the other electronic device.

Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.

Abstract: A Peripheral Component Interconnect Express (PCIe) device performing communication with a host through a PCIe link includes a first physical function, a plurality of second physical functions, and a function mode controller. The first physical function manages the PCIe link and receives function mode control information from the host. Each of the plurality of second physical functions may be enabled or disabled according to a respective operation mode. Based on the function mode control information, the function mode controller sets the operation modes of the plurality of second physical functions to one of an active mode and an inactive mode.

Abstract: An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.

Abstract: A device that may configure itself is disclosed. The device may include an interface that may be used for communications with a chassis. The interface may support a plurality of transport protocols. The device may include a Vital Product Data (VPD) reading logic to read a VPD from the chassis and a built-in self-configuration logic to configure the interface to use one of the transport protocols and to disable alternative transport protocols, responsive to the VPD.

Abstract: A multi-chip module (MCM includes a substrate and first and second integrated circuit chips disposed on the substrate. The second IC chip includes transceiver circuitry configured to communicate with the first IC chip. The transceiver circuitry includes transmit circuitry having an inverter circuit to generate a first signal for transmission to the first IC chip along a signaling link. The signaling link includes a line termination impedance. Receiver circuitry includes a receiver circuit to receive a second signal from the first IC chip along the signaling link concurrently with transmission of the first signal along the signaling link. Hybrid circuitry is coupled to the transmit circuitry and to the receiver circuitry. The hybrid circuitry is configured to cancel a received component of the first signal. The hybrid circuitry includes a replica termination impedance that is configured in an open state.

Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. A configuration unload controller connected to the bus system, including logic to execute an array configuration unload process, including distributing a command to a plurality of the configurable units in the array to unload the unit files particular to the corresponding configurable units, the unit files each comprising a plurality of ordered sub-files, receiving sub-files via the bus system from the array of configurable units, and assembling an unload configuration file by arranging the received sub-files in memory according to the configurable unit of the unit file of which the sub-file is a part, and the order of the sub-file in the unit file.

Abstract: A system for executing an application on a pool of reconfigurable processors with first and second reconfigurable processors having first and second architectures that are different from each other is presented. The system comprises an archive of configuration files with first and second configuration files for executing the application on the first and second reconfigurable processors, respectively, and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises a runtime processor that allocates reconfigurable processors for executing the application and an auto-discovery module that is configured to perform discovery of whether the reconfigurable processors include at least one of the first reconfigurable processors and whether the reconfigurable processors include at least one of the second reconfigurable processors.

Abstract: Embodiments of the present disclosure provide a method, device and computer program product for managing backup data. The method comprising: obtaining historical information of a plurality of historical operations on target data in a backup storage device during a first time period, the historical information indicating at least types and time of occurrences of the plurality of historical operations; determining, based on the historical information, whether the target data is to be rewritten to the backup storage device within a second time period after the first time period; and in response to determining that the target data is to be written to the backup storage device within the second time period, adjusting an expiration time of the target data in the backup storage device. Based on such a manner, efficiency of the backup system can be increased.

Abstract: A method includes receiving a plurality of files where each file represents an object. The method further combines selected files of the plurality of files into an aggregation file and stores the aggregation file on low-latency storage media, such as disk storage media. The method represents the aggregation file with a single inode that is stored on the low-latency storage media. The method migrates the aggregate file to high-latency storage media, such as tape storage media, while leaving the single inode representing the aggregation file on the low-latency storage media. By collecting files into larger aggregation files, the number of files archived is significantly reduced and the files archived are of larger size. The reduced number of files and increased size of the files improves archival and retrieval performance due to reduced metadata operation overhead. A corresponding system and computer program product are also disclosed.

Abstract: Dynamic snapshot scheduling techniques are provided using storage system metrics. One method comprises obtaining a schedule for generating snapshots of a portion of a storage system; automatically adjusting snapshot generation parameters in the schedule based on: (i) a current storage pool usage metric, (ii) an input/output metric of at least one storage resource in the portion of the storage system, (iii) a measure of snapshots in a destroying state, and/or (iv) a measure of a number of created snapshots; and initiating a generation of a snapshot of the storage system portion in accordance with the adjusted schedule. A snapshot generation frequency may be increased in response to an increase of: the current storage pool usage metric, the number of snapshots in the destroying state, and/or the number of created snapshots. A snapshot generation frequency may be decreased in response to an increase of the I/O metric of the at least one storage resource.

Abstract: Systems and computer-implemented methods and systems for modifying information in a document file are disclosed. An example computer-implemented method for modifying information in a document file includes: receiving a first text string; opening a file corresponding to the first text string, the file including binary data and text data; reading the text data; detecting a file location identifier in the text data; replacing a portion of the file location identifier with a second text string based on the first text string; and closing the file.

Abstract: A copy-on-write union filesystem. A computer system identifies a first filesystem namespace as a mutable layer, and a second filesystem namespace as an immutable layer. The computer system exposes a merged filesystem namespace as a union filesystem that merges the mutable layer and the immutable layer, and that overlays the first filesystem namespace over the second filesystem namespace. The computer system identifies an operation on the merged filesystem namespace that requests to read from a file within the merged filesystem namespace, the file being stored in the second filesystem namespace and not being stored in the first filesystem namespace. The computer system returns a handle referencing a proxy object stored in a system memory. The proxy object includes a mapping to a file object corresponding to the file as stored in the second filesystem namespace.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving, at a clustered filesystem from a formatted filesystem, a request to perform a data integrity check for a portion of data. A determination is made as to whether the request includes a filesystem type of the portion of data, and in response to determining that the request includes a filesystem type of the portion of data, another determination is made as to whether the clustered filesystem supports the data integrity check for the filesystem type. In response to determining the clustered filesystem supports the data integrity check, another determination is made as to whether the portion of data is currently available. Furthermore, the computer-implemented method includes causing the data integrity check to be performed in response to determining that the portion of data is currently available. Results of performing the data integrity check are also sent to the formatted filesystem.

Abstract: A method includes retrieving, with a masker controller job, an object and an associated object ID from a masking bucket that is defined in storage, making a copy of the object, with a masker worker microservice, masking the copy of the object to create a masked object, transmitting the masked object to an object access microservice, with the object access microservice, transmitting the masked object to a deduplication microservice, with the deduplication microservice, deduplicating the masked object, and storing the masked object in the storage.

Abstract: A scenario execution system includes a scenario execution terminal, a log management device, and a storage device. The scenario execution terminal includes a scenario execution unit and an event notification unit. The scenario execution unit executes a scenario file having a scenario indicating a procedure of operations in the scenario execution terminal described therein. The event notification unit notifies the log management device of information on an event generated by the scenario execution unit executing the scenario file. The log management device includes a log recording unit that receives the information on the event from the scenario execution terminal and records log data having the received information on the event set therein on the storage device. The storage device adds, to the log data, information uniquely generated on the basis of log data recorded before such log data and stores resultant log data.

Abstract: Provided herein are systems and methods for replicating share objects to remote deployments. An example method includes generating, at a second deployment in a data exchange, a replica of a share object included in a first deployment of the data exchange. The share object grants privileges to a first account to access a first database of the first deployment, wherein the first database comprises a database object. The method also includes retrieving, at the first deployment, share grant metadata from the share object of the first deployment, wherein the share grant metadata includes a reference to the database object and allows the first account to use the database object. The method also includes transmitting a message comprising the share grant metadata to the replica in the second deployment. The share grant metadata in the replica allows a second account to use the database object replicated in the second deployment.

Abstract: Herein are resource-constrained techniques that plan ahead for resiliently moving pluggable databases between container databases after a failure in a high-availability database cluster. In an embodiment, a computer identifies many alternative placements that respectively assign each pluggable database to a respective container database. For each alternative placement, a respective resilience score is calculated for each pluggable database that is based on the container database of the pluggable database. Based on the resilience scores of the pluggable databases for the alternative placements, a particular placement is selected as an optimal placement that would maximize utilization of computer resources, minimize database latencies, maximize system throughput, and maximize the ability of the database cluster to avoid a service outage.

Abstract: Systems, methods, and computer program products described herein for building a prediction model with varying availability. Embodiments described herein build a prediction model that is initially trained with a selected subset of data characteristics (e.g., data characteristics that are commonly available in training data), and then augmented via Bayesian estimation with additional data characteristics when such data characteristics are available.

Abstract: Some implementations of the disclosed systems, apparatus, methods and computer program products may provide for determination of resource usage by tenants in a multi-tenant server system. Tenants may provide resource requests to a database of the multi-tenant server system and such resource requests may include context data. Periodic snapshots of the database may be performed to determine the pending resource requests received by the various tenants and, based on the snapshots and the context data, the resource usage of the various tenants, as well as the system as a whole, may be determined and forecasted for the future.

Abstract: A recipe management system includes a versioning system that tracks the revision history of templates and their child instances. Modifications to templates and instances create new records with new primary key identifiers and version identifiers. However, each new version of a template or instance has the same root identifier as the prior versions. When a template is modified, a flag is set in its child instances, but they are not modified automatically. When an instance is modified, it has no effect on the parent template. At runtime, a recipe model is loaded to an equipment model to execute a recipe on a piece of equipment. Only approved versions of equipment models are used during execution, even if newer versions exist. During execution, new equipment models can be created. The recipe management system includes an execution engine that can be hosted as a standalone executable or in a system platform.

Abstract: A method includes: obtaining, by a computing device, a first work item from a first index, wherein the first work item represents a namespace of a bucket of a vault in a dispersed storage network; dividing, by the computing device, the namespace into plural ranges of names; creating, by the computing device, plural second work items, each respective one of the plural second work items including a respective one of the plural ranges of names; and adding, by the computing device, each of the plural second work items to a second index.

Abstract: A system and method to index one or more sensor-based datasets utilizing pattern recognition and prediction to identify instances and regions of novelty and change as a means of highlighting potential subjective interest for the purposes of optimizing the manual and automated search, visualization, and extraction of datasets.

Abstract: Systems, apparatus, and methods of managing the lifecycle of a digital token are described. In an example, while the digital token is being generated, the digital token or the underlying digital asset can be compared to other digital tokens and/or digital assets to determine similarity thereto. Based on the similarity, a program code interface (e.g., smart contract, an application programming interface—API, RPC, etc.) can be determined and an API call can be made to execute a program code. The execution can indicate whether the digital token creation process can be completed. If so, the digital token is recorded. Thereafter, its use or the use of the underlying digital asset can be monitored, whereby this monitoring can apply similarity processing. If a use thereof is determined or if a use of a similar digital token or similar digital asset is determined, notifications can be generated and sent.