Abstract: A system (10) for expression, purification, and detection and screening of biological drugs comprises: one or more incubators (1), which are used for culturing biological samples to provide basic samples for detection and screening of biological drugs; a liquid operation system (3), which is used for implementing predetermined operations on the biological samples cultured in the incubator(s) (1); a sample detection platform (5), which is used for detecting the biological samples so as to facilitate screening; a transfer platform, which is used for transferring the biological samples between the incubator(s) (1) and the liquid operation system (3) and/or between the liquid operation system (3) and the sample detection platform (5); and an automatic control system (6), which is configured to control the operation of at least one of the incubator(s) (1), the liquid operation system (3), the sample detection platform (5) and the transfer platform.

Abstract: A method includes irradiating a target droplet in an extreme ultraviolet (EUV) light source of an extreme ultraviolet lithography tool with non-ionizing light from a droplet illumination module. The method further includes detecting light reflected and/or scattered by the target droplet, and performing particle image velocimetry, based on the detected light, to determine a velocity of the target droplet. The method also includes adjusting a time delay between a generation of the target droplet and a generation of an excitation laser beam based on the velocity of the target droplet.

Abstract: Distance-sensing techniques (between probes and a sample) utilize at least one of squeeze-film damping and temperature sensing for scanning probe microscopy. Squeeze-film damping may be used for “approach;” that is, z-position detection. It may also be used for “imaging;” that is, to obtain a topographic map of the surface of a sample.

Abstract: A test socket for testing the electrical characteristics of a semiconductor device provides a test socket, including a housing in which a plurality of first through holes are formed; a cover in which a plurality of second through holes are formed; and a plurality of contact pins inserted into the plurality of first and second through holes, wherein the plurality of contact pins include an elastic part capable of elastic deformation in the longitudinal direction; a first contact part comprising: a first support part extending from one end of the elastic part, a stroke part connected to an end of the first support part and movable in the longitudinal direction, and a first contact tip connected to an end of the stroke part and exposed in the first through hole.

Abstract: A circuit structure, an electronic device, and a manufacturing method of the electronic device are provided. The circuit structure includes a support layer, a base layer, and a circuit layer. The base layer is disposed on the support layer. The circuit layer is disposed on the base layer and includes a first conductive layer, a first insulating layer, and a second conductive layer. The first conductive layer is disposed on the base layer. The first insulating layer is disposed on the first conductive layer. The second conductive layer is disposed on the first insulating layer. The elongation of the support layer is smaller than the elongation of the base layer.

Abstract: A method for detecting a contact force of a probe card is provided. The method includes contacting a pressure film sensor with a plurality of needles over a lower surface of the probe card. The method includes detecting the contact force of the probe card via the pressure film sensor. The method also includes adjusting a position of a push base over an upper surface of the probe card based on the detected contact force of the pressure film sensor.

Abstract: A membrane probe card includes probes each having a base electrically connected with a trace of a membrane wiring structure, and a probe tip protruding from the base. The base has a tip placement section and an extension section, which extend from a first side edge to a second side edge of the base in order. The probe tip is made by laser processing and electroplating, located at the tip placement section, and provided with a fixed end portion connected with the base in a way that the width of the tip placement section is greater than the width of the fixed end portion. A distance from a center of the probe tip to the first side edge is less than a distance from the center of the probe tip to the second side edge. As such, requirements of fine pitch and probe height may be achieved.

Abstract: A thin-film resistor circuit for an integrated circuit provides low resistance by segmenting a thin-film resistor to provide a wider effective thin-film resistor in a smaller die. The die includes a substrate, multiple electronic devices integrated on the substrate and interconnected to form at least a portion of an electronic circuit, a plurality of interconnect lands arranged in a grid that interconnect the devices with external terminals, and a thin-film resistor implemented by two or more thin-film resistor segments that operate in parallel in the circuit. The segments are disposed between different pairs of adjacent columns of the grid interconnect lands, with one of the thin-film resistor segments electrically connected along its width to lands of a first column of the grid of interconnect lands, and another one of the thin-film resistor segments is electrically connected along its width to lands of a second column of the grid interconnect lands.

Abstract: Embodiments of the present invention provide cooling for a test array (e.g., a semiconductor test array) using a 2-phase refrigerant. Testing can be performed without any added insulation, which improves test site density significantly. The refrigerant can be provided by any suitable refrigerant source, such as a pump or valve-controlled pressure chamber, for example, and can be provided to a cold plate of a test site, for example. The cold plate can include a flow field or flow channels for guiding the refrigerant to evenly cool surfaces and/or prevent condensation forming on outer surfaces of the cold plate or test site.

Abstract: A current sensor includes a busbar extending in a direction, a magnetic sensor facing the busbar in a direction intersecting the direction in which the busbar extends, a magnetic shield having a base that faces the busbar, at least a portion of the base facing a side of the busbar opposite to a side where the magnetic sensor is disposed, and a case having an insert-molded section in which at least a part of the magnetic shield is insert-molded. The insert-molded section has holes (first holes), and in the holes (first holes), some portions of the magnetic shield are exposed as exposure portions (first exposure portions) and the exposure portions (first exposure portions) have rust-prevention properties. Such a current sensor has the rustproofed exposure portions and thus problems caused by rusting in the exposure portions in the magnetic shield can be prevented or reduced.

Abstract: Proposed is a high current measuring device for measuring an entire current flowing through a metal bar (10), wherein the metal bar (10) is a rectangle, has a plate-shaped outline, and includes an even number of split slits (11a, 11b) disposed in a widthwise direction at a center of a longitudinal direction so that a branch set 11, which includes branches (in an odd number no smaller than 3) through which the entire current is divided and flows, is provided, a 1-1 notch (12a) and a 1-2 notch (12b) respectively provided by being concaved inward from two longer sides of the rectangle at the front ends of the split slits (11a, 11b), and a 2-1 notch (14a) and a 2-2 notch (14b) respectively provided by being concaved inward from two longer sides of the rectangle at the rear ends of the split slits (11a, 11b).

Abstract: A current sensing apparatus includes a planar current conductor with a current shaping section, designed to carry an alternating current (AC) current with a maximum frequency. The current shaping section of the conductor consists of a pair of adjacent legs separated by a slot, which shapes the AC current to flow around the slot in opposite directions. The legs of the current conductor have a width no greater than twice the skin depth of the AC current at a frequency of at least half of the maximum frequency. The apparatus also includes a differential current sensor that measures the directional components of the AC current on opposite sides of the slot. This configuration allows for accurate current sensing while minimizing the effect of the skin effect at high frequencies, making it suitable for use in various applications where a broad range of fundamental frequencies are expected.

Abstract: An optical voltage measurement system can include a pickoff rod, a sled, and optical componentry. The pickoff rod can be electrically connected to a power line and configured to emanate an electric field commensurate with the power line's energy. The sled can align and maintain the optical componentry in a fixed orientation to the pickoff rod. The optical componentry can include a dual RTP crystal assembly.

Abstract: A current sensor includes units each of which has a bus bar through which current flows, a magnetic sensor facing one of plate surfaces of the bus bar, a shield facing the other plate surface. The units have a large-current unit and a small-current unit. A first distance between the bus bar and the magnetic sensor in a normal direction of the plate surfaces of the bus bar is the same as a distance L1A of the large-current unit and a distance L1B of the small-current unit. Since, as for a second distance between the bus bar and a base of the shield, a distance L2A of the large-current unit is larger than a distance L2B of the small-current unit, a measurement range of the large-current unit is widened and a measurement error due to magnetic saturation of the shield is suppressed.

Abstract: A high voltage measurement port and a circuit contact wire assembly for vehicle high-voltage power decommissioning. The high voltage measurement port includes four externally accessible pins for obtaining an electrical characteristic measurement of a connected circuit. For redundancy, the assembly includes a resistor between a first measurement port pin and a first positive DC busbar at a first location, a resistor between a second pin and the first DC busbar at a second location different from the first location, a resistor between a third pin and a second negative DC busbar at a first location, and a resistor between a fourth pin and the second DC busbar at a second location different from the first location. Via the high voltage measurement port, a multi-meter can verify each resistance connection between the positive pins and then again between negative pins before a differential voltage measurement is made between positive and negative.

Abstract: An electric power interface features a body which is positionable in a sandwiched mount between an existing electric power meter and the mounting bracket for the electric meter. So positioned it allows for the formation of a secondary electric circuit extending from the body which may have electric current flowing therethrough measured by the original power meter or by a secondary power meter.

Abstract: A power detector device includes a voltage generator circuit, a reference circuit, a level hold circuit and a comparator circuit. The voltage generator circuit generates a bias voltage and a detection voltage according to a power supply voltage. The reference circuit generates a first reference voltage according to the power supply voltage. The level hold circuit selectively transmits the first reference voltage to a node according to the bias voltage, outputs a second reference voltage via the node, and holds a level of the second reference voltage after stopping transmitting the first reference voltage to the node. The comparator circuit compares the second reference voltage with the detection voltage to generate a power detection signal.

Abstract: A system for measuring power quality on an electrical grid is disclosed. The system comprises a plurality of monitoring systems installed at a plurality of structures receiving power via the electrical grid, the structure being at the edge of the electrical grid and including, for example, houses and other buildings. Each monitoring system is configured to be electrically coupled to a panel assembly and an electric service meter at the structure at which it is installed. Each monitoring system also comprises a measurement unit configured to measure electrical values associated with the panel assembly at the structure and to detect power quality events based on the measured electrical values. The system further includes a reporting system communicatively coupled to the monitoring systems and configured to receive data representing the detected power quality events from the monitoring systems.

Abstract: An example method includes following operations: (i) receiving a device signal from a device under test (DUT); (ii) setting an attenuation value; (iii) applying the attenuation value to the device signal to produce an attenuated device signal for a frequency spectrum analyzing device, where the frequency spectrum analyzing device produces a noise signal and intermodulation interference; (iv) obtaining a power spectral density value, where the power spectral density value comprises a power, at a frequency value, of a combined signal that is based on the attenuated device signal, the noise signal, and the intermodulation interference; (v) repeating operations (ii), (iii), and (iv) one or more times to produce multiple power spectral density values; (vi) repeating operations (i), (ii), (iii), (iv), and (v) one or more times to add power spectral density values to the multiple power spectral density values; and (vii) obtaining a power spectral density of the device signal.

Abstract: This application discloses a method and apparatus for phase detection, the said method comprising: receiving input pulse signals; obtaining the primary sampling points of the input pulse signals; calculating the first area formed by the waveform curve of the input pulse signals and the time axis within the preceding unit time of the primary sampling point; calculating the second area formed by the waveform curve of the input pulse signals and the time axis within the subsequent unit time of the primary sampling point; comparing the size of the first area with the size of the second area to obtain the first comparison result; outputting the phase detection result of the input pulse signals based on the first comparison result and a pre-defined true value rule.

Abstract: A remotely controlled, unmanned, rotorcraft, such as a drone, can measure an electrical parameter. The rotorcraft includes an electrically conductive contact element having a rigid substrate perpendicular to the connecting arm. The element is coated, at least on the face thereof opposite said arm, with a coating made of conductive flexible material.

Abstract: Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.

Abstract: Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.

Abstract: The invention relates to a method and a system for determining test signals for electromagnetic susceptibility, EMS, testing of a device-under-test, DUT. The method comprises the steps of: receiving at least one DUT parameter which defines a property of the DUT; receiving at least one environmental parameter which defines an electromagnetic environment, EME, in which the DUT is to be used; receiving information on an EM emission behavior, in particular an emission spectrum, of the DUT; and inputting the at least one DUT parameter, the at least one environmental parameter and the information on the EM emission behavior to a machine learning, ML, or artificial intelligence, AI, model. The ML or AI model is configured to determine one or more test signals for EMS testing of the DUT based on the at least one DUT parameter, the at least one environmental parameter and the information on the EM emission behavior.

Abstract: An expected-power-value estimation device is configured to in such a way as to include: a covariance matrix calculation unit that acquires a received signal vector of a reflected wave from a reception array antenna that receives the reflected wave from a target, and calculates a covariance matrix of the received signal vector; and an unnecessary vector value removal unit that removes a vector value present inside a convex hull of the array manifold vector from among a plurality of vector values that the array manifold vector of the reception array antenna can take. Furthermore, the expected-power-value estimation device includes an expected-power-value estimation unit that estimates an expected-power-value of the reflected wave using a vector value that is not removed by the unnecessary vector value removal unit among the plurality of vector values that the array manifold vector can take, and the covariance matrix calculated by the covariance matrix calculation unit.

Abstract: Disclosed are a power transmission line monitoring system and a power transmission line monitoring method. The monitoring method comprises: acquiring, by means of a functional node, monitoring data related to a power transmission line, and transmitting the monitoring data to an edge node; and receiving the monitoring data by means of the edge node, transmitting the monitoring data to a collection node by means of an edge node chain type communication network, and sending, by the collection node, the data to a master station server. In the application, a self-organized edge node chain type network is formed by means of edge nodes, and data transmission is performed by means of the edge node chain type network, so that problem of poor data transmission caused by impossible coverage of a cellular network can be solved.

Abstract: An estimation device for estimating a conversion factor which is a ratio between the number of photoelectrons generated from a pixel in response to inputting of light to the pixel and an electrical signal intensity output in response to the number of photoelectrons is provided. The estimation device includes: an acquisition unit configured to acquire a plurality of data groups including the electrical signal intensity for each of a plurality of pixels when light is input to the plurality of pixels; and a calculation unit configured to calculate the conversion factor for each of the plurality of pixels from the plurality of data groups based on a likelihood function indicating a likelihood of the conversion factor corresponding to the output electrical signal intensity.

Abstract: An example method includes the following operations: (i) receiving a device signal from a device under test (DUT); (ii) setting an attenuation value; (iii) applying the attenuation value to the device signal to produce an attenuated device signal for a frequency spectrum analyzing device, where the frequency spectrum analyzing device produces a noise signal; (iv) obtaining a power spectral density value using the frequency spectrum analyzing device, where a power spectral density comprises a power, at a frequency value, of a combined signal that is based on the attenuated device signal and the noise signal; (v) repeating operations (ii), (iii), and (iv) one or more times to produce multiple power spectral density values; (vi) repeating operations (i), (ii), (iii), (iv), and (v) one or more times to add power spectral density values to the multiple power spectral density values; and (vii) obtaining a power spectral density of the device signal.

Abstract: A measurement instrument for testing a DUT comprises a common port configured to be connectable to a signal output of the DUT for receiving a forward-travelling signal from the DUT. The measurement instrument further comprises a signal line connected to the common port, a signal analysis circuit and a signal generator circuit. The signal analysis circuit receives the forward-travelling signal from the common port. The signal analysis circuit is configured to analyze the forward-travelling signal in order to assess a performance of the DUT. The signal generator circuit is connected to the signal line and is configured to generate a backward-travelling signal that is forwarded to the common port. The signal generator circuit comprises a reference signal input configured to receive a reference signal from a reference signal generator. The signal generator circuit is configured to generate the backward-travelling signal based on the reference signal.

Abstract: A small-sized fast cold and hot shock test device is provided. The device includes a host, a test head used for cold and hot shock to a component under test by temperature control and output of compressed air, and an adjustment device for adjusting a position of the test head. The host includes a control device at least used to send temperature control data to the test head. The test head includes an eddy current mechanism for cooling or heating the compressed air, a heater including an air inlet end and an air outlet end, and a nozzle. The eddy current mechanism includes an air inlet, a cold air outlet, and a hot air outlet. The air inlet is connected with an air supply system through an intake air line unit. The cool air outlet is connected with the air inlet end of the heater.

Abstract: A small-sized fast cold and hot shock test device is provided. The device includes a host, a test head used for cold and hot shock to a component under test by temperature control and output of compressed air, and an adjustment device for adjusting a position of the test head. The host includes a control device at least used to send temperature control data to the test head. The test head includes an eddy current mechanism for cooling or heating the compressed air, a heater including an air inlet end and an air outlet end, and a nozzle. The eddy current mechanism includes an air inlet, a cold air outlet, and a hot air outlet. The air inlet is connected with an air supply system through an intake air line unit. The cool air outlet is connected with the air inlet end of the heater.

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The system includes a signal generator and a module. The signal generator is configured to apply an initial signal to an input terminal of a DUT during a first period; and apply a stress signal to the input terminal in a second period. The module is configured to: obtain an output signal in response to the initial signal and the stress signal at an output terminal of the DUT, the output signal in response to the stress signal including a first sequence and a second sequence, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage, wherein a duration of the first sequence is longer than that of the second sequence; and compare the output signal with the stress signal.

Abstract: In a semiconductor manufacturing method includes providing a plurality of patterns on a semiconductor substrate. The patterns include an NMOS structure arranged next to an N+/N well structure, and/or a PMOS structure arranged next to a P+/P well structure. The method further includes: receiving a plurality of images by applying an electron beam to the patterns; and transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns.

Abstract: A semiconductor failure analysis device includes a first analysis unit that emits first irradiation light along a first path set on a first main surface of a semiconductor device, a second analysis unit that emits second irradiation light along a second path set on a second main surface that is a back side of the first main surface, an electric signal acquisition unit that receives an electric signal output from the semiconductor device irradiated with the first irradiation light and the second irradiation light, and a computer that controls the second analysis unit. A size of a first irradiation region is different from a size of a second irradiation region. The computer emits the first irradiation light and the second irradiation light while a state where the entire second irradiation region overlaps the first irradiation region is maintained.

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

Abstract: Embodiments disclosed herein relate to clock gating. An example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. The clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.

Abstract: Systems, methods, and devices are described herein for performing intra-die and inter-die tests of one or more dies of an integrated circuit. A cell of an integrated circuit includes a data register, an I/O pad, and a first multiplexer. The data register is configured to output a signal. The I/O pad is coupled to the data register and configured to receive and buffer the signal. The first multiplexer is coupled to the I/O pad and the data register. The multiplexer is configured to selectively output either the buffered signal or the signal based on whether a scan mode or a functional mode is enabled.

Abstract: A method is provided for determining a decoupling capacitance of a device under test (DUT) interface circuitry, which is between automated testing equipment (ATE) and a DUT. The method: disconnects the DUT from the DUT interface circuitry; connects a Device Under Testing Power Supply (DPS) resource as a DUT Power Supply to the DUT interface circuitry; sets a current clamp of the DPS resource to a test application level; turns off the DPS resource voltage; sets the DPS resource to a force voltage mode; sets the current clamp to a minimum current level; turns on the output; waits a period of time to allow the decoupling capacitance to charge; places the DPS resource into a voltage measurement mode; adds any delay time to the period of time; measures the voltage before the capacitance is fully charged; and determines the decoupling capacitance.

Abstract: An example method of estimating an arc duration in a circuit breaker includes receiving a first measurement corresponding to a low-frequency electric field emitted from a vacuum circuit breaker during an interruption or circuit break operation and a second measurement corresponding to a low-frequency magnetic field, vibration, or acoustic emitted by the vacuum circuit breaker during operation, aligning the first measurement and the second measurement in time, wherein the first measurement is calibrated according to a first physical constant and wherein the second measurement is calibrated according to a second physical constant; and determining, by a sensor-fusion algorithm or a trained AI model, an estimated duration value of an arc duration using the time-aligned first measurement and second measurement, wherein the arc duration corresponds to a first time corresponding to a separation of contacts of the vacuum circuit breaker and a second time corresponding to arc extinction.

Abstract: A battery system including: a battery having a plurality of battery cells connected in parallel; a temperature sensor measuring a cell temperature of each of the plurality of battery cells; and a battery management system (BMS). The BMS determines: an estimated cell resistance value corresponding to a measured cell temperature value by using a first look-up table for each of the plurality of battery cells; an estimated cell current value based on the estimated cell resistance value and an estimated cell voltage value estimated during a (N?1)-th estimation period, N being a natural number greater than or equal to 1; an estimated cell capacity corresponding to the estimated cell current value by using a capacity estimation model; and the estimated cell voltage value corresponding to the estimated cell capacity as the estimated cell voltage value during an N-th estimation period using a second look-up table.

Abstract: A wireless battery module monitoring system includes a flexible printed circuit (FPC) including a first insulating layer. A conductive layer defines a plurality of traces arranged in a first predetermined pattern. A battery module monitoring circuit is connected to at least one of the plurality of traces of the FPC. A wireless transceiver is connected to at least one of the plurality of traces of the FPC at a location remote from the battery module monitoring circuit. An antenna is one of mounted on the FPC and connected to the wireless transceiver and implemented by at least one of the plurality traces of the conductive layer of the FPC and connected to the wireless transceiver.

Abstract: Disclosed is a power supply monitoring circuit including: a first terminal to which a first voltage as a highest voltage of a battery including cells is connected; a second terminal to which a second voltage as a lowest voltage of the battery is connected; a selection circuit that selects a high potential and a low potential of a cell; an analog-to-digital conversion circuit to which the high and low potentials are input; a power supply circuit that generates an operating voltage of the analog-to-digital conversion circuit; and a logic circuit that receives a signal from the analog-to-digital conversion circuit, processes the signal, and outputs a signal from a third terminal to an external device. The operating voltage is a first operating voltage with a midpoint of the high potential and the low potential as a reference.

Abstract: According to various embodiments, an operation method for determining an abnormality in a battery, the method comprising: acquiring battery information including a representative SOC value of the battery at a specific time point and a parameter value for an equivalent model circuit of the battery; acquiring an OCV deviation tolerance for the battery at the specific time point, predicting a polarization voltage deviation, and measuring a measured voltage deviation based on the battery information; and determining whether the battery is abnormal based on a sum of the OCV deviation tolerance and the polarization voltage deviation, and the measured voltage deviation, and a device thereof may be provided.

Abstract: A power unit operable to power equipment, the power unit including an electric motor, multiple removable and rechargeable battery packs, multiple switching elements, and a control unit. Each of the switching elements is connected between one of the battery packs and the electric motor and operate in one of an open position or a closed position. The control unit is operable to manage the position of the switching elements. The control unit is configured to determine whether one or more battery packs are supplying power for the electric motor, measure a voltage of each of the battery packs, determine whether each of the voltage measurements is within a predetermined value to each other, calculate a pulse width modulated (PWM) signal for each of the switching elements, assign each PWM signal to one of the switching elements, and apply each of the PWM signals to the assigned switching element.

Abstract: A vehicle such as an electric vehicle may include a battery such as a secondary battery that includes an electrode manufactured using a dry process. A system for evaluating a dry electrode mixture of the battery includes an electrical conductivity measurement device configured to measure electrical conductivity of the dry electrode mixture, and an analysis device configured to evaluate the dry electrode mixture based on the measured electrical conductivity.

Abstract: The present invention discloses a method for in-situ detection of the state of charge (SOC) of pouch-type lithium-ion batteries using ultrasonic guided waves. The invention involves attaching two circular piezoelectric patches symmetrically at a fixed distance from each other on the surface of the lithium-ion battery using a coupling agent. A function generator is controlled to produce a Hanning-window-modulated five-cycle sine signal to excite the circular piezoelectric patch located on the left side of the battery, generating ultrasonic guided waves within the battery. These waves are then received by the circular piezoelectric patch located on the right side of the battery. The received guided wave signal is processed to extract the time-domain characteristic parameters of the wave (transit time). Based on the correspondence between the guided wave characteristic parameters (transit time) and the state of charge, the method enables the detection of the SOC of the pouch-type lithium-ion battery.

Abstract: An electronic device may comprise a battery configured to supply power, and processing circuitry configured to, calculate a state of charge (SOC) calculated value of the battery based on sensed battery condition information of the battery, generate an SOC reported value, which fluctuates between a desired first value and a desired second value, wherein the desired second value is lower than the desired first value, based on at least one of the SOC calculated value, a charging status of the battery, a fully charged voltage of the battery, and a fully discharged voltage of the battery, and control the electronic device based on the SOC reported value.

Abstract: Provided are a direct current resistance (DCR) detection method for batteries, a system, a device, and a storage medium. Multiple discharging current pulses are applied during the constant current charging process of a battery to form a negative pulse charging mode. The discharging current can be added during the charging process to quickly remove the polarization effect of a battery cell generated during the charging process, thereby improving the charging acceptance capacity of the battery cell, shortening the charging time and increasing the charging efficiency. At the same time, a first battery voltage is obtained during the discharging current pulse time period, and a second battery voltage is obtained during the constant current charging time period after the discharging current pulse, thereby obtaining a DCR value of the battery during actual charging and use. The DCR of the battery cell can be detected simultaneously in the negative pulse charging mode.

Abstract: A method for ascertaining the state of health of the vehicle battery of an electric vehicle includes charging the vehicle battery and ascertaining specified battery parameters during the charging process, and calculating the state of health of the vehicle battery using a vehicle-specific battery model on the basis of the transmitted battery parameters. A basic battery model, which is based on the vehicle battery type, in the form of an electric equivalent circuit model is first used as the vehicle-specific battery model, wherein the internal resistance and RC elements are ascertained as a function of the cell temperature and the charge state, an open circuit voltage characteristic is ascertained as a function of the charge state, and the cell temperature is ascertained using a thermal model on the basis of the measured battery pack current, EC parameters, the battery module temperature, and the ambient temperature.

Abstract: Systems and methods for improving device locatability are disclosed herein. An example method includes determining a beacon mode capacity of a device battery, the beacon mode capacity corresponding to a device operating in a beacon mode while powered by the device battery. The example method further includes calculating a total battery power of the device battery and an aged total battery power of the device battery based on the total battery power and a state of health (SOH) of the device battery. The example method further includes determining a beacon state of charge (SOC) threshold for the device battery based on the beacon mode capacity and the aged total battery power, and causing the device to begin operating in the beacon mode when a remaining charge of the device battery is less than the beacon SOC threshold.