Patents Issued in November 28, 2024
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Publication number: 20240394141Abstract: The mapping of system memory addresses to physical memory addresses is modeled as a two dimensional mapping array. Each element of the mapping array is assigned a system memory address and a physical memory address to which the system memory address is mapped. The mapping array is arranged to facilitate designation of a portion of the physical memory addresses as spareable physical memory addresses that are employed when there is a memory failure.Type: ApplicationFiled: May 26, 2023Publication date: November 28, 2024Inventors: Gurushankar Rajamani, Horia Alexandru Toma, Le Wang, Spoorthy Nanjaiah, Albert Forte Magyar, Xiaoming Wang
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Publication number: 20240394142Abstract: Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.Type: ApplicationFiled: July 8, 2024Publication date: November 28, 2024Applicant: MICRON TECHNOLOGY, INC.Inventor: Beau D. Barry
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Publication number: 20240394143Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Inventors: Jonathan Scott Parry, Nadav Grosz, David Aaron Palmer, Christian M. Gyllenskog
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Publication number: 20240394144Abstract: The technology described herein involves encoding data representing an array of finite field elements for performing calculations when creating RAID storage systems, characterized in that the bits encoding each element of the Galois field are not arranged sequentially, one after the other, but in increments of n bits, where n>1.Type: ApplicationFiled: May 16, 2024Publication date: November 28, 2024Inventor: Andrey Fedorov
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Publication number: 20240394145Abstract: A method includes: determining, in response to a failure of a disk where a RAID extent (RE) in a storage system is located, a first disk set based on a predetermined range and the failed disk, wherein the first disk set comprises a plurality of disks within the predetermined range that are associated with the RE; determining a second disk set for rebuilding data located on the failed disk based on other disks in the first disk set than the plurality of disks that are associated with the RE; determining scores for disks in the second disk set based on disk correlations, RE spans, and weights of the plurality of disks in the second disk set; determining a target disk among the plurality of disks in the second disk set based on the plurality of scores; and rebuilding the data located on the failed disk on the target disk.Type: ApplicationFiled: June 15, 2023Publication date: November 28, 2024Inventors: Huijuan Fan, Chi Chen, Hailan Dong
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Publication number: 20240394146Abstract: A processor in a storage network operates by: receiving an access request for a data segment, wherein the data segment is encoded utilizing an error correcting information dispersal algorithm as a set of encoded data slices that are stored in a plurality of storage units of the storage network and wherein each encoded data slice of the set of encoded data slices includes a corresponding checksum of a plurality of checksums; retrieving, from the storage network, a subset of encoded data slices that includes a threshold number of encoded data slices of the set of encoded data slices; determining, based on ones of the plurality of checksums corresponding to the subset of encoded data slices, when the subset of encoded data slices includes at least one corrupted encoded data slice; retrieving from at least one of the plurality of storage units an addition number of encoded data slices required to generate a reconstructed data segment based on the subset of encoded data slices; generating the reconstructed data seType: ApplicationFiled: August 1, 2024Publication date: November 28, 2024Applicant: Pure Storage, Inc.Inventors: Greg R. Dhuse, Vance T. Thornton, Jason K. Resch, Ilya Volvovski, Dustin M. Hendrickson, John Quigley
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Publication number: 20240394147Abstract: Systems and methods described herein can involve managing volume management information indicative of a relationship between an application and a volume used by the application; for receipt of a first request to make the application ready for takeover to another location, updating the volume management information to indicate that another volume of the another location is associated with the application. For receipt of a second request to conduct volume attachment for the application, the systems and methods can involve identifying one or more volumes associated with the application based on the volume management information; and attaching an identified volume from the identified one or more volumes to the application.Type: ApplicationFiled: May 24, 2023Publication date: November 28, 2024Inventor: Akiyoshi TSUCHIYA
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Publication number: 20240394148Abstract: USB Timer Boards and methods for backing up digital data from a host system onto storage devices which are automatically selected on an individual basis for digital connection, data exchange, data storage on a scheduled basis, and then digitally disconnected. When the storage devices are not selected and connected for backup data transfer and storage, the storage devices remain offline and not visible to the host system. USB Timer Boards and methods which backup data on one of a number of offline storage devices by connecting a selected storage device, backup data onto it and then disconnecting it, in order to isolate the backed-up data and optionally allow a different storage device to be used for the next back up event. The USB Timer Boards and methods include a real time clock and battery to allow the USB Timer Board to retain the exact date and time settings during power-off events.Type: ApplicationFiled: May 13, 2024Publication date: November 28, 2024Applicant: Computero Inc.Inventors: Bartosz Piotrowski, Leonid Kulskyi
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Publication number: 20240394149Abstract: A method for managing a client environment includes obtaining a notification for an auto-generated service request, wherein the auto-generated service request is associated with an issue with the client environment, in response to the notification: obtaining metadata associated with the auto-generated service request, analyzing the metadata to extract pattern information, comparing the pattern information to a service request pattern database, making a determination, using the service request pattern database, that a recommendation is associated with the pattern information, and based on the determination, performing a remediation action associated with the recommendation.Type: ApplicationFiled: May 26, 2023Publication date: November 28, 2024Inventors: Mahantesh Ambaljeri, Shelesh Chopra, Gururaj Kulkami
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Publication number: 20240394150Abstract: Performing disaster recovery in a cloud-based storage system, including: creating, by a storage system a snapshot of a dataset; uploading, from the storage system to a cloud computing environment, the snapshot; storing, by the cloud computing environment, the snapshot; detecting, by the cloud computing environment, that the dataset is not available on the storage system; and creating, by the cloud computing environment using the snapshot that is stored within the cloud computing environment, a cloud-based storage system that includes the dataset.Type: ApplicationFiled: August 2, 2024Publication date: November 28, 2024Inventors: JAMES FISHER, NAVEEN NEELAKANTAM, YUVAL FRANDZEL
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Publication number: 20240394151Abstract: Modifying a storage system configuration using a large language model (‘LLM’), including: receiving a request for a deployment of a resource; generating, by a large language model (LLM), based on the request and a configuration of a computing environment, data facilitating a deployment of the resource in the computing environment; and providing the data facilitating the deployment of the resource in response to the request.Type: ApplicationFiled: August 2, 2024Publication date: November 28, 2024Inventors: BOGUMILA ANNA FRESE, VASILEIOS KARAVAS, EDOUARD PERNOT, BRYAN SMÉE, KIN LUNG WILLIAM PANG, NAVEEN NEELAKANTAM
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Publication number: 20240394152Abstract: A method and a system for providing database resiliency are disclosed. The method includes receiving a set of data from one or more sources at a primary database. Next, the method includes continuously monitoring for a potential detection of at least one anomaly in the set of data based on at least one activity performed on the set of data. Next, the method includes transmitting a plurality of data logs associated with the set of data from the primary database to an intermediate log storage location. Next, the method includes introducing a predefined delay to the plurality of data logs at the intermediate log storage location prior to a transmission of the plurality of data logs to a recovery database. Thereafter, the method includes performing a standby switchover to the recovery database in an event the at least one anomaly is detected at the primary database.Type: ApplicationFiled: July 6, 2023Publication date: November 28, 2024Applicant: JPMorgan Chase Bank, N.A.Inventors: Raghunath PAIKARAY, Rama Shankar SAHU, Amar JAIN, Jay BORHADE, Naresh E ANDHE
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Publication number: 20240394153Abstract: Techniques are described that include receiving, by a computing system, a request to create a restored block volume using a first manifest, the first manifest comprising: (i) a block identifier for a block and (ii) a first block sequence number corresponding to the block identifier and associated with a first snapshot, and (iii) a manifest identifier. The techniques further include receiving, by the computing system, the request to create the restored block volume using a second manifest, the second manifest comprising: (i) the block identifier for the block, (ii) a second block sequence number corresponding to the block identifier and associated with a second snapshot. The techniques further include determining, by the computing system, whether the second block sequence number is indicative of the block having been altered after the first manifest was generated, and responsive to the determination by the computing system, creating the restored block volume.Type: ApplicationFiled: April 11, 2024Publication date: November 28, 2024Applicant: Oracle International CorporationInventor: Travis John PORTZ
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Publication number: 20240394154Abstract: A failure of a head is detected, the head reading from and writing to an affected surface of a disk of a disk drive. The failure prevents the head from writing to the affected surface but does not prevent the head from reading from the affected surface. In response to detecting the failure, a remediation is performed. The remediation involves determining spare capacity blocks on other surfaces of the disk drive different than the affected surface, and copying data from the affected surface to the spare capacity blocks via an internal copy function within the disk drive. The spare capacity blocks in place of the affected surface for data storage and retrieval subsequent to the failure.Type: ApplicationFiled: May 22, 2024Publication date: November 28, 2024Inventors: Mohamad El-Batal, Curtis Stevens, David Allen, Jon D. Trantham, Ian Robert Davies, Mark A. Gaertner
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Publication number: 20240394155Abstract: A method for performing data access management of a memory device in predetermined communications architecture to enhance sudden power off recovery (SPOR) of page-group-based redundant array of independent disks (RAID) protection with aid of suspendible serial number and associated apparatus are provided. The method may include: utilizing the memory controller to write preceding data and metadata thereof into at least one set of preceding pages in a first active block to make the metadata carry at least one preceding serial number; writing dummy data and other metadata into at least one set of dummy pages in the first active block to make the other metadata carry at least one suspended serial number which is equal to a last serial number among the at least one preceding serial number; and utilizing the memory controller to write subsequent data and metadata thereof to make it carry at least one subsequent serial number.Type: ApplicationFiled: May 26, 2023Publication date: November 28, 2024Applicant: Silicon Motion, Inc.Inventors: Jie-Hao Lee, Chun-Ju Chen, Po-Ting Chen
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Publication number: 20240394156Abstract: A technique provides network efficient data failover by explicitly protecting one or more common snapshot references at sites of a multi-site data replication environment to improve granularity of control of recovery point objectives (RPO) for data across the sites. A common snapshot reference or recovery point (RP) ensures that, in the event of failure to a site, data designated for failover may be quickly protected by replicating only small incremental changes to the RP so as to maintain RPO requirements across the sites. Illustratively, the technique enhances and extends a disaster recovery (DR) application programming interface (API) protocol through an extension that defines and applies a tag to the RP, wherein the tag enables protection and/or preservation of the RP by ensuring that the sites honor the tag applied to the RP. The tag essentially functions as an advisory lock for the RP that is shared among the sites to prevent deletion of the RP at the sites throughout the duration of the lock.Type: ApplicationFiled: August 8, 2024Publication date: November 28, 2024Inventors: Kai Tan, Karthikeyan Vaideswaran, Pranab Patnaik, Ramya Uthamarajan
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Publication number: 20240394157Abstract: A system comprises a first data center, a second data center and a cloud server. A first server of the first data center receives a command to process a first processing job, accesses from the cloud server a software application, and processes the first processing job using the software application. The first server transmits the processing data associated with the processing to a second data center. A second server of the second data center receives and stores the processing data in a memory associated with the second data center. The second server detects that the processing of the first processing job was interrupted at the first server and, in response, resumes the processing based on the processing data.Type: ApplicationFiled: May 26, 2023Publication date: November 28, 2024Inventors: Gayathri Vangala, Kalpana Kumaraswami, Gaurav Jain
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Publication number: 20240394158Abstract: Methods and systems are described for provisioning cloud-based database systems and performing decoupled maintenance. For example, conventional systems may rely on database management systems to provision and modify databases hosted by a service provider. However, for entities operating complex database systems with the need for highly customized cloud infrastructure, database management systems fail to provide the granular customization and the control necessary to create and service these systems. In contrast, the described solutions provide an improvement over conventional database management system architecture by providing direct communication between an entity and its cloud-based database systems via command line prompts or API calls, decoupling database system maintenance from database system provisioning process to increase the speed and granular customization of the database system.Type: ApplicationFiled: May 23, 2023Publication date: November 28, 2024Inventors: Vitaliy Mogilevskiy, Abhishek Chanda, Norberto Leite, Maryame Boulhajat, Miguel Pilar
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Publication number: 20240394159Abstract: Managing storage systems that are synchronously replicating a dataset, including: detecting a change in membership to the set of storage systems synchronously replicating the dataset; and applying one or more membership protocols to determine a new set of storage systems to synchronously replicate the dataset, wherein the one or more membership protocols include a quorum protocol, an external management protocol, or a racing protocol, and wherein one or more I/O operations directed to the dataset are applied to a new set of storage systems.Type: ApplicationFiled: August 1, 2024Publication date: November 28, 2024Inventors: RONALD KARR, DAVID GRUNWALD, NAVEEN NEELAKANTAM, ZOHEB SHIVANI, THOMAS GILL, CONNOR BROOKS, ASWIN KARUMBUNATHAN, KUNAL TRIVEDI
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Publication number: 20240394160Abstract: A hot storage backup system and method for server, relating to the technical field of servers. The method includes: after a Complex Programming Logic Device (CPLD) in a hard disk backboard detects access of a hard disk, triggering a hard disk access signal and sending same to a Central Processing Unit (CPU), and sending command parameters, corresponding to the hard disk, combined by a Basic Input Output System (BIOS) to the CPU; and checking, by the CPU, the command parameters with a mapping table, and in the case that the check is successful, setting an Advanced Configuration and Power Management Interface (ACPI) protocol according to the command parameters, so that the server normally recognizes the hard disk, thereby implementing a hot storage backup function through the hard disk.Type: ApplicationFiled: June 30, 2022Publication date: November 28, 2024Applicant: IEIT SYSTEMS CO., LTD.Inventors: Xiuqiang SUN, Jiaming HUANG, Xiaobao WANG, Fanyi YAO
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Publication number: 20240394161Abstract: The present disclosure relates to a testing technology field, in particular, relates to a method for testing stability and an electronic device. The method includes: in response to a testing start operation instruction triggered by a user, controlling a relay of a testing circuit of the server switch to perform a power-off operation and a power-on operation; after completing the power-off operation and the power-on operation by the relay, sending a testing instruction to the server switch; in response to the testing instruction, receiving testing data returned by the server switch, and executing a testing task according to the testing data, and obtaining a testing result. The present disclosure is able to achieve independent and out of band stability testing of server switches, greatly saving labor and time costs, and improving testing efficiency.Type: ApplicationFiled: November 13, 2023Publication date: November 28, 2024Inventors: TENG-FEI MA, JIE YUAN
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Publication number: 20240394162Abstract: A computer-implemented method, according to one embodiment, includes: intentionally causing faults to be injected in a compute infrastructure, and determining whether the injected faults cause application failures. Weights are also assigned to the injected faults based on severity of the respective application failures. The weighted faults are compared, and changes to the compute infrastructure are recommended based on the comparison. Moreover, the changes that are recommended are configured to prevent the application failures. Other systems, methods, and computer program products are described in additional embodiments.Type: ApplicationFiled: May 25, 2023Publication date: November 28, 2024Inventors: Sandeep Hans, Mudit Verma, Samuel Solomon Ackerman, Diptikalyan Saha, Eitan Daniel Farchi, Praveen Jayachandran
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Publication number: 20240394163Abstract: Apparatus and methods for automatically testing mobile devices are disclosed according to various embodiments. In one example, a disclosed apparatus includes: a robot having a retention device into which the mobile device to be tested is positioned; a test computer having a processor and a non-transitory computer readable storage medium storing test software for testing the mobile device; and a user monitor electrically connected to the test computer and configured for providing a result of the testing of the mobile device. The mobile device is wirelessly connected to the test computer and has a test application installed thereon corresponding to the test software. The robot is configured for performing interaction and manipulation of the mobile device in cooperation with the test application and the test software during the testing.Type: ApplicationFiled: August 8, 2024Publication date: November 28, 2024Applicant: Communications Test Design, Inc.Inventors: Gerald J. PARSONS, Brian PARSONS, Sean PARSONS, Mark PARSONS, Nidhin DAVIS, Timothy HOPFER, Pooya HEIRATY, Soham PATWARDHAM, Lukasz MACNAR, Mario HUBER, Martian FIEDLER, Bartosz BEDYNSKI, Nick GAMBER
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Publication number: 20240394164Abstract: Methods, systems, and devices for memory performance evaluation using address mapping information are described. A memory system may write a data file associated with a range of logical block addresses to a first set of blocks in a set of memory dies. The memory system may then determine, for a memory die of the set of memory dies that stores a portion of the data file, a quantity of read operations for reading the portion of the data file. The memory system may determine the quantity of read operations based on address mapping information that maps logical block addresses associated with the datafile to physical addresses. After determining the quantity of read operations, the memory device may use the quantity of read operations to determine a performance metric associated with the data file and the first set of blocks.Type: ApplicationFiled: July 25, 2022Publication date: November 28, 2024Inventors: Ziqing WU, Wenjun WU, Xiaolai ZHU, Chunyu SHENG, Xiao WANG
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Publication number: 20240394165Abstract: A method includes obtaining a discovery pattern that indicates a plurality of operations associated with a corresponding computing resource type of a plurality of computing resource types. The method also includes identifying a variable parameter value associated with execution of the discovery pattern with respect to a computing resource of the corresponding computing resource type, and determining an error value by using a machine learning model to process the variable parameter value. The error value indicates a likelihood that execution of the discovery pattern, when associated with the variable parameter value, with respect to the particular computing resource results in a corresponding error type. The method further includes receiving, based on the error value, an input comprising one or more of (i) an instruction to execute the discovery pattern or (ii) a modification applicable to the variable parameter value.Type: ApplicationFiled: May 24, 2023Publication date: November 28, 2024Inventors: Shay Herzog, Asaf Garty
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Publication number: 20240394166Abstract: A dialysis system includes a plurality of hydraulically connected components and a control device. A method of operating the dialysis system includes receiving component operating data from the components, the component operating data including at least demand data for an upcoming task to be performed by the respective component, determining an expected resource consumption of the component based on the demand data, monitoring of an actual resource consumption of the components, determining a deviation of the actual resource consumption from the expected resource consumption, and detecting a leakage in the dialysis system if the deviation is outside a predetermined range.Type: ApplicationFiled: May 22, 2024Publication date: November 28, 2024Inventors: Stephan Krietemeyer, Philipp Odernheimer, Nino Lieb, Jonas Giesa
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Publication number: 20240394167Abstract: A system may receive a first directed acyclic graphic (DAG) for an application. The system may model performance of each function in the DAG to generate a performance model. The system may generate a plurality of variant DAGs. For each of the variant DAGs, the system may obtain a configuration vector and forecast, based on the performance model and the configuration vector, a plurality of end-to-end latency distributions for the variant DAGS. The system may select the variant DAG and configuration vector based on a selection criteria. The system may cause an application to be executed according to the variant DAG and configuration vector.Type: ApplicationFiled: May 28, 2024Publication date: November 28, 2024Applicant: Purdue Research FoundationInventors: Somali Chaterji, Saurabh Bagchi, Ashraf Mahgoub, Sameh Elnikety
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Publication number: 20240394168Abstract: To reproduce, in consideration of the distributed hardware configuration, a software execution timing in a target environment on a host environment with high accuracy. A simulation method includes: extracting a first host feature value 11 obtained by executing first software 10 on a host environment 100; executing the first software 10 on a target environment 110 to calculate a target execution time 20 taken to execute the first software 10 on the target environment 110; calculating a performance difference between the host environment 100 and the target environment 110 based on the first host feature value 11 and the target execution time 20; extracting a second host feature value 13 obtained by executing second software 12 on the host environment 100; and estimating a time 40 taken to execute the second software 12 on the target environment 110 based on the second host feature value 13 and the performance difference.Type: ApplicationFiled: August 15, 2022Publication date: November 28, 2024Applicant: HITACHI ASTEMO, LTD.Inventors: Yuma KATO, Tasuku ISHIGOOKA, Yasuhiro FUSE, Akihiro KONDO, Yoshitaka ATARASHI
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Publication number: 20240394169Abstract: Systems and methods are provided for improved auditing of user actions associated with a software application. The system includes functionality to log user actions in a structured, standardized way. The system includes interactive user interfaces for analyzing the logs. The logging is based on a well-defined categorization of available actions. The log information includes (and distinguishes among) user details, context details, user inputs, and/or system outputs (including identification of data objects). The interactive user interfaces enable a user to view structured log data in an efficient manner, such as by presenting logs in a tabular format, executing queries on the log data, and/or presenting visualizations that summarize the log data. The interactive user interfaces provide functionality that allows a user to investigate and/or audit user interactions with a data object. The interactive interfaces present log entries associated with the object(s) for further review by the reviewer.Type: ApplicationFiled: August 7, 2024Publication date: November 28, 2024Inventors: Natalie Meurer, Andrew Lampert, Dyon Balding, Yeong Wei Wee
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Publication number: 20240394170Abstract: Systems and methods for detecting accessibility failures. In some aspects, the system receives a request for evaluating accessibility for a user interface of an updated version of a software application, wherein the request includes the updated and previous versions of the software application, and previous textual data corresponding to the previous version. The system generates audio output by using a screen reader to process the user interface. Textual data is generated by processing the audio output using speech recognition. The system compares the textual data to previous textual data to determine whether feature differences are present between the updated and previous versions. The one or more feature differences are analyzed to identify a feature difference corresponding to an accessibility failure point. In response to identifying the accessibility failure point, the system determines actions for removing the accessibility failure point.Type: ApplicationFiled: May 26, 2023Publication date: November 28, 2024Applicant: Capital One Services, LLCInventors: Mark MORRISON, Tom VANDENBERGE
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Publication number: 20240394171Abstract: According to embodiments of the present disclosure, there are provided a method, an apparatus, a device and a storage medium for code parameter verification. In a method, a parameter verification request for target code is detected; in response to detecting a parameter verification statement, at least one code segment is extracted from the target code that matches at least one predetermined statement type of a plurality of predetermined statement types; and a verification statement for at least one parameter of the target code is generated, with a trained machine learning model, based on the at least one code segment, the verification statement being configured to verify validation of the at least one parameter, where the machine learning model is trained based on a sample code set and sample verification statement for parameters of sample code in the sample code set.Type: ApplicationFiled: May 22, 2024Publication date: November 28, 2024Inventors: Xu Duan, Huan Song, Yannan Liu, Jie Liu
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Publication number: 20240394172Abstract: Disclosed is a method inferring function symbol names from assembly code in an executable binary with transformer-based architecture on a computing apparatus having at least one processor. The method includes: performing BPE (Byte-Pair-Encoding) tokenization on the assembly code, without code normalization for using the assembly code as an input to the inference model; and inferring the function symbols based on the input. The inference model performs operations as follows: at each layer of an encoder and decoder, normalizing input tokens by grouping similar tokens in an input vector and then dividing each group by a sum of unique values, and applying positional embedding at each layer of the encoder.Type: ApplicationFiled: May 24, 2024Publication date: November 28, 2024Applicant: Research & Business Foundation Sungkyunkwan UniversityInventors: Hyungjoon KOO, Hyunjin KIM, Jinyeong BAK
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Publication number: 20240394173Abstract: Described are techniques for evaluating the readiness level in the industrial floor infrastructure and automation software to ensure that the appropriate automation software is being utilized to control the appropriate industrial floor infrastructure. A digital twin simulation is created and executed to analyze the capabilities of the industrial floor infrastructure in view of an update to the automation software to identify capabilities of the updated automation software that are utilized by the existing capabilities of the industrial floor infrastructure. Recommendations may then be provided to upgrade, replace, install and/or perform proactive maintenance of the industrial floor infrastructure to further utilize the capabilities of the updated automation software if the capabilities of the updated automation software are not being utilized with the existing capabilities of the industrial floor infrastructure at an acceptable level.Type: ApplicationFiled: May 24, 2023Publication date: November 28, 2024Inventors: Tushar Agrawal, Jeremy R. Fox, Sarbajit K. Rakshit
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Publication number: 20240394174Abstract: The present disclosure provides an application software (APP) testing method, an electronic device, and a computer-readable storage medium. The APP testing method includes: acquiring a key log; determining information related to a tested fault cause according to the key log; acquiring a User Interface (UI) screenshot; and comparing the UI screenshot with a pre-stored UI design drawing, and determining whether there is a difference between the UI screenshot and the UI design drawing. The APP testing method provided by the present disclosure can realize quick check of network access logs and crash logs even without a platform of a development tool, assist testers and developers in problem reproduction and fault location, and improve development efficiency of the developers.Type: ApplicationFiled: July 18, 2022Publication date: November 28, 2024Inventors: Jing LUO, Jianzheng DUN, Pei ZHANG, Xin HOU, Zijian LI
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Publication number: 20240394175Abstract: A method is disclosed and includes determining a test plan to test a kernel on a mobile device, and determining an interaction input message according to the test plan, the interaction input message comprising first data. The method also includes transmitting the interaction input message comprising the first data to the mobile device over a network-based communication channel. The kernel in the mobile device generates the interaction output message in response to receiving the interaction input message. The method also includes receiving, from the mobile device, the interaction output message comprising second data from the mobile device over the network-based communication channel, and determining if the interaction output message is consistent with the test plan.Type: ApplicationFiled: August 2, 2024Publication date: November 28, 2024Applicant: Visa International Service AssociationInventors: Yuexi Chen, Hendy Wong, Sarah Jane Galamay
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Publication number: 20240394176Abstract: A computer-implemented method, computer program product and computing system for: providing evaluation content to a target chatbot, wherein the evaluation content includes a plurality of inquiries and a plurality of anticipated responses; processing the plurality of inquiries on the target chatbot; receiving a plurality of generated responses from the target chatbot in response to the plurality of inquiries; and comparing the plurality of generated responses received from the target chatbot to the plurality of anticipated responses included within the evaluation content.Type: ApplicationFiled: May 24, 2024Publication date: November 28, 2024Inventors: Christian Pean, Hadi Javeed
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Publication number: 20240394177Abstract: A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. A respective data buffer includes data paths and logic configurable to, in response to the second module control signals, enable at least a subset of the data paths to receive and regenerate signals carrying a section of the data communicated from/to corresponding module data lines. The logic is further configurable to disable the data paths when the memory module is not communicating data with the memory controller.Type: ApplicationFiled: May 27, 2024Publication date: November 28, 2024Inventors: Hyun Lee, Jayesh Bhakta
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Publication number: 20240394178Abstract: A stacked memory device comprises a stack of dies including respective core memories. An interface die in the stack includes interface circuitry for interfacing between a data bus coupled to a memory controller and the respective core memories of the stack of dies. The interface circuitry may implement decoding of data received from the data bus for the respective core memories and encoding of data sent to the data bus from the respective core memories. The respective core memories of the stacked memory device may be arranged in two or more ranks. A memory module includes a set of stacked memory devices. The stacked memory devices may be arranged in various configurations having varying numbers of channels, ranks, and data widths.Type: ApplicationFiled: October 20, 2022Publication date: November 28, 2024Inventor: Torsten Partsch
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Publication number: 20240394179Abstract: A memory management unit-less (MMU-less) device having at least one processing unit, a RAM, and a built-in non-volatile memory of the MMU-less device. The built-in non-volatile memory or the RAM stores a loader component configured to load a plurality of allocatable sections from an executable file into available blocks in the RAM, to record into the RAM a table of correspondence between the allocatable sections of the plurality and addresses at which the allocatable sections are loaded, and to perform at least one relocation for an invocation from a one of the allocatable sections of the plurality to the same or another of the allocatable sections of the plurality based on the table of correspondence.Type: ApplicationFiled: May 27, 2024Publication date: November 28, 2024Inventors: IVAN KOTOMIN, SERGEI GAVRILOV, ALEKSANDR KUTUZOV
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Publication number: 20240394180Abstract: Systems and methods for computer memory management by a memory coordinator and a plurality of memory consumers. An urgency and memory quota of each memory consumer is initialized by the memory coordinator, which then adjusts the memory quota of each memory consumer such that the sum of the memory quota of each memory consumer does not exceed a finite amount of computer memory. Each memory consumer adjusts its memory usage in response to the quota input and urgency input from the memory coordinator.Type: ApplicationFiled: August 6, 2024Publication date: November 28, 2024Inventors: Angela LIN, Robert WALKER, Marin CREANGA, Dylan ELLICOTT, Alex FITZPATRICK
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Publication number: 20240394181Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.Type: ApplicationFiled: August 6, 2024Publication date: November 28, 2024Applicant: KIOXIA CORPORATIONInventor: Shinichi KANNO
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Publication number: 20240394182Abstract: In some situations, the programming of one memory die can be suspended in favor of the programming of another memory die. This can lead to a delay in certain programming operations. To avoid this problem, a data storage device can perform dynamic logical page write ordering by determining an availability of each memory die of a plurality of memory dies and changing a programing order of the plurality of memory dies in response to the determined availability.Type: ApplicationFiled: July 21, 2023Publication date: November 28, 2024Applicant: Western Digital Technologies, Inc.Inventors: Noor Mohamed AA, Ramanathan Muthiah, Subash Rajaram
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Publication number: 20240394183Abstract: Devices and techniques for corrupted storage portion recovery in a memory device are described herein. A failure event can be detected during a garbage collection operation on a collection of storage portions (e.g., pages) in a memory array. Here, members of the collection of storage portions are being moved from a former physical location to a new physical location by the garbage collection operation. A reference to a former physical location of a possibly corrupt storage portion in the collection of storage portions can be retrieved in response to the failure event. Here, the possibly corrupt storage portion has already been written to a new physical location as part of the garbage collection operation. The possibly corrupt storage portion can then be rewritten at the new physical location using data from the former physical location.Type: ApplicationFiled: August 2, 2024Publication date: November 28, 2024Inventors: Lalla Fatima Drissi, Giuseppe D'Eliseo, Paolo Papa, Massimo Iaculo, Carminantonio Manganelli
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Publication number: 20240394184Abstract: Embodiments of the present disclosure relate to a method, a device, and a computer program product for storing data. The method includes determining multiple access frequencies and multiple input/output (IO) modes of multiple data blocks, where the multiple data blocks are stored in a disk, and an IO mode in the multiple IO modes indicates an access size, a read operation proportion, and a sequential access proportion. The method further includes determining multiple cache hit ratios corresponding to the multiple IO modes. The method further includes determining multiple scores of the multiple data blocks based on the multiple access frequencies and the multiple cache hit ratios. In addition, the method further includes determining, based on the multiple scores of the multiple data blocks, a data block in the multiple data blocks to be replicated to a cache.Type: ApplicationFiled: June 16, 2023Publication date: November 28, 2024Inventors: Hailan Dong, Chi Chen, Huijuan Fan
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Publication number: 20240394185Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.Type: ApplicationFiled: August 2, 2024Publication date: November 28, 2024Inventor: Andrew M. Kowles
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Publication number: 20240394186Abstract: Various embodiments include techniques for storing data in a repurposed cache memory in a computing system. The disclosed techniques include a system level cache controller that processes a memory operation for a processing unit. The controller and the processing unit communicate over a network-on-chip. To process the memory operation, the controller selects a repurposed cache memory from a pool of active cache memories associated with processing units that are inoperable and/or are in a low-power state. To select the repurposed cache memory, the controller generates a candidate vector that identifies the position of the requesting processing unit relative to the controller. The candidate vector enables the controller in selecting a repurposed cache memory that is, for example, on the shortest path between the processing unit and the controller. These techniques result in a lower latency, and improved memory performance, relative to prior conventional techniques.Type: ApplicationFiled: May 23, 2023Publication date: November 28, 2024Inventors: Ariel SZAPIRO, Anurag CHAUDHARY, Mark ROSENBLUTH, Mayank BAUNTHIYAL
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Publication number: 20240394187Abstract: Reclamation of a portion of a cache memory in a cloud computing environment is described herein. A cache activeness signal is received from a cache broker. The cache activeness signal is representative of a usage of a first set of cache entries of the cache memory by a first group of computing nodes in a cluster of nodes. A determination to reclaim a portion of the first set of cache entries or of a second set of cache entries is made based at least on the cache activeness signal. The second set of cache entries are utilized by a second group of computing nodes in the cluster of nodes. The determined portion of memory is reclaimed. In an aspect, the cache broker determines a usage of the set of cache entries by the first group of computing nodes and generates the cache activeness signal representative of the determined usage.Type: ApplicationFiled: May 26, 2023Publication date: November 28, 2024Inventors: Junfeng DONG, Ajay KALHAN, Michael E. HABBEN, John M. OSLAKE, Preetham Melavarige GOPALAKRISHNA, Dhrumilkumar Utpalbhai SHAH, Purvi SHAH
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Publication number: 20240394188Abstract: The present disclosure discloses a command accessing method having power saving mechanism is provided that includes steps outlined below. A cache control circuit is controlled to retrieve a plurality of commands from a command source to be executed. A plurality of loop commands corresponding to a loop procedure included in the commands are determined, wherein the loop commands include a first part that matches a storage amount of a command buffer circuit and a second part that exceeds the storage amount. The cache control circuit is controlled to store the first part of the loop commands to the command buffer circuit and not store the second part of the loop commands to the command buffer circuit. The cache control circuit is controlled to, every time the loop procedure is performed, retrieve and execute the first part of the loop commands from the command buffer circuit and retrieve and execute the second part of the loop commands from the command source.Type: ApplicationFiled: May 21, 2024Publication date: November 28, 2024Inventors: JUI-YUAN LIN, YING-WEI WANG
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Publication number: 20240394189Abstract: Provided herein may be a memory system and a host device. The memory system may include a first memory module communicating with a host through a first interface and a second memory module communicating with the host through a second interface. The second memory module may include a memory device configured to store data and a memory controller configured to update at least one of first metadata related to a space-locality and second metadata related to a time-locality based on a result of comparing the numbers of the pages respectively corresponding to a first trigger address and a second trigger address sequentially input from the host, and to prefetch, to the first memory module, the data determined based on the first metadata and the second metadata. The first and second trigger addresses are addresses corresponding to data for which access to the first memory module is missed.Type: ApplicationFiled: August 8, 2024Publication date: November 28, 2024Inventor: Sung Woo HYUN
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Publication number: 20240394190Abstract: The present application provides a method of training a deep learning model. A specific implementation solution of the method of training the deep learning model includes: determining, according to first training data for a current training round, a first target parameter required to be written into a target memory in a first network parameter required by an embedding of the first training data, wherein the target memory is a memory contained in a target processor; determining a remaining storage slot in the target memory according to a first mapping relationship between a storage slot of the target memory and a network parameter; and writing, in response to the remaining storage slot meeting a storage requirement of the first target parameter, the first target parameter into the target memory so that a computing core contained in the target processor adjusts the first network parameter according to the first training data.Type: ApplicationFiled: September 27, 2022Publication date: November 28, 2024Inventors: Minxu ZHANG, Haifeng WANG, Fan ZHANG, Xinxuan WU, Xuefeng YAO, Danlei FENG, Zhihua WU, Zhipeng TAN, Jie DING, Dianhai YU