Abstract: In some embodiments, an electronic device receives handwritten inputs in text entry fields and converts the handwritten inputs into font-based text. In some embodiments, an electronic device selects and deletes text based on inputs from a stylus. In some embodiments, an electronic device inserts text into pre-existing text based on inputs from a stylus. In some embodiments, an electronic device manages the timing of converting handwritten inputs into font-based text. In some embodiments, an electronic device presents a handwritten entry menu. In some embodiments, an electronic device controls the characteristic of handwritten inputs based on selections on the handwritten entry menu. In some embodiments, an electronic device presents autocomplete suggestions. In some embodiments, an electronic device converts handwritten input to font-based text. In some embodiments, an electronic device displays options in a content entry palette.

Abstract: This invention relates to a method of improving the convenience and efficiency of services related to the input and output of multiple languages in a mobile environment in a virtual keyboard of a mobile device consisting of an input part, an operation part, and an output part, or a virtual keyboard in a metaverse such as holographic interface or augmented reality simulating the same, based on function buttons arranged around buttons assigned with characters, and language service functions such as speech recognition, speech synthesis, and machine translation functions assigned to the function buttons, by touching said function buttons to cause a plurality of registered input languages or translation target languages to be displayed on an expanded keypad, and selecting a language icon activated on the expanded keypad to determine a language to be used and input, translation, or speech synthesis to be performed in such language.

Abstract: Generating optimization instructions for data processing pipelines is described. A pipeline optimization system computes resource usage information that describes memory and compute usage metrics during execution of each stage of the data processing pipeline. The system additionally generates data storage information that describes how data output by each pipeline stage is utilized by other stages of the pipeline. The pipeline optimization system then generates the optimization instructions to control how memory operations are performed for a specific data processing pipeline during execution. In implementations, the optimization instructions cause a memory system to discard data (e.g., invalidate cache entries) without copying the discarded data to another storage location after the data is no longer needed by the pipeline. The optimization instructions alternatively or additionally control at least one of evicting, writing-back, or prefetching data to minimize latency during pipeline execution.

Abstract: A request is received to upgrade firmware for disk array enclosures (DAEs). Each DAE is reachable by a host server using first and second paths. The first path extends from a first port of a first HBA of the host server to each of a set of first input/output modules (IOMs) in the DAEs. The first IOMs have first SAS expanders to which storage disks are connected. The second path extends from a second port of a second HBA of the host server to each of a set of second IOMs in the DAEs. The second IOMs have second SAS expanders to which the disks are connected. The first port is changed from a first state during which a SAS driver exposes all topology change events to an OS of the host server to a second state during which the SAS driver does not expose all of the topology change events.

Abstract: The subject application relates to in-situ compression of data in a main memory and storing of the compressed data in the same main memory to improve memory optimization. A hardware logic of a memory device may receive modified pages from a first portion of memory array, cause a page compression accelerator in the hardware logic to compress the received modified pages to generate compressed data, and facilitate storing of the compressed data to a second portion of memory array of the same memory device. By using in-situ data compression, memory optimization in a computing device is improved.

Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

Abstract: A method for adjusting a specification parameter of a solid-state drive (SSD) includes that the SSD receives a configuration command through an internal configuration interface, where a current specification parameter of the SSD is a first specification parameter, and the configuration command includes representation information of a second specification parameter; and then the SSD adjusts the specification parameter of the SSD from the first specification parameter to the second specification parameter based on the configuration command.

Abstract: A system and method are provided to detect an event corresponding to the system powering up or a storage device being inserted into the backplane. In response to detecting the event, the system obtains configuration information associated with a physical topology of the backplane, the configuration information associated with: a first bus between a storage controller and a redriver; a second bus between the redriver and the storage device; the backplane; and the storage device. The system searches, in a data structure based on the configuration information, for an optimized redriver setting. The system activates, based on the optimized setting, the redriver by enhancing signals sent via the second bus to the storage device and by enhancing signals sent via the first bus to the storage controller, thereby facilitating enhancement of signal integrity between the storage components in the backplane.

Abstract: In an embodiment of the disclosed technology, a host device may control an operation of writing data to a plurality of types of memory cells included in a memory, through booster logic units respectively corresponding to the plurality of types of memory cells, and a timing thereof. It is possible to prevent performance of a device from degrading due to differences in characteristics of operations in which data are written to the plurality of types of memory cells, and improve performance and efficiency of an operation of writing data to a plurality of memory cells.

Abstract: A server includes at least one local memory and communicates with one or more network devices that provide an external shared memory. A kernel space of the server is used to monitor memory usage by different applications executed by the server. A memory kernel module adjusts usage of the at least one local memory and the external shared memory by the different applications based at least in part on the monitored memory usage. In another aspect, a memory access profiling server receives memory information and application usage information added to packets sent between servers and one or more memory devices. The memory access profiling server analyzes the memory information and application usage information to determine memory placement information that is sent to at least one server to adjust usage of the external shared memory.

Abstract: Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.

Abstract: A memory device including a first plane group, a second plane group and a multiplexer circuit. The multiplexer circuit is coupled to a first input/output (I/O) interface and a second I/O interface. The multiplexer circuit enables the first I/O interface to access the first plane group and the second plane group and enables the second I/O interface to access the first plane group and the second plane group.

Abstract: A bandwidth control method and a storage device are provided. The bandwidth control method may include: determining a target bandwidth expected when an application uses a storage device; calculating a bandwidth difference between the target bandwidth and an allocation bandwidth allocated to the application by the storage device; and adjusting the allocation bandwidth to the target bandwidth based on the bandwidth difference.

Abstract: Systems and methods for dynamic throttling of input/output queues in data storage device arrays are described. Data storage devices are connected through the slots and corresponding lanes of a storage interface switch. A storage controller uses a delay inserted between host submission queues and backend submission queues to manage the priority of host storage commands using slot groups.

Abstract: A system is disclosed. The system may include a processor, a first memory connected to the processor, and a second memory connected to the processor. A data structure may include an entry, which may identify that a data is stored in a location. The location may include one of the first memory or the second memory.

Abstract: A cloud computing system includes cloud orchestrator circuitry and fabric manager circuitry. The cloud orchestrator circuitry receives an input application and determines a task graph, a data graph, and a function popularity heap parameter for the input application. The task graph comprises an indication of function interdependency of functions of the input application, the data graph comprises an indication of data interdependency of the functions, and the function popularity heap parameter corresponds to a re-usability index for the functions. The fabric manager circuitry allocate a first programmable integrated circuit (IC) device to perform a first function of the input application based on the task graph, the data graph, and the function popularity heap parameter.

Abstract: An apparatus is provided that includes a memory array and a control circuit. The memory array includes non-volatile memory cells each including a resistive random access memory element. The control circuit is configured to receive a read command that specifies an address of a first group of the non-volatile memory cells, use a first predetermined read reference value to perform a first read of the first group of the non-volatile memory cells to provide first read data, while performing the first read, retrieve from a memory a second predetermined read reference value corresponding to the specified address, and in response to a condition being satisfied regarding the first read data, use the second predetermined read reference value to perform a second read of the first group of the non-volatile memory cells to provide second read data.

Abstract: A memory system is included in a host device. The memory system incudes: a volatile memory device that performs self-refresh until the host device turns on duty when detecting that the host device is off duty; a non-volatile memory device; and a processor that controls a read operation or a write operation of the volatile memory device and the nonvolatile memory device. The processor backs up data stored in the volatile memory device to the non-volatile memory device after a first time period elapses from when the host device is off duty. The volatile memory device stops the self-refresh after a second time period elapses from a time point when the data stored in the volatile memory device is backed up to the nonvolatile memory device.

Abstract: A computer-implemented method of operating on a program is disclosed which includes executing at least one instruction towards method of operating a program, the execution includes receiving request for input data associated with at least one dataset; at run time determining if the input data associated with the at least one dataset is resident on memory of one or more processors of a second class (Class2 Processors), if the associated data is resident on the memory of at least one or more processors of a first class (Class2 Processors) and not resident on the memory of the Class2 Processors, i) retrieving only the associated input data from the memory of the Classi Processors, ii) copying the associated input data onto the memory of the Class2 Processors, iii) using the retrieved input data in the execution of the at last one instruction, and iv) generating output data.

Abstract: A method for execution by one or more computing devices includes generating current slice integrity check value information for a rebuilt appended encoded data slice of a set of appended encoded data slices stored in a set of storage units of the storage network, where an appended encoded data slice of the set of appended encoded data slices includes an encoded data slice of a set of encoded data slices and slice integrity check value information for the encoded data slice. The method further includes determining the current slice integrity check value information compares favorably to the slice integrity check value information to produce a trusted rebuilt appended encoded data slice. When the current slice integrity check value information compares favorably to the slice integrity check value information, the method further includes storing the rebuilt appended encoded data slice as the trusted rebuilt appended encoded data slice.

Abstract: A method to perform data scrub operations by operating a memory device, the memory device comprising a main memory, an internal Error Correction Code (ECC) engine and a scrub memory. The method comprising: receiving a read command; accessing, based on the receiving the read command, a location in the main memory to read data at the location; error correcting data read during the accessing; and storing at the scrub memory information of the location based at least in part on the correcting the data meeting or exceeding an ECC threshold.

Abstract: Provided are a computer program product, system, and method for generating data protection directives to provide to a storage controller to control access to data in cache. A data protection directive is generated for a data subset indicating access request type and a protective action with respect to the access request type for the data subset. The data protection directive is transmitted to the storage controller. The storage controller includes the data protection directive in metadata for the data subset. The data protection directive causes the storage controller to perform the protective action in response to an access request of the access request type to a portion of the data subset.

Abstract: Data movement for reducing an environmental load in a hierarchical storage is appropriately determined. A storage system includes an upper-level storage device and a management device. The management device is configured to determine, for each file stored in the upper-level storage device, based on a size of a target file and an access frequency of the target file, and the power consumption information, whether power consumption for holding the target file is to be reduced by moving the target file to the lower-level storage device, and output, when it is determined that the power consumption for holding the target file is to be reduced by moving the target file to the lower-level storage device, an instruction to move the target file from the upper-level storage device to the lower-level storage device.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support row-selective self-refresh operation while a host processor is in sleep mode. In a first aspect, a method of operating a memory system by a memory controller includes receiving, from the host device through the channel, a hash filter indicating a first subset of rows in a memory array; and refreshing, by the memory controller, a second subset of rows in the memory array based on the hash filter. The hash filter may be a Bloom filter, a Cuckoo filter, a linear probing filter, or a XOR filter. Other aspects and features are also claimed and described.

Abstract: A storage device may include a memory and a controller. The memory may include a plurality of memory units. The controller may transmit a read command for a target memory unit among the plurality of memory units to the memory, read a state value from the memory after transmitting the read command to the memory, and determine that all bits of data stored in the target memory unit are 1 when the state value is a first value, and determine that all bits of the data stored in the target memory unit are 0 when the state value is a second value.

Abstract: Methods, systems, and devices for power management techniques are described. A memory system may receive a command to exit a first power mode and enter a second power mode. The first power mode may have a lower power consumption than the second power mode. The memory system may determine whether a duration of an idle period associated with the first power mode satisfies a threshold based on receiving the command to exit the first power mode. The memory system may receive another command associated with executing a flush operation and perform one or more power management operations based on receiving the command and determining that the duration satisfies the threshold.

Abstract: Systems and methods are described herein for an efficient storage layout of recorded content associated with a particular user. Content segments, unique to the user and encoded/transcoded at different bit rates, may be stored/partitioned based on the likelihood of a particular bit rate version of content being requested by the user and a duration of playback for the content segment. Content that is more frequently requested may be concatenated in a single storage location on more high performance hardware. Further, content that is played back for a longer duration of playback may also be grouped together and stored on more high performance hardware. Content that is more likely to be played for only a short time may be stored within a plurality of storage containers.

Abstract: This application provides a memory defragmentation method performed by a computer device. The method includes: obtaining n idle blocks before a tail idle block in a memory of a graphic processing unit, the tail idle block located at a head of remaining unallocated idle blocks in the memory, and n being a positive integer; obtaining tail non-idle blocks in the memory, the tail non-idle blocks comprising one allocated block or a plurality of continuous allocated blocks immediately before the tail idle block in the memory; determining one or more target idle blocks in the n idle blocks, a size of the target idle block being not less than a size of the allocated blocks among the tail non-idle blocks; migrating data in the tail non-idle blocks to the target idle blocks; and updating the head of remaining unallocated idle blocks in the memory by releasing the tail non-idle blocks.

Abstract: A processing device in a memory sub-system determines a total power-off time of a memory sub-system and identifies a configurable power-off time threshold for the memory sub-system. The processing device determines whether the total power-off time satisfies a threshold criterion based on the configurable power-off time threshold, responsive to determining that the total power-off time satisfies the threshold criterion, causes the memory sub-system to enter a relaxed block retirement mode of operation.

Abstract: A memory system includes a volatile memory, a nonvolatile memory, and a controller. The controller is configured to set a block group of the nonvolatile memory to be in a writable state and generate in the volatile memory a list associated with the block group. The controller is configured to, with respect to a write command, add an entry to the list, which includes a first address of a host and a second address of the volatile memory, obtain the write data from the first address of the host and store the write data in the second address of the volatile memory, write the write data stored at the second address of the volatile memory into the block group, and upon the block group being fully written, set the block group to be in a non-writable state and dissociate the list from the block group.

Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to perform a write operation on the non-volatile memory in response to a write command from a host by writing system data in a first mode to a first block of the non-volatile memory, the first mode being a write mode for writing data with a first number of bits per memory cell, writing user data in the first mode to a second block of the non-volatile memory when the write command is of a first type, and writing user data in a second mode to a third block of the non-volatile memory when the write command is of a second type. The second mode is a write mode for writing data with a second number of bits larger than the first number of bits per memory cell.

Abstract: A data partitioning and processing method having the following steps: receiving a partitioned storage capacity sent by each storage node in a distributed storage system; wherein the partitioned storage capacity is a storage capacity of each partition included in the storage node; determining a storage capacity of an i-th rolling block according to the partitioned storage capacity; determining whether the storage capacity of the i-th rolling block meets a preset condition according to the storage capacity of the i-th rolling block; creating an (i+1)-th rolling block in response to the fact that the storage capacity of the i-th rolling block meets a preset condition; splitting the (i+1)-th rolling block into N partitions on average; and establishing a mapping relationship between N partitions in the (i+1)-th rolling block and storage nodes in the distributed storage system, so that the storage node writes data into the partitions according to the mapping relationship.

Abstract: Systems and methods are provided for bringing a volume of a consistency group (CG) into an in-synchronization (InSync) state while other volumes of the CG remain in the InSync state. According to an example, in order to support recovery from disruptive events in a manner that ensures a zero recovery point objective (RPO) guarantee and insulates an application making use of the CG from adverse impacts, responsive to a triggering event, a Fast Resync process may first be attempted to promptly bring an affected volume back into an in-synchronization (InSync) state from an out of synchronization (OOS) state while allowing other members of the CG to remain in the InSync state. Should the Fast resync process be unsuccessful in bringing the volume back into the InSync state within a predetermined or configurable time threshold, then a second type of resynchronization process may be employed at the CG level.

Abstract: A cluster of one or more computing devices is operably coupled to a plurality of storage devices. Each computing device in the cluster comprises a frontend and a backend. The backend comprises a plurality of buckets. Each bucket is operable to build a failure-protected stipe that spans two or more of the plurality of the storage devices. A file system comprises one or more failure-protected stipes. A client other than the one or more computing devices in the cluster is operable to access at least a portion of the file system via a stateless mount string comprising a cryptographically-signed key.

Abstract: A distributed storage system includes one or multiple proxies, a metadata store, multiple agents, and multiple data repositories, which provisions storage space within a cloud or a cloud region from one or multiple cloud storage services. A proxy encodes data objects to generate coded chunks for fault tolerance and security, stores coded chunks in data repositories via agents, and persists the states and metadata of data objects in the metadata store. An agent manages the coded chunks in one or multiple data repositories and encodes coded chunks during data repair. The system utilizes data processing and management methods for improved data repair and management, including (i) hierarchical data repair for reducing both the cross-cloud network bandwidth usage and the data repair time, (ii) various data management configurations across objects, and (iii) extensions for new data management mechanisms and new cloud storage services.

Abstract: A storage device includes: a non-volatile memory device; and a storage controller for receiving a first Protocol Information unit (PIU) including a first merge message from an external device, and performing, based on the first PIU, at least one of a sense operation of reading first data stored in a memory block of the non-volatile memory device and a select operation of storing, in the memory block, second data received from the external device. The first PIU includes a basic header segment commonly included in PIUs transmitted/received between the external device and the storage controller, and a first Extra Header Segment (EHS) including the first merge message.

Abstract: A memory device includes a memory array configured as quad-level cell (QLC) memory and a control logic operatively coupled to the memory array. The control logic identifies a first two bits of particular pages of a QLC logical state. The control logic causes memory cells of the memory array to be coarse programmed with a threshold voltage distribution of a multi-level cell (MLC) logical state corresponding to the first two bits. The control logic reads the MLC logical state from the memory cells and a second two bits from a cache buffer to determine the QLC logical state. The control logic causes the memory cells to be further coarse programmed with a QLC threshold voltage distribution corresponding to the QLC logical state.

Abstract: Implementations described herein relate to memory device background operations. In some implementations, a memory device may receive a background operation command, from a host device, that indicates for the memory device to initiate a background operation for a memory of the memory device. The background operation command may include at least one of an optimization indicator, an idle time indicator, or a power-off time indicator. The memory device may initiate the background operation in accordance with the background operation command.

Abstract: A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.

Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

Abstract: A memory module supports multiple memory channel modes, each including a double-date-rate (DDR) data channel supported by an independent command-and-address (CA) channel. In a two-channel mode, the memory module supports two DDR data channels using two respective DDR CA channels. Each CA channel includes a corresponding set of CA links. In a four-channel mode, the memory module supports two pairs of DDR data channels, each pair supported by a pair of independent CA channels. Memory commands issued in the four-channel mode are time interleaved to share one of the sets of CA links.

Abstract: System and techniques for host-preferred memory operation are described herein. At a memory-side cache of a memory device that includes accelerator hardware, a first memory operation can be received from a host. A determination that the first memory operation corresponds to a cache set based on an address of the first memory operation is made. A second memory operation can be received from the accelerator hardware. Another determination can be made that the second memory operation corresponds to the cache set. Here, the first memory operation can be enqueued in a host queue of the cache set and the second memory operation can be enqueued in an internal request queue of the cache set. The first memory operation and the second memory operation can be executed as each is dequeued.

Abstract: Provided are systems, methods, and apparatuses for managing functions for storage devices. The method can include: determining one or more functions associated with a first device and determining one or more corresponding function types for the functions; grouping the functions based on the function types using a group name; and providing the group name to a second device for use in connection with an associated application, wherein the storage device comprises a computational storage (CS) device.

Abstract: A request is received to upgrade firmware for disk array enclosures (DAEs). Each DAE is reachable by a host server using first and second paths. The first path extends from a first port of a first HBA of the host server to each of a set of first input/output modules (IOMs) in the DAEs. The first IOMs have first SAS expanders to which storage disks are connected. A flag is set in firmware of each first IOM that causes SMP and SES protocol services of a DAE to mark each respective storage disk connected to each respective SAS expander of the first SAS expanders as vacant. During the firmware upgrade, advertising to a SAS driver topology change events indicating that a storage disk has been removed or added is withheld based on the flag.

Abstract: An information processing apparatus including a storage which stores an application capable of supporting a print setting corresponding to a device in cooperation with a printer driver and a controller which obtains device information of the device associated with the application when the application is activated, in which the controller stores the print setting corresponding to the device in the storage on the basis of the obtained device information and reflects the print setting stored in the storage at print execution on the basis of the application.

Abstract: An image forming system includes a hardware processor that determines an image formation condition for each of a plurality of image forming apparatuses based on sheet characteristic information corresponding to a characteristic of a sheet acquired from each of the plurality of image forming apparatuses.

Abstract: A processing apparatus includes circuitry to set a value on a device-independent color space as a first color reproduction target value of mixed color, obtain, as a calibration target, a second color reproduction target value of mixed color in a printing environment where the first color reproduction target value is set, and adjust a correction parameter to be applied in the printing environment in a case that a calibration is updated, so as to correct a color difference between the first color reproduction target value and the second color reproduction target value using the correction parameter.

Abstract: An information processing apparatus incudes at least one memory and at least one processor configured to cause a display device to display an image indicated by image data; accept a change in an original size of the image displayed on the display device; in a case where a change from a first original size to a second original size that is different from the first original size in an aspect ratio has been accepted as the change, change a layout of an object included in the image data based on the second original size; and cause the display device to display the image in the second original size based on the object whose layout has been changed.

Abstract: An information processing system includes one or more processors configured to: accept that a user registers print information serving as a print target and an information processing terminal serving as a transfer destination of the print information; in transferring the registered print information to the registered information processing terminal, perform a first transfer operation that transfers a first portion of the print information to the information processing terminal; and if the information processing terminal serving as the transfer destination is verified as being an information processing terminal of a regular user after the first transfer operation, perform a second transfer operation that transfers a second portion of the print information to the information processing terminal.